KR101667400B1 - Apparatus and method for generating and detecting single event upset - Google Patents

Apparatus and method for generating and detecting single event upset Download PDF

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KR101667400B1
KR101667400B1 KR1020150063179A KR20150063179A KR101667400B1 KR 101667400 B1 KR101667400 B1 KR 101667400B1 KR 1020150063179 A KR1020150063179 A KR 1020150063179A KR 20150063179 A KR20150063179 A KR 20150063179A KR 101667400 B1 KR101667400 B1 KR 101667400B1
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register
seu
detection
fault
failure
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KR1020150063179A
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Korean (ko)
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박정태
강동수
오대수
남명용
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루미르 주식회사
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0766—Error or fault reporting or storing
    • G06F11/0772—Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers

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  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

An embodiment of the present invention relates to an apparatus and a method for generating and detecting a single event upset (SEU). The apparatus for generating and detecting the SEU according to an embodiment of the present invention comprises: a memory device comprising at least one register and a hamming code controller for generating SEU detection data by detecting the errors of the register when the SEU generates in the register; and a fault manage module which experimentally generates the SEU in the register and records the generation of the SEU in the register by receiving the SEU detection data. The fault manage module comprises a fault inject register which stores the map address of the target register among the at least one register, and the fault inject register generates the SEU in the target register that the map address instructs. The present invention is designed to provide an apparatus and a method for generating and detecting the SEU which can experimentally generate and detect the SEU in a real cosmic radiation not in a space place.

Description

Field of the Invention [0001] The present invention relates to a single event upset (SEU)

An embodiment of the present invention relates to an SEU generation and detection apparatus and method.

Since the first upset phenomenon in the space environment, the importance of error recovery systems in semiconductor equipment has become increasingly important. As a result, studies have been continuing to perform missions continuously without being affected by errors (failures) in the integrated circuits (ICs) in high-radiation environments such as space mission and high energy physics experiments .

The cosmic radiation environment can have a serious impact on the satellite's electronic system, especially when the sun's explosion occurs, the enormous amounts of protons, alpha particles, and heavy ions that are strong electromagnetic waves and high energy particles are emitted. Since these energies are strong enough to reach hundreds of meV, when these high energy particles come into contact with the satellites, the particles penetrate the satellites and cause disturbances and errors in various electronic equipments mounted on the satellites. This phenomenon is referred to as a single event effect (SEE).

If this phenomenon continues, not only the performance of the satellite but also the power efficiency of the solar cell, which is the energy production device of the satellite, is deteriorated, which causes a serious obstacle to the performance of the satellite. Also, depending on the energy level of the particles that collide with the satellites, the SEE will cause the data to change or change. The main concern here is a Single Event Upset (hereinafter referred to as 'SEU') in which bits of memory are inverted due to data changes.

Field programmable gate arrays (FPGAs) are programmable non-memory semiconductors that, unlike conventional semiconductors that can not change their circuit, can be recoded for their intended use. Therefore, the user can modify the function of the semiconductor as if it is a software program according to his / her purpose.

Satellite systems use FPGA devices primarily for high performance and high integration requirements. Registers that store data in FPGAs used in satellite systems are protected by Hamming Code.

The satellite system uses a single error correction (SECDED) method that can recover one bit error for each register and detect only two or more bit errors.

The SECDEC method is suitable because it requires more information to increase the error recovery rate, which increases the additional memory capacity and increases the power consumption.

In the FPGA, if a register protected by a Hamming code generates an SEU by cosmic radiation, one bit error can be detected and corrected by a Hamming code, but two or more bit errors can only be detected.

In the current satellite system related technology, it is not known how the SEU caused by actual cosmic radiation affects the entire satellite system until the SEU is generated in the register by the actual cosmic radiation, It is difficult to accumulate the amount of SEU generated.

It is an object of the present invention to provide an SEU generation and detection apparatus and method capable of experimentally generating and detecting SEUs by actual cosmic radiation in a place other than the outer space .

The solution of the present invention is not limited to those mentioned above, and other solutions not mentioned can be clearly understood by those skilled in the art from the following description.

An SEU generation and detection apparatus according to an embodiment of the present invention includes a register for generating SEU detection data by detecting an error in the register when at least one register and a single event upset (SEU) A memory device including a code controller and a Fault manage module that empirically generates the SEU in the register and receives the SEU detection data and records that the SEU has been generated in the register. According to the SEU generation and detection apparatus according to this embodiment, it is possible to experimentally generate and detect SEU occurrence in a place other than the actual space, and to confirm how the satellite system affects the SEU.

In the SEU generation and detection apparatus, the fault management module includes a fault injection register for storing a map address of the register, a type of the SEU, and the number of occurrences of the SEU; And a fault detection register for storing the type of the SEU and the number of detection of the SEU from the SEU detection data. According to the SEU generation and detection apparatus, the register to generate the SEU can be selected, the type of the SEU can be selected, and the influence of the satellite system by the SEU can be confirmed in a manner desired by the designer by accumulating the number of SEU occurrences.

The SEU generation and detection apparatus according to claim 1, further comprising a monitoring module for monitoring the fault management module, wherein the register is a plurality, the fault insertion register generates an SEU in each of the plurality of registers, Wherein the failure detection register accumulates and records the type of the SEU and the detection count of the SEU in each of the plurality of registers, and the monitoring module records the type of the SEU recorded in the failure detection register It is possible to read the detection count of the SEU, read the address of the register stored in the failure insertion register, and detect the last register of the SEU among the plurality of registers. According to such an SEU generation and detection apparatus, the number of failure detection registers is independent of the number of registers, and the number of failure detection registers can be reduced to reduce the number of logic circuits used. Therefore, there is an advantage that the data capacity of the SEU generation and detection apparatus can be drastically reduced.

In the SEU generation and detection apparatus, the number of the failure detection registers corresponds to the number of the registers, and the failure detection register can correspond to the registers one to one. According to such an SEU generation and detection apparatus, SEU generation and detection can be easily performed for each register.

In the SEU generation and detection apparatus, the fault management module may further include an arm wrapper for connection with the AMBA. According to such SEU generation and detection apparatus, it is possible to perform high-speed communication with an external apparatus and to easily operate.

In the SEU generation and detection apparatus, the failure insertion register may store whether or not the entire memory device is reset. According to such SEU generation and detection apparatus, it is possible to reset all the memory elements connected to the fault management module.

In the SEU generation and detection apparatus, the failure insertion register may store the number of resets of the register from the SEU detection data. According to the SEU generation and detection apparatus, when the SEU corresponding to the double error is generated in the register, there is an advantage that the number of resets of the register can be confirmed.

An SEU generation and detection method according to an embodiment of the present invention is a SEU generation and detection method of a SEU generation and detection apparatus including a memory element including at least one register and a Hamming code controller and a fault management module, The management module empirically generating an SEU in the register; The Hamming code controller detecting an error in the register and generating SEU detection data; And the fault management module receiving the SEU detection data and recording that the SEU has been generated in the register. According to this SEU generation and detection method, SEU generation is experimentally generated in a place other than the actual space, and it can be detected to confirm how the satellite system affects SEU.

The SEU generation and detection method may further include a monitoring module for monitoring the fault management module, wherein the monitoring module checks the occurrence of the SEU recorded in the fault management module . According to the SEU generation and detection method, there is an advantage that the generation of the SEU recorded in the failure management module can be easily provided to the user.

The use of the SEU generating and detecting apparatus according to the embodiment of the present invention has an advantage that SEU generation is experimentally generated at a place other than the actual space and it is detected that the satellite system is affected by the SEU .

1 is a block diagram of an SEU generation and detection apparatus according to an embodiment;
2 shows the structure of the fault insertion register 310 shown in FIG.
3 shows the structure of the fault detection register 330 shown in Fig.
4 is a block diagram showing an example of an overall system including the SEU generating and detecting device 10 shown in Fig.
5 is an actual logic circuit diagram in which the fault management module 300 of the SEU generation and detection apparatus 10 shown in FIG. 1 generates an SEU in the register 110 of the memory device 100. FIG.
6 is an actual logic circuit diagram for detecting an SEU generated in the register 110 in the fault management module 300 of the SEU generation and detection apparatus 10 shown in FIG.
7 is a flowchart for explaining a method of generating and detecting an SEU in an SEU generating and detecting apparatus according to an embodiment of the present invention shown in Fig.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a detailed description of preferred embodiments of the present invention will be given with reference to the accompanying drawings. It should be noted that in the drawings, the same reference numerals and the same elements are denoted by the same reference numerals even though they are shown on different drawings. In the following description, well-known functions or constructions are not described in detail to avoid unnecessarily obscuring the subject matter of the present invention.

Hereinafter, a single event upset (SEU) generation and detection apparatus according to an embodiment of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram of an SEU generation and detection apparatus according to an embodiment.

Referring to FIG. 1, an SEU generation and detection apparatus 10 according to an embodiment includes a memory device 100, a fault manage module 300, and a monitoring module 500 can do.

The memory element 100 is an element storing predetermined data necessary for the operation of the SEU generation and detection apparatus 10. [ For example, the memory device 100 may be one of an 8051-FT, a block RAM, and an error detection and correction (EDAC).

Within the SEU generation and detection device 10, the memory device 100 may be multiple. As shown in Figure 1, n memory devices 100 may be located within the SEU generation and detection device 10. [

One memory device 100 may include at least one register 110. [ The register 110 may be a single register or a plurality of registers, depending on the type and function of the memory device 100. 1, the memory device 100 includes n registers 110, but the present invention is not limited thereto. The memory device 100 may include one register 110.

The memory device 100 may include a Hamming code controller 150.

The Hamming code controller 150 may encode data to be stored in the register 110 with a Hamming code and store the encoded data in the register 110. [ In addition, the hamming code controller 150 may detect the error of the data stored in the register 110 using the Hamming code, or may correct the detected error to restore the error data to the original state. Here, an error in the register 110 may mean that the bit string stored in the register 110 is changed by the fault management module 300 or by cosmic radiation. In other words, an error in the register 110 may mean that an SEU has been generated in the register 110.

When the SEU is generated in the register 110, the Hamming code controller 150 can generate 'SEU detection data' and output the generated SEU detection data to the fault management module 300.

Here, the SEU detection data may include information indicating that an error has been detected in the register 110 and information indicating that the error has been recovered. Here, the Hamming code controller 150 can detect a single error (single error) by using a Hamming code, but can detect only a two-bit error (double error) Therefore, when an error is detected and recovered, the SEU is a single error, and the error is detected only when the SEU is a double error. The SEU detection data may also include the reset information of the register 110 when the SEU corresponding to the double error of the register 110 is generated.

The fault management module 300 may be located within the SEU generation and detection device 10. [ The fault management module 300 may control the memory device 100 disposed within the SEU generation and detection device 10. [ Here, the fault management module 300 may be a generic fault management module that can integrally and wholly control a plurality of memory devices 100 disposed within the SEU generation and detection apparatus 10. [ This SEU generation and detection apparatus according to the embodiment of the present invention has an advantage that one memory module 100 in the SEU generation and detection apparatus 10 can be controlled using one fault management module 300 have.

The fault management module 300 may change the data stored in the register 110 in the memory device 100. [ Specifically, the fault management module 300 may change one or two or more bits of the bit string stored in the register 110. The fault management module 300 may experimentally change the state as if the register 110 was actually generated by cosmic radiation in space. Thus, using this fault management module 300, it is possible to experimentally generate an SEU in the register 110 of the memory device 100 in a non-space. Thus, it can be experimentally confirmed in advance whether the memory device 100 can perform its function normally in space.

The fault management module 300 may receive SEU detection data from the memory device 100 and record that the SEU has been generated in the register 110. [ Here, the SEU detection data may be received from the hamming code controller 150 of the memory device 100.

The fault management module 300 may include a fault injection register 310, a fault detection register 330, and a fault controller 350.

The fault insertion register 310 may change the data stored in the register 110 of the memory element 100. [ That is, the failure insertion register 310 may change one or two or more bits of the bit string stored in the register 110. [ The scheme of the failure insertion register 310 will be described in detail with reference to FIG.

FIG. 2 shows a structure of the failure insertion register 310 shown in FIG.

Referring to FIG. 2, the failure insertion register 310 may store a map address of a target register. The fault insertion register 310 may generate the SEU in the target register 110 of any memory device 100 in the SEU generation and detection device 10. [ Using this fault insertion register 310, the designer can arbitrarily select the target register from which the SEU is to be generated. Specifically, the designer can select the target register for which to generate the SEU by writing the map address (0x00 or 0x01) of the target register in the failure insertion register 310. [ Then, the failure insertion register 310 can generate the SEU in the selected target register. Here, the map address of the target register can be written between the 31st bit stream in the 24th bit stream.

The fault insertion register 310 may store the type of the SEU. Specifically, the failure insertion register 310 may store information on whether to cause a single error or a double error to be generated in the target register. Using this fault insertion register 310, the designer can select whether the SEU corresponding to the single error or the double error is generated in the target register. Here, a single error may be written in the 0th bit string (ISE), and a double error may be written in the 1st bit string (IDE).

The failure insertion register 310 may store the number of SEU occurrences. The fault insertion register 310 may store information on how many times the SEU is to be generated in the target register. Using this fault insertion register 310, the designer can set the SEU to occur more than once in the target register. Here, the number of times of generating the SEU may be recorded in the 16th bit string to the 23rd bit string (FIC).

The failure insertion register 310 can store whether an SEU has occurred or not. Specifically, the failure insertion register 310 can control generating the SEU in the target register. Irrespective of whether the designer has written the map address of the target register, the number of occurrences of the SEU, and the type of the SEU in the fault insertion register 310, the fault insertion register 310 may cause the target register to generate the SEU, Can be controlled. Even if the map address of the target register, the number of occurrences of the SEU, and the type of the SEU are recorded in the failure insertion register 310, the failure insertion register 310 outputs the 8th If 0 is written in the bit string CI, SEU is not generated. On the other hand, if 1 is recorded in the 8th bit stream (CI) in the failure insertion register 310, SEU is generated.

The fault insertion register 310 may store whether or not the entire memory device is reset. Resetting the whole system may mean resetting all the memory devices 100 connected to the fault management module 300 shown in FIG. Here, the reset can be written in the 11th bit stream FR.

The fault insertion register 310 can provide a scrubbing function. This function may cause the memory element 100 to perform scrubbing per clock. Here, the scrubbing function can be recorded in the ninth bit stream SS.

The failure insertion register 310 may record the number of times the target register 110 is reset if the SEU to be generated in the target register is a double error. Whether or not the target register has been reset can be ascertained through the SEU detection data received from the memory element 100. Here, the reset number of the target register may be written between the 12th bit stream and the 15th bit stream (RC).

The fault insertion register 310 may include an 'Error Interrupt Flag' function. The error interrupt flag function records the SEU in the target register when it is generated, and can be a function that notifies the designer that the SEU has been generated in the target register. Whether or not an SEU has occurred in the target register can be confirmed through the SEU detection data received from the memory device 100. [ Here, the error interrupt flag function of the target register can be written in the tenth bit string (EI).

Some bit strings in the failure insertion register 310 shown in Fig. 2 can be protected by a Hamming code. Specifically, the 8th bit stream (CI), the 9th bit stream (SS), the 10th bit stream (EI), the 11th bit stream (FR) It can be protected by code. This is because the failure insertion register 310 itself can generate an SEU by cosmic radiation, so that the portion containing important information is protected by the Hamming code. To this end, the fault management module 300 may include a hamming code controller 370, as shown in FIG.

1, the fault detection register 330 may record that the SEU has been detected in the register 110 upon receipt of the SEU detection data from the memory device 100. [ The structure of the fault detection register 330 will be described in detail with reference to FIG.

FIG. 3 shows a structure of the failure detection register 330 shown in FIG.

Referring to FIG. 3, the fault detection register 330 can record the type of the SEU from the SEU detection data from the memory device 100 shown in FIG. Specifically, it is possible to record whether the SEU is a single error or a double error. Here, detection of a single error is recorded in the 0th bit stream SEC, and detection of a double error can be recorded in the 1st bit stream DED.

In addition, the failure detection register 330 may record the number of times of detection of a single error (or a double error) from the received SEU detection data. Here, the number of times of detection of the single error is recorded in the SEFDC between the 31st bit stream and the 16th bit stream, and the number of times of detection of the double error can be recorded in the 15th bit stream DEFDC in the 8th bit stream.

The fault detection register 330 may correspond to the register 110 of the memory device 100 on a one-to-one basis. That is, the number of the failure detection registers 330 may correspond to the number of the registers 110. The case where the fault detection register 330 exists for each of the registers 110 is referred to as a 'normal mode'. The failure detection register 330 in the normal mode records that the SEU is generated in the register 110 of the memory element 100 and records the number of times the SEU has been generated for a predetermined period, It can be accurately determined whether the register 110 of the device 100 is vulnerable to the SEU and whether the data stored in the register 110 of the memory device 100 is correctly restored or reset when the SEU is generated.

On the other hand, only one fault detection register 330 can exist regardless of the number of the registers 110. [ In this way, the case where the fault detection register 330 is one is referred to as a so-called 'simple mode'.

Since the number of the failure detection registers 330 is one, rather than a plurality, as compared with the failure detection register 330 in the normal mode, Can be reduced compared to the failure detection register 330. Therefore, the FPGA device including the failure detection register 330 in the simple mode has an advantage that the data capacity can be drastically reduced.

Since one failure detection register 330 in the simple mode can record the number of SEU occurrences and the occurrence of SEUs of all the registers 110 in which the SEU has been generated, You can see how many SEUs have occurred in the registers or what SEUs have occurred.

Referring again to FIG. 1, the fault controller 350 may control the fault insertion register 310 and the fault detection register 330. Specifically, the fault controller 350 can generate an SEU in the register 110 of the memory device 100 based on the data stored in the fault insertion register 310. [ In addition, when the SEU detection data is received from the memory device 100, the failure controller 350 may analyze the received SEU detection data and store the information in the failure insertion register 310 and the failure detection register 330. [ This fault controller 350 may be a finite state machine (FSM).

The monitoring module 500 monitors the fault management module 300. Specifically, the monitoring module 500 can access the fault management module 300 and read the data stored in the fault management module 300. For example, the monitoring module 500 may read the data stored in the failure insertion register 310 and / or the failure detection register 330 and provide the data to the user.

1, the monitoring module 500 may be included in the SEU generation and detection apparatus 10 according to the embodiment, but the present invention is not limited thereto. Is present outside the detecting device 10 and can be connected to the SEU generating and detecting device 10 by a bus.

4 is a block diagram showing an example of an overall system including the SEU generating and detecting device 10 shown in FIG.

The SEU generation and detection apparatus 10 includes a memory element 8051-FT 100 and a fault management module 300.

4, an SEU generation and detection apparatus 10 according to an embodiment of the present invention includes a user terminal 30 (for example, a microprocessor or the like) through an Advanced Microcontroller Bus Architecture (AMBA) and a Universal Asynchronous Receiver / Transmitter ). It can also be connected via USB or Ethernet.

The AMBA may include an Advanced High-performance Bus (AHB) and an Advanced Peripheral Bus (APB). The AHB connects the 8051-FT 100, the AHB UART, and the APB bridge, and the APB connects the fault management module 300 and the APB bridge.

The fault management module 300 of the SEU generation and detection apparatus 10 according to the embodiment of the present invention may include an APB wrapper to be connected to the APB. Further, the 8051-FT 100 of the SEU generation and detection apparatus 10 according to the embodiment of the present invention may include an APB-3 wrapper and an AHB wrapper to be connected to the AHB.

The 8051-FT 100 of the SEU generation and detection apparatus 10 according to the embodiment of the present invention can be connected to each other through an EEPROM, an SRAM, and a bus (BUS).

5 is an actual logic circuit diagram showing that the fault management module 300 of the SEU generation and detection apparatus 10 shown in Fig. 1 generates an SEU in the register 110 of the memory element 100. Fig.

6 is an actual logic circuit diagram showing the detection of the SEU generated in the register 110 in the fault management module 300 of the SEU generation and detection apparatus 10 shown in FIG.

7 is a flowchart for explaining a method of generating and detecting an SEU in the SEU generation and detection apparatus according to the embodiment of the present invention shown in Fig.

1 and 7, a method for generating and detecting an SEU in an SEU generating and detecting apparatus according to an embodiment of the present invention shown in FIG. 1 includes generating (410) an SEU, generating (Step 420), writing the SEU (step 430), and verifying the occurrence of the SEU (step 440).

First, an SEU is generated in the register 110 of the memory device 100 (410). The method for generating the SEU in the register 110 may use the failure insertion register 310 having the structure as shown in FIG. The SEU can be generated in the register 110 by changing the data stored in the register 110 according to the data recorded in the failure insertion register 310. [

Next, SEU detection data is generated at memory element 100 (420). SEU detection data is generated in the hamming code controller 150 and may include information that the hamming code controller 150 has detected an error in the register 110 in which the SEU has been generated. The SEU detection data may include information in which the SEU corresponding to a single error or a double error is generated in the register 110 and information in which the register 110 is reset when a double error occurs.

Next, the fault management module 300 records an occurrence of the SEU (430). The fault management module 300 receives the SEU detection data generated in the memory device 100, analyzes the SEU detection data, and records the SEU occurrence in the fault detection register 330. The occurrence of the SEU can be recorded in the failure detection register 330 having the structure shown in FIG. Specifically, it is possible to record how many times the SEU occurred in the failure detection register 330 and what kind of SEU was generated.

Next, the monitoring module 500 confirms the occurrence of the SEU (440). The monitoring module 500 reads the data stored in the fault insertion register 310 and the fault detection register 330 of the fault management module 300 and determines the number of occurrences of the SEU generated in the register 110 and the type of the generated SEU You can confirm it to the user.

On the other hand, when the fault detection register 330 exists for each of the registers 110 (normal mode), if the number of the memory devices 100 is large in the FPGA device 10, the number of the fault detection registers 330 also increases , The data capacity of the FPGA device 10 increases.

In order to solve this problem, only one fault detection register 330 may exist, not for each register 110. If only one fault detection register 330 is present (simple mode), if the monitoring module 500 reads only the data stored in the fault detection register 330, it can not know from which register the SEU was last generated. To this end, the monitoring module 500 can read the address of the target register 110 written in the failure insertion register 310 and determine in which register the SEU was last generated.

The SEU generation and detection apparatus and method according to the embodiments of the present invention can be implemented on a printed circuit board (PCB) using various electronic elements, and can be implemented as a Field Programmable Gate Array (FPGA), a Programmable Logic Device (PLD) (CHIP) using a semiconductor design technique such as a complex programmable logic device and the like.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, It will be understood that various changes and modifications may be made without departing from the spirit and scope of the invention. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

10: SEU generation and detection device
100: memory element
110: Register
150: Hamming code controller
300: Fault Management Module
310: failure insertion register
330: Fault detection register
350: fault controller
370: Hamming code controller

Claims (9)

A memory element including at least one register and a Hamming code controller for detecting an error of the register when a single event upset (SEU) is generated in the register to generate SEU detection data; And
And a Fault manage module that generates the SEU in the register experimentally and receives the SEU detection data and records that the SEU has been generated in the register,
Wherein the fault management module includes a fault injection register for storing a map address of a target register among the at least one register,
And the fault insertion register generates the SEU in the target register indicated by the map address. The method according to claim 1,
Wherein the failure insertion register stores the type of the SEU and the number of occurrences of the SEU,
Wherein the fault management module includes a fault detection register for storing the type of the SEU and the number of detection of the SEU from the SEU detection data. 3. The method of claim 2,
Further comprising a monitoring module for monitoring the fault management module,
Wherein the register includes a plurality of registers,
Wherein the failure insertion register generates an SEU in each of the plurality of registers,
The fault detection register is one,
Wherein the failure detection register accumulates and records the type of the SEU and the detection count of the SEU in each of the plurality of registers,
The monitoring module reads the type of the SEU recorded in the failure detection register and the detection count of the SEU, reads the address of the register stored in the failure insertion register, and then the SEU of the plurality of registers SEU generation and detection device for detecting the last generated register. 3. The method of claim 2,
Wherein the number of the fault detection registers corresponds to the number of the registers,
Wherein the failure detection register is in one-to-one correspondence with the register. 3. The method of claim 2,
Wherein the fault management module further comprises an arm wrapper for connection with the AMBA. The method according to claim 1,
Wherein the failure insertion register stores whether or not the entire memory device is reset. The method according to claim 1,
Wherein the failure insertion register stores the number of resets of the register from the SEU detection data. A SEU generation and detection method of a SEU generation and detection apparatus, comprising a failure management module including a memory element including at least one register and a Hamming code controller, and a failure insertion register in which a map address of a target register is stored,
The fault management module empirically generating an SEU in a target register indicated by a map address of the target register among the at least one register;
The Hamming code controller detecting an error in the target register and generating SEU detection data; And
The fault management module receiving the SEU detection data and recording that the SEU has occurred in the target register;
/ RTI > 9. The method of claim 8,
Wherein the SEU generation and detection apparatus further comprises a monitoring module for monitoring the fault management module,
Further comprising: the monitoring module verifying the occurrence of the SEU recorded in the fault management module.
KR1020150063179A 2015-05-06 2015-05-06 Apparatus and method for generating and detecting single event upset KR101667400B1 (en)

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CN113744787A (en) * 2021-07-27 2021-12-03 北京空间飞行器总体设计部 SRAM (static random Access memory) type FPGA (field programmable Gate array) user register single event upset fault injection method
KR20220069579A (en) 2020-11-20 2022-05-27 한화시스템 주식회사 Device for preventing circuit damage by cosmic radiation

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KR20180115188A (en) * 2017-04-12 2018-10-22 한국과학기술원 Self-repairing digital device with real-time circuit switching inspired by attractor-conversion characteristics of a cancer cell
KR101939387B1 (en) 2017-04-12 2019-04-11 한국과학기술원 Self-repairing digital device with real-time circuit switching inspired by attractor-conversion characteristics of a cancer cell
KR20190031799A (en) 2017-09-18 2019-03-27 재단법인대구경북과학기술원 Prediction Method of the Information Throughput Change of OBP Satellite Due to Changes of Cosmic Radiation Environment and Prediction Device thereof
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CN113744787A (en) * 2021-07-27 2021-12-03 北京空间飞行器总体设计部 SRAM (static random Access memory) type FPGA (field programmable Gate array) user register single event upset fault injection method
CN113744787B (en) * 2021-07-27 2023-09-08 北京空间飞行器总体设计部 SRAM type FPGA user register single event upset fault injection method

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