CN111599402A - Single event effect test analysis method, device and test system for memory - Google Patents
Single event effect test analysis method, device and test system for memory Download PDFInfo
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Abstract
The application provides a single event effect test analysis method, a single event effect test analysis device and a single event effect test system of a memory, wherein the method comprises the steps of obtaining error data of single event upset in a single event effect test of the memory; based on the error data, carrying out classification recognition on the single event upset generated by the memory according to a preset single event upset classification recognition rule so as to obtain the classification category of the single event upset; and performing data statistical analysis of the single event upset on the memory according to the classification category of the single event upset, and determining the sensitive position of the memory where the single event upset occurs. The method can count the number of single event upsets of the memory under the irradiation environment, and can deduce the sensitive position of the memory where the single event upsets occur from data by combining with classification statistics and analysis of each single event upset. Therefore, irradiation resistance reinforcement and evaluation can be performed on the sensitive position of the memory device, and pertinence is strong.
Description
Technical Field
The present application belongs to the field of irradiation testing technologies, and in particular, to a single event effect test analysis method, apparatus, and test system for a memory, and further, to an electronic device and a storage medium for executing the single event effect test analysis method.
Background
With the development of the aerospace industry, various spacecrafts have also appeared in succession. The space has a radiation environment of high-energy ions, various artificial satellites and spacecrafts can be radiated by solar cosmic rays, silver river cosmic rays and radiation bands, the radiation easily causes damage to electronic components in the satellites or the spacecrafts in different degrees, normal work of the satellites or the spacecrafts is influenced, and space accidents can be caused in serious cases.
The memory is an important component of a satellite electronic system as a data storage carrier. The memory is easy to radiate to generate a single event upset effect, so that the function of the device is failed when data stored by the device is wrong or even serious, and the whole system is failed. This makes it necessary to reinforce and evaluate the memory against irradiation for use in aerospace systems. However, most of the existing memory single-particle test methods can only calculate the single-particle upset cross section, and are difficult to carry out targeted anti-radiation reinforcement and evaluation on the memory device.
Disclosure of Invention
In view of this, the embodiment of the present application provides a single event effect test analysis method, a single event effect test analysis device, a single event effect test analysis system, an electronic device and a storage medium for executing the single event effect test analysis method, which are suitable for single event irradiation test analysis before and after a dynamic memory is reinforced, and can realize targeted irradiation resistance reinforcement and evaluation on a memory device.
A first aspect of an embodiment of the present application provides a single event effect test analysis method for a memory, where the single event effect test analysis method for the memory includes:
acquiring error data of a memory subjected to single event upset in a single event effect test;
based on the error data, carrying out classification recognition on the single event upset generated by the memory according to a preset single event upset classification recognition rule so as to obtain the classification category of the single event upset;
and performing data statistical analysis of the single event upset on the memory according to the classification category of the single event upset, and determining the sensitive position of the memory where the single event upset occurs.
With reference to the first aspect, in a first possible implementation manner of the first aspect, the classification category of the single event upset includes at least one of: the method comprises the following steps of single-event upset of a storage unit, single-event upset of a column address register, single-event upset of a row address register, single-event upset of a mode register and single-event upset of a control module.
With reference to the first possible implementation manner of the first aspect, in a second possible implementation manner of the first aspect, the step of performing classification and identification on the single event upset occurring in the memory according to a preset single event upset classification and identification rule based on the error data to obtain a classification category of the single event upset includes:
identifying the error length of error data corresponding to the single event upset;
comparing the error length with a preset first length threshold, wherein the first length threshold is set as 1 burst read length;
and classifying the single event upset corresponding to the error data into single event upset of a storage unit for the error data with the error length smaller than a preset first length threshold.
With reference to the second possible implementation manner of the first aspect, in a third possible implementation manner of the first aspect, after the step of identifying the error length of the error data corresponding to the single event upset, the method further includes:
comparing the error length with a preset second length threshold, wherein the second length threshold is set to be 3 burst reading lengths;
for the error data with the error length larger than a preset second length threshold, carrying out data re-reading processing on a memory, and comparing a second error address obtained by re-reading with a first error address obtained originally;
if the second error address is inconsistent with the first error address, classifying the single event upset corresponding to the error data into row address register single event upset, otherwise, initializing the memory and re-reading the data, and comparing a third error address obtained by re-reading with the second error address;
if the third error address obtained after the memory is initialized and the data is reread is inconsistent with the second error address, classifying the single event upset corresponding to the error data into mode register single event upset, otherwise, performing the power-on and data reread processing on the memory again, and comparing the fourth error address obtained by reread with the third error address;
and if the fourth error address obtained after the re-electrification and data re-reading processing is inconsistent with the third error address, classifying the single event upset corresponding to the error data into the single event upset of the control module, otherwise classifying the single event upset into the damage of the memory device.
With reference to the second or third possible implementation manner of the first aspect, in a fourth possible implementation manner of the first aspect, after the step of identifying the error length of the error data corresponding to the single event upset, the method further includes:
comparing the error length with a preset length range to determine whether the error length falls within the preset length range, wherein the preset length range is set to be 1-3 burst reading lengths;
and classifying the single event upset corresponding to the error data into the single event upset of the column address register for the error data with the error length falling in the preset length range.
With reference to the first aspect, in a fifth possible implementation manner of the first aspect, the step of acquiring error data of a single event upset occurring when the memory performs a single event effect test further includes:
recording the test starting time and the test ending time so as to obtain the fluence of the memory for carrying out the single event effect test according to the test starting time and the test ending time, wherein the fluence is used for calculating the single event upset cross section.
A second aspect of the embodiments of the present application provides a single event effect testing and analyzing apparatus for a memory, where the single event effect testing and analyzing apparatus for a memory includes:
the acquisition module is used for acquiring error data of single event upset when the memory is subjected to single event effect test;
the processing module is used for carrying out classification and identification on the single event upset generated by the memory according to a preset single event upset classification and identification rule based on the error data so as to obtain a classification category of the single event upset;
and the execution module is used for performing data statistical analysis of the single event upset on the memory according to the classification category of the single event upset and determining the sensitive position of the memory where the single event upset occurs.
The third aspect of the embodiment of the application provides a single event effect testing system of a memory, which comprises an upper computer and a single event test board, and is used for acquiring error data of single event upset when the memory is subjected to single event effect testing. The single-particle test board comprises a non-irradiation area and an irradiation area, the non-irradiation area is located on the front side of the single-particle test board and used for installing a communication serial port and an FPGA control module which are connected with the upper computer, and the irradiation area is located on the back side of the single-particle test board and used for installing a chip to be tested.
A fourth aspect of the embodiments of the present application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the steps of the method for single event effect test analysis of the memory according to any one of the first aspect when executing the computer program.
A fifth aspect of the embodiments of the present application provides a computer-readable storage medium, where a computer program is stored, and the computer program, when being executed by a processor, implements the steps of the single event effect test analysis method of the memory according to any one of the first aspect.
Compared with the prior art, the embodiment of the application has the advantages that:
the method comprises the steps of carrying out single event upset test on error data by obtaining a memory; based on the error data, carrying out classification recognition on the single event upset generated by the memory according to a preset single event upset classification recognition rule so as to obtain the classification category of the single event upset; and performing data statistical analysis of the single event upset on the memory according to the classification category of the single event upset, and determining the sensitive position of the memory where the single event upset occurs. The method can count the number of single event upset of the memory under the irradiation environment and perform classification analysis by combining the position of the single event upset, can deduce the sensitive position of the memory where the single event upset occurs from data, and is suitable for single event irradiation test analysis before and after reinforcing the dynamic memory. Therefore, irradiation resistance reinforcement and evaluation are carried out on the sensitive position of the memory device, and pertinence is strong.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic flowchart of a basic method of a single event effect test analysis method of a memory according to an embodiment of the present disclosure;
fig. 2 is a schematic flow chart of a method for determining single event upset classification in the single event effect test analysis method for the memory according to the embodiment of the present disclosure;
fig. 3 is a schematic flow chart of another method for determining single event upset classification in the single event effect test analysis method for the memory according to the embodiment of the present disclosure;
fig. 4 is a schematic flow chart of another method for determining single event upset classification in the single event effect test analysis method for the memory according to the embodiment of the present application;
fig. 5 is a test analysis flow chart of a single event effect test analysis method of a memory according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a single event effect testing and analyzing device for a memory according to an embodiment of the present disclosure;
fig. 7 is a schematic diagram of a basic structure of a single event effect test system of a memory according to an embodiment of the present disclosure;
fig. 8 is a schematic diagram of an electronic device for implementing a single event effect test analysis method for a memory according to an embodiment of the present disclosure.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to" determining "or" in response to detecting ". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".
Furthermore, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between descriptions and not necessarily for describing or implying relative importance.
Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise.
In order to explain the technical solution described in the present application, the following description will be given by way of specific examples.
The single event effect test analysis method of the memory provided by the embodiment of the application aims to classify single event upset when the memory is subjected to single event effect test by combining the structure and the characteristics of the dynamic memory, and obtain a classification category corresponding to the single event upset. And then, the classification types of the single event upset are counted and analyzed, so that the sensitive position of the memory where the single event upset occurs is deduced. The method is suitable for single particle irradiation test analysis before and after the dynamic memory is reinforced, irradiation resistance reinforcement and evaluation of the sensitive position of the memory device are realized, and the pertinence is strong.
In some embodiments of the present application, please refer to fig. 1, and fig. 1 is a flowchart illustrating a basic method of a single event effect test analysis method for a memory according to an embodiment of the present application. The details are as follows:
in step S101, error data of a single event upset occurring in the single event effect test performed by the memory is acquired.
In the embodiment, the single event effect test system is used for carrying out the single event effect test on the memory to obtain the error data corresponding to the single event upset of the memory in the test process. Specifically, in the irradiation environment, initial data is correspondingly written into each address of the memory, and the initial data may be random code initial data, all 0 code initial data, or all 1 code initial data. And then, carrying out data reading operation on the memory once to obtain the test data of all the addresses of the memory. Comparing the read test data with the initial data bit by bit according to the address, if the test data is not consistent with the initial data, recording the dislocation data of the data bit, and recording the error address. And counting all error data after traversing the memory.
In step S102, based on the error data, the single event upset occurring in the memory is classified and identified according to a preset single event upset classification and identification rule, so as to obtain a classification category of the single event upset.
In this embodiment, the memory is subjected to single event upset at different positions, and the error data obtained by testing the memory correspondingly has different performance characteristics. In this embodiment, in combination with the structure and characteristics of the memory, the single event upset may be divided into multiple categories according to the position of the single event upset in the memory. For example, the classification may include at least one of: the method comprises the following steps of single-event upset of a storage unit, single-event upset of a column address register, single-event upset of a row address register, single-event upset of a mode register and single-event upset of a control module. For the classification type of single event upset of the memory cells, error data obtained by testing the memory cells are represented as discrete address distribution. For the classification type of single event upset of the column address register, the error data obtained by testing the column address register is represented as continuous address errors, and the error length is within a set length range. For the classification type of single event upset of the row address register, the error data obtained by testing the row address register is represented as continuous address errors, the error length exceeds one row, and the row address register can be recovered if refreshed. For the classification type of mode register single event upset, error data obtained by testing the classification type shows that the error data can be recovered after the register is reconfigured. For the classification type of single event upset of the control module, the error data obtained by testing the classification type shows that the error data can be recovered after being electrified again. In this embodiment, the error data expression characteristics corresponding to each classification category are used as a classification identification rule, and single event upset occurring in the memory during the test is classified and identified according to the error data obtained through the single event upset effect test, so that all classification categories of the single event upset occurring in the memory during the test are identified and obtained.
In step S103, a statistical analysis of the single event upset data is performed on the memory according to the classification category of the single event upset, and a sensitive location of the memory where the single event upset occurs is determined.
In this embodiment, for the error data obtained by the single event upset test, classification is performed according to the features expressed by the error data, and classification categories corresponding to all single event upsets can be obtained. For one single event upset test of the memory, multiple types of single event upsets may occur, and at this time, the single event upset number of each classification type can be obtained by identifying the classification of the single event upsets and then performing data statistical analysis of the single event upsets on the memory according to the classification type of the single event upsets. The classification categories with larger single event upset number are more sensitive to the corresponding positions in the memory. Therefore, after all classification categories of the single event upset are obtained through classification and identification, statistical analysis is carried out on the classification categories, the number of the single event upset occurring at each position of the memory can be known, and the sensitive position of the memory can be judged and determined according to the number of the single event upset occurring. In some specific embodiments, a number threshold may be set as a determination criterion for a sensitive location of the memory, and if the number of single event upsets occurring at a certain location of the memory exceeds the number threshold, the location is determined to be the sensitive location of the memory.
The single event effect test analysis method for the memory provided by the embodiment can be used for counting the number of single event upsets of the memory in an irradiation environment and carrying out classification analysis on the positions of the single event upsets, can be used for deducing the sensitive positions of the memory where the single event upsets occur from data, and is suitable for single event irradiation test analysis before and after reinforcing the dynamic memory. Therefore, irradiation resistance reinforcement and evaluation are carried out on the sensitive position of the memory device, and pertinence is strong.
In some embodiments of the present application, please refer to fig. 2, which is a schematic flow chart illustrating a method for determining single event upset classification in the single event effect testing and analyzing method for a memory according to the present application. The details are as follows:
in step S201, identifying an error length of error data corresponding to the single event upset;
in step S202, comparing the error length with a preset first length threshold, wherein the first length threshold is set to be 1 burst read length;
in step S203, for error data with an error length smaller than a preset first length threshold, classifying the single event upset corresponding to the error data as a single event upset of the memory cell.
In this embodiment, after all the error data are obtained through traversing the memory statistics, the number of consecutive address errors in the error data corresponding to the single event upset is identified. For example, if the addresses corresponding to 1, 3, 6, 7, 8, and 10 of 10 consecutive addresses of the memory are erroneous, the number of consecutive address errors of the first single event upset is recorded as 1, the number of consecutive address errors of the second single event upset is recorded as 1, the number of consecutive address errors of the third single event upset is recorded as 3, and the number of consecutive address errors of the fourth single event upset is recorded as 1.
In this embodiment, the consecutive address errors are the error length of the error data. And comparing the error length with a preset first length threshold, and classifying the single event upset corresponding to the error data into the single event upset of the memory unit if the error length of the error data is smaller than the preset first length threshold. In this embodiment, the preset first length threshold is set as a burst read length, where the burst read length is an address length read once when the memory reads data, and may be one address length, or two address lengths, four address lengths, and so on, and the specific burst read length may be set by a tester according to its actual needs. For example, if the memory is set to read data address by address, the burst read length at this time is the length of one address, and if the memory is set to read data of two addresses at a time, the burst read length at this time is the length of two addresses. Assuming that the burst read length is set to be two addresses in the test, for the four single event upsets in the above example, the first, second, and fourth may be classified as memory cell single event upsets.
In some embodiments of the present application, please refer to fig. 3, and fig. 3 is a schematic flow chart illustrating another method for determining single event upset classification in the single event effect testing and analyzing method for a memory according to the present application. The details are as follows:
in step S301, comparing the error length with a preset second length threshold, where the second length threshold is set to be 3 burst read lengths;
in step S302, for the error data with the error length greater than the preset second length threshold, performing data re-reading processing on the memory, and comparing a second error address obtained by re-reading with the first error address obtained originally;
in step S303, if the second error address is not consistent with the first error address, classifying the single event upset corresponding to the error data as row address register single event upset, otherwise, performing initialization and data re-reading processing on the memory, and comparing a third error address obtained by re-reading with the second error address;
in step S304, if the third error address obtained after the initialization and data re-reading processing of the memory is inconsistent with the second error address, classifying the single event upset corresponding to the error data as mode register single event upset, otherwise, performing power-on and data re-reading processing on the memory again, and comparing the fourth error address obtained by re-reading with the third error address;
in step S305, if the fourth error address obtained after the power-up and data re-reading processes is inconsistent with the third error address, classifying the single event upset corresponding to the error data as the control module single event upset, otherwise classifying the single event upset as the damage of the memory device.
In this embodiment, for three categories, namely row address register single event upset, mode register single event upset, and control module single event upset, the error length of the error data exceeds 3 burst read lengths, and the performance characteristics of the error data can disappear after the inverted register is reset (refreshed). The row address register single event upset can disappear by directly refreshing the address, the error data of the mode register single event upset can disappear after the register is reconfigured, and the error data of the control module register upset can disappear after the register is powered on again. Therefore, a second length threshold is preset and is used for judging whether the single event upset corresponding to the error data is one of three categories, namely the row address register single event upset, the mode register single event upset and the control module single event upset, and the second length threshold is set to be 3 burst reading lengths. In this embodiment, after all the error data are obtained through traversing the memory statistics, the number of consecutive address errors of single event upset in the error data is identified, and the number of consecutive address errors of single event upset is the error length of the single event upset. Comparing the error length of single-particle upset with a preset second length threshold, firstly, re-reading the memory to refresh the row address register and read all the error addresses and error numbers of single-particle upset for error data with the error length larger than the preset second length threshold. And comparing a second error address obtained by re-reading with a first error address obtained originally, and classifying the single event upset corresponding to the error data into row address register single event upset if the second error address is inconsistent with the first error address. If the second error address is consistent with the first error address, further judging whether the error data is mode register single event upset. Specifically, the memory is initialized and data is read again, and all single event upset error addresses and error numbers are read. And then comparing a third error address obtained by the data re-reading processing with a second error address obtained by the last data re-reading processing, and classifying the single event upset corresponding to the error data into the single event upset of the mode register if the third error address is inconsistent with the second error address. If the third error address is consistent with the second error address, whether the error data is the single event upset of the control module is further judged. Specifically, the memory is powered up again and data is read again, and all single event upset error addresses and error numbers are read. And then comparing a fourth error address obtained by the data re-reading processing with a third error address obtained by the last data re-reading processing, and classifying the single event upset corresponding to the error data into the single event upset of the control module if the fourth error address is inconsistent with the third error address. If the fourth error address is identical to the third error address, the memory device is classified as defective.
In some embodiments of the present application, please refer to fig. 4, and fig. 4 is a flowchart illustrating another method for determining single event upset classification in the single event effect testing and analyzing method for a memory according to the embodiments of the present application. The details are as follows:
in step S401, comparing the error length with a preset length range to determine whether the error length falls within the preset length range, wherein the preset length range is set to 1-3 burst read lengths;
in step S402, for error data with an error length falling within a preset length range, the single event upset corresponding to the error data is classified as a column address register single event upset.
In this embodiment, after all the error data are obtained by traversing the memory statistics, the column address is refreshed once every time the memory reads data, that is, the column address error only affects the addresses with the burst read length of 1 to 3. Thus, a length range of 1-3 burst read lengths is preset. And comparing the error length of the single particle overturn with the preset length range, so as to determine whether the error length falls into the preset length range. And if the error length falls into a preset length range, classifying the single event upset corresponding to the error data into the single event upset of the column address register.
In some embodiments of the present application, please refer to fig. 5, and fig. 5 is a flowchart illustrating a test analysis of a single event effect test analysis method for a memory according to an embodiment of the present application. As shown in fig. 5, the memory is powered on first, and then the memory is initialized, including the precharge process, the auto-refresh data process, and the setting of the mode register. Then, the memory is subjected to read-write cycle configuration under irradiation conditions, i.e., initial data (random code, all 0's, all 1's, etc.) is written. And therefore, entering a single event effect test stage, performing data reading processing for the first time, acquiring error data of single event upset in the process of performing the single event effect test on the memory, and counting error addresses and error numbers of all the single event upset. Classifying single event upset corresponding to error data with the continuous address error number smaller than 1 burst reading length into single event upset of a storage unit according to the address length (namely burst reading length) read once when the data is read by a memory; and classifying the single event upset corresponding to the error data with the continuous address error number more than or equal to 1 burst reading length and less than or equal to 3 burst reading lengths into the single event upset of the column address register.
In this embodiment, for error data with a continuous address error number greater than 3 burst read lengths, a second data read process is performed to refresh the row address register and read all the error addresses and error numbers of single event upsets. And comparing the error data with the continuous address error number larger than 3 burst reading lengths obtained by the second data reading processing with the error data with the continuous address error number larger than 3 burst reading lengths in the first read data, and classifying the single event upset corresponding to the error data with the continuous address error number larger than 3 burst reading lengths in the second read data as the single event upset of the row address register if the error address of the error data in the second read data is inconsistent with the error address of the error data in the first read data.
In this embodiment, if the error addresses of the error data read for the first time and the second time are identical, the initialization processing is performed on the memory to rewrite the code pattern and the configuration register, and then the data reading processing for the third time is performed to read the error addresses and the error numbers of all single event upsets. And comparing the error data with the continuous address error number larger than 3 burst reading lengths obtained by the third data reading processing with the error data with the continuous address error number larger than 3 burst reading lengths in the second read data, and classifying the single event upset corresponding to the error data with the continuous address error number larger than 3 burst reading lengths in the third read data as the mode register single event upset if the error address of the error data in the third read is inconsistent with the error address of the error data in the second read.
In this embodiment, if the error addresses of the error data read for the second time and the third time are the same, the memory is powered up again, the code pattern and the configuration register are rewritten through initialization, and then the data read for the fourth time is performed to read the error addresses and the error numbers of all single event upsets. And comparing the error data with the continuous address error number larger than 3 burst reading lengths obtained by the fourth data reading processing with the error data with the continuous address error number larger than 3 burst reading lengths in the third read data, and classifying the single event upset corresponding to the error data with the continuous address error number larger than 3 burst reading lengths in the fourth read as the control module single event upset if the error address of the error data in the fourth read is inconsistent with the error address of the error data in the third read. Otherwise, it is determined that the memory device is defective.
In some embodiments of the application, when error data of single event upset occurring in a process of performing single event effect test on a memory is acquired, a test starting time and a test ending time can be recorded, so that the fluence of the memory for performing single event effect test is calculated according to the test starting time and the test ending time, and therefore, a single event upset cross section can be generated by combining the number of single event upsets occurring in the memory, the irradiation time and the fluence of the memory for performing single event effect test. Therefore, the sensitive position and the sensitive degree of the memory with the single event upset can be conjectured according to the cross section of the single event upset by combining the classification of the single event upset and the distribution of error addresses.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
In some embodiments of the present application, please refer to fig. 6, where fig. 6 is a schematic structural diagram of an apparatus for testing and analyzing single event effect of a memory according to an embodiment of the present application, which is detailed as follows:
in this embodiment, the apparatus for testing and analyzing single event effect of the memory includes: an acquisition block 601, a processing module 602, and an execution module 603. The obtaining module 601 is configured to obtain error data of a single event upset occurring when the memory performs a single event effect test. The processing module 602 is configured to perform classification and identification on the single event upset occurring in the memory according to a preset single event upset classification and identification rule based on the error data, so as to obtain a classification category of the single event upset. The execution module 603 is configured to perform data statistical analysis of single event upset on the memory according to the classification category of the single event upset, and determine a sensitive location of the memory where the single event upset occurs.
The single event effect test analysis device of the memory corresponds to the single event effect test analysis method of the memory one by one, and details are not repeated here.
In some embodiments of the present application, please refer to fig. 7, and fig. 7 is a schematic diagram illustrating a basic structure of a single event effect testing system of a memory according to an embodiment of the present application. As shown in fig. 7, the single event effect testing system of the memory includes an upper computer and a single event testing board. And the upper computer is used for controlling the single-particle test board and displaying the test result. The single particle test plate comprises a non-irradiation area and an irradiation area. The non-irradiation area is located on the front side of the single-particle test board and used for installing a serial port communication module and an FPGA control module which are connected with an upper computer, and the irradiation area is located on the back side of the single-particle test board and used for installing a chip to be tested. The single event effect test system of the memory is used for acquiring error data of single event upset when the memory is subjected to single event effect test.
In some embodiments of the present application, please refer to fig. 8, and fig. 8 is a schematic diagram of an electronic device implementing a single event effect test analysis method for a memory according to an embodiment of the present application. As shown in fig. 8, the electronic apparatus 8 of this embodiment includes: a processor 81, a memory 82 and a computer program 83 stored in said memory 82 and operable on said processor 81, such as a single event effect test analysis program of the memory. The processor 81 executes the computer program 82 to implement the steps in the above-described embodiments of the single event effect test analysis method for each memory. Alternatively, the processor 81 implements the functions of the modules/units in the above-described device embodiments when executing the computer program 83.
Illustratively, the computer program 83 may be partitioned into one or more modules/units that are stored in the memory 82 and executed by the processor 81 to accomplish the present application. The one or more modules/units may be a series of computer program instruction segments capable of performing specific functions, which are used to describe the execution of the computer program 83 in the electronic device 8. For example, the computer program 83 may be divided into:
the acquisition module is used for acquiring error data of single event upset generated during single event effect test of the memory;
the processing module is used for carrying out classification and identification on the single event upset generated by the memory according to a preset single event upset classification and identification rule based on the error data so as to obtain a classification category of the single event upset;
and the execution module is used for performing data statistical analysis of the single event upset on the memory according to the classification category of the single event upset and determining the sensitive position of the memory where the single event upset occurs.
The electronic device may include, but is not limited to, a processor 81, a memory 82. Those skilled in the art will appreciate that fig. 8 is merely an example of an electronic device 8 and does not constitute a limitation of the electronic device 8 and may include more or fewer components than shown, or some components may be combined, or different components, e.g., the electronic device may also include input-output devices, network access devices, buses, etc.
The Processor 81 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 82 may be an internal storage unit of the electronic device 8, such as a hard disk or a memory of the electronic device 8. The memory 82 may also be an external storage device of the electronic device 8, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like, which are provided on the electronic device 8. Further, the memory 82 may also include both an internal storage unit and an external storage device of the electronic device 8. The memory 82 is used for storing the computer program and other programs and data required by the electronic device. The memory 82 may also be used to temporarily store data that has been output or is to be output.
It should be noted that, for the information interaction, execution process, and other contents between the above-mentioned devices/units, the specific functions and technical effects thereof are based on the same concept as those of the embodiment of the method of the present application, and specific reference may be made to the part of the embodiment of the method, which is not described herein again.
The embodiments of the present application further provide a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the computer program implements the steps in the above-mentioned method embodiments.
The embodiments of the present application provide a computer program product, which when running on a mobile terminal, enables the mobile terminal to implement the steps in the above method embodiments when executed.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
The integrated modules/units, if implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium. Based on such understanding, all or part of the flow in the method of the embodiments described above can be realized by a computer program, which can be stored in a computer-readable storage medium and can realize the steps of the embodiments of the methods described above when the computer program is executed by a processor. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution medium, and the like. It should be noted that the computer readable medium may contain other components which may be suitably increased or decreased as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer readable media which may not include electrical carrier signals and telecommunications signals in accordance with legislation and patent practice.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus/terminal device and method may be implemented in other ways. For example, the above-described embodiments of the apparatus/terminal device are merely illustrative, and for example, the division of the modules or units is only one logical division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. A single event effect test analysis method of a memory is characterized by comprising the following steps:
acquiring error data of a memory subjected to single event upset in a single event effect test;
based on the error data, carrying out classification recognition on the single event upset generated by the memory according to a preset single event upset classification recognition rule so as to obtain the classification category of the single event upset;
and performing data statistical analysis of the single event upset on the memory according to the classification category of the single event upset, and determining the sensitive position of the memory where the single event upset occurs.
2. The single event effect test analysis method of the memory according to claim 1, wherein the classification category of the single event upset comprises at least one of: the method comprises the following steps of single-event upset of a storage unit, single-event upset of a column address register, single-event upset of a row address register, single-event upset of a mode register and single-event upset of a control module.
3. The single event effect test analysis method of the memory according to claim 2, wherein the step of classifying and identifying the single event upset occurring in the memory according to a preset single event upset classification and identification rule based on the error data to obtain the classification category of the single event upset comprises:
identifying the error length of error data corresponding to the single event upset;
comparing the error length with a preset first length threshold, wherein the first length threshold is set as 1 burst read length;
and classifying the single event upset corresponding to the error data into single event upset of a storage unit for the error data with the error length smaller than a preset first length threshold.
4. The method for single event effect test analysis of a memory according to claim 3, wherein after the step of identifying the error length of the error data corresponding to a single event upset, the method further comprises:
comparing the error length with a preset second length threshold, wherein the second length threshold is set to be 3 burst reading lengths;
for the error data with the error length larger than a preset second length threshold, carrying out data re-reading processing on a memory, and comparing a second error address obtained by re-reading with a first error address obtained originally;
if the second error address is inconsistent with the first error address, classifying the single event upset corresponding to the error data into row address register single event upset, otherwise, initializing the memory and re-reading the data, and comparing a third error address obtained by re-reading with the second error address;
if the third error address obtained after the memory is initialized and the data is reread is inconsistent with the second error address, classifying the single event upset corresponding to the error data into mode register single event upset, otherwise, performing the power-on and data reread processing on the memory again, and comparing the fourth error address obtained by reread with the third error address;
and if the fourth error address obtained after the re-electrification and data re-reading processing is inconsistent with the third error address, classifying the single event upset corresponding to the error data into the single event upset of the control module, otherwise classifying the single event upset into the damage of the memory device.
5. The single event effect test analysis method of the memory according to any one of claims 3 to 4, wherein after the step of identifying the error length of the error data corresponding to the single event upset, the method further comprises:
comparing the error length with a preset length range to determine whether the error length falls within the preset length range, wherein the preset length range is set to be 1-3 burst reading lengths;
and classifying the single event upset corresponding to the error data into the single event upset of the column address register for the error data with the error length falling in the preset length range.
6. The single event effect test analysis method of the memory according to claim 1, wherein the step of obtaining the error data of the single event upset occurring in the single event effect test of the memory further comprises:
recording the test starting time and the test ending time to acquire the fluence information of the memory when the memory is subjected to the single event effect test according to the test starting time and the test ending time, wherein the fluence information is used for calculating the single event upset cross section.
7. The single event effect test analysis device of the memory is characterized by comprising the following components:
the acquisition module is used for acquiring error data of single event upset generated during single event effect test of the memory;
the processing module is used for carrying out classification and identification on the single event upset generated by the memory according to a preset single event upset classification and identification rule based on the error data so as to obtain a classification category of the single event upset;
and the execution module is used for performing data statistical analysis of the single event upset on the memory according to the classification category of the single event upset and determining the sensitive position of the memory where the single event upset occurs.
8. The single event effect test system of the memory comprises an upper computer and a single event test board and is used for obtaining error data of single event upset of the memory during single event effect test.
9. An electronic device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the single event effect test analysis method of the memory according to any one of claims 1 to 6 when executing the computer program.
10. A computer-readable storage medium, in which a computer program is stored, which, when being executed by a processor, carries out the steps of the method for single event effect test analysis according to any one of claims 1 to 6.
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