CN114189397B - Device and method for detecting and correcting single event effect of Ethernet interface circuit - Google Patents
Device and method for detecting and correcting single event effect of Ethernet interface circuit Download PDFInfo
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- H02H7/10—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers
- H02H7/12—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers
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Abstract
The invention discloses a device and a method for detecting and correcting single event effect of an Ethernet interface circuit, which relate to the technical field of Ethernet interface circuits and comprise the following steps: firstly, detecting the power supply condition, and if the power supply branch circuit finds abnormality, re-electrifying the corresponding power supply branch circuit; if the power supply branch circuit does not find abnormality, detecting the state of the processor, and if abnormality occurs, resetting software, resetting hardware, refreshing again or powering on again; if the processor does not find abnormality, the Ethernet interface PHY register is detected, and if the PHY register is abnormal, software reset, hardware reset or re-power-on is carried out; if the PHY register is not abnormal, the loop detection of the Ethernet interface is carried out, if the PHY register is abnormal, the correction is carried out, if the PHY register is not abnormal, the Ethernet interface circuit is normal, the modularized detection is carried out, the reliability of the system is enhanced, and the problem that the Ethernet interface circuit is paralyzed or burnt out due to the single event effect of the Ethernet interface circuit is solved.
Description
Technical Field
The invention relates to the technical field of Ethernet interface circuits, in particular to a device and a method for detecting and correcting a single event effect of an Ethernet interface circuit.
Background
Since the first Ethernet technology of the space boat is adopted, the hot tide of the space Internet and the world Internet is lifted, and the constraint of the world bandwidth is about to be broken along with the popularization of 5G. Therefore, the new generation of ethernet bus communication method is continuously innovated, but a problem is neglected behind the phenomenon, and the PHY chip of the ethernet core chip, as a CMOS device, is prone to faults, such as a single event effect, in the space environment.
When single event upset occurs in the PHY chip, if the single event upset occurs in the data register, the effect can not be caused under the continuously optimized algorithm design, but once the single event upset occurs in the configuration register of the PHY chip, the key devices such as A/D, D/A and the like, the whole Ethernet interface circuit is paralyzed.
When single particle locking occurs to the PHY chip and its peripheral circuits, the whole Ethernet interface circuit is disabled, and the circuit current is increased continuously to burn the whole circuit.
Disclosure of Invention
The invention aims to provide a device and a method for detecting and correcting the single event effect of an Ethernet interface circuit, which solve the problem that the Ethernet interface circuit is paralyzed or burnt out due to the single event effect of the Ethernet interface circuit.
The invention is realized by the following technical scheme:
the method for detecting and correcting the single event effect of the Ethernet interface circuit comprises the following steps:
s1, detecting the power supply condition:
s11, reading power supply parameters of different power supply branches;
s12, comparing the power supply branch parameter with a corresponding threshold value in the storage equipment, and judging whether the power supply branch parameter exceeds the corresponding threshold value in the storage equipment;
s13, if the power supply branch parameters exceed the corresponding threshold values in the storage equipment, primarily judging that the power supply branch abnormality is single particle locking, and correcting the power supply branch abnormality;
s14, if the power supply branch parameter does not exceed the corresponding threshold value in the storage device, executing S2;
s2, detecting an Ethernet interface PHY register:
s21, reading current PHY register information;
s22, comparing the current PHY register information with pre-stored information in the storage device, and judging whether the current PHY register information is consistent with the pre-stored information in the storage device;
s221, if the current PHY register information is inconsistent with the pre-stored information in the storage device, primarily determining that the PHY register abnormality is single event upset or single event locking, and performing PHY register abnormality correction;
s222, if the current PHY register information is consistent with the pre-stored information in the storage device, performing ethernet interface loop detection.
s3, ethernet interface loop detection:
s31, configuring a PHY register, starting a loop mode and sending test information;
s32, detecting whether loop feedback test information is received or not;
s321, if no loop feedback test information is received, initially determining that the loop is turned over by a single particle or locked by a single particle, and returning to S2 to correct the loop abnormality;
s322, if the feedback test information is received, determining that the ethernet interface circuit is normal.
As the power supply system of the whole Ethernet interface circuit, once abnormality occurs, the whole Ethernet interface circuit is easy to break down or burn out, so that the applicant researches and discovers that fault detection is needed to be carried out on each branch of the power supply, and the break down or burn out of the Ethernet interface circuit is prevented; PHY register detection and loop detection are combined to ensure that the abnormality of the whole Ethernet interface circuit is found in time, so that the detection result is more comprehensive and accurate, and the problem that the Ethernet interface circuit is paralyzed or burnt out due to the single event effect of the Ethernet interface circuit is solved.
Further, after the power condition detection, before the ethernet interface PHY register detection, the method further includes a processor state detection, where the processor state detection includes the following steps:
f1, reading state information or scanning target area data sent by a processor;
f2, comparing the scanning target area data with the pre-stored state lookup table information or the pre-stored state data table information in the storage device, and judging whether the state information sent by the processor is consistent with the pre-stored state lookup table information in the storage device or whether the scanning target area data is consistent with the pre-stored state data table information in the storage device or not;
f21, if the state information sent by the processor is inconsistent with the prestored state lookup table information in the storage device, or the scanning target area data is inconsistent with the prestored state data table information in the storage device, the processor is abnormal, and processor abnormality correction is carried out;
and f22, if the state information sent by the processor is consistent with the pre-stored state lookup table information in the storage device, or if the scanning target area data is judged to be consistent with the pre-stored state data table information in the storage device, executing the detection of the PHY register of the Ethernet interface.
Furthermore, the processor performs software refreshing once at intervals, so that the processor is prevented from generating software abnormality, the condition that loop detection is inaccurate due to accumulated errors and the like is reduced, and the processor is ensured to normally operate.
Furthermore, the correction method of single particle locking comprises the steps of re-electrifying and resetting, and a re-electrifying mode is preferentially used; when conditions such as current increase slowly and the threshold is exceeded, then the reset mode is used preferentially.
The correcting method for single event upset comprises the steps of initializing a PHY register, resetting hardware, powering up an Ethernet interface circuit again, and selecting the correcting method according to a pre-stored abnormality solving table.
Further, the power supply branch abnormality correction method includes the following steps:
a1, re-electrifying the corresponding power supply branch, adding 1 to a power supply electrifying counter, and judging whether the abnormality of the corresponding power supply branch is solved;
a21, if the abnormality of the corresponding power supply branch is solved, judging that the single particle locking of the corresponding power supply branch at the abnormal position occurs;
a22, if the abnormality of the corresponding power supply branch is not solved, judging whether the power supply power-on counter is not less than 10 times;
a221, if the power-on counter is smaller than 10 times, re-electrifying the corresponding power branch;
and a222, if the power-on counter is not less than 10 times, judging that the system is uncorrectable in error corresponding to the power branch generation system at the abnormal position, closing the power branch corresponding to the abnormal position, resetting the power-on counter, transmitting error information and ending detection.
When the abnormality of the power supply branch is detected, the power supply branch is firstly electrified again, so that the power supply branch is internally corrected, if the power supply branch cannot be internally corrected, the corresponding power supply branch is closed, and error information is issued to remind relevant staff to process.
Further, the processor exception correcting method includes the following steps:
b1, if the processor abnormality counter is smaller than 10 times, selecting one or more combination modes of software reset, hardware reset, refreshing again or powering on again according to an abnormality lookup table prepared in advance to correct, and returning to power condition detection;
b2, adding 1 to the processor exception counter once in each processing;
and b3, if the processor abnormality counter is not less than 10 times, judging that the fault which can not be corrected by the processor occurs, resetting the processor abnormality counter, transmitting error information and ending detection.
When the abnormality of the processor is detected, firstly, internal correction is carried out, if the abnormality cannot be solved, the error is reported, and related staff is reminded to process the abnormality of the processor or the problem that the Ethernet interface circuit is paralyzed when the abnormality of the processor cannot be corrected is solved.
Further, the PHY register exception correction method includes the steps of:
c1, judging whether the PHY register has a flag bit set or not;
c11, if the PHY register has no flag bit, initially judging that the abnormality of the PHY register is single event upset, performing PHY register initialization operation, returning to power condition detection, and positioning the PHY register initialization flag bit;
c12, if the PHY register initialization flag bit is set, judging whether the PHY hardware reset flag bit is set;
c121, if the PHY hardware reset flag bit is not set, judging that the PHY register is abnormal and turned over by a single event, triggering a reset pin of the PHY chip to carry out hardware reset, returning to power condition detection, setting a PHY hardware reset flag, and clearing an PHY register initialization flag bit;
c122, if the PHY hardware reset flag is set, judging whether the PHY power-up counter is smaller than 10;
c1221, if the PHY power-on counter is smaller than 10, judging that the PHY register is abnormally locked by single particles, powering on the Ethernet interface circuit again, adding 1 to the PHY power-on counter, and returning to the power condition detection;
and c1222, if the PHY power-on counter is not less than 10, judging that the Ethernet interface circuit fails in an uncorrectable way, clearing the PHY register initialization flag bit and the PHY hardware reset flag bit, clearing the PHY power-on counter, transmitting error information and ending detection.
When the abnormality of the PHY register is detected, firstly, internal correction is carried out, if the abnormality can not be solved, the error is reported, and related staff is reminded to process the abnormality, so that the problem that the circuit of the Ethernet interface is paralyzed or burnt out due to single event upset or single event locking of the PHY register is solved.
Further, the loop abnormality correction method includes the following steps:
d1, judging whether the loop abnormity counter is not less than 10;
d2, if the loop-back exception counter is smaller than 10, executing the detection of the PHY register of the Ethernet interface, and adding 1 to the loop-back exception counter;
and d3, if the loop abnormality counter is not less than 10, powering on the Ethernet interface circuit again, positioning the loop abnormality zone bit, if the loop abnormality zone bit exists and is abnormal, judging that the Ethernet interface circuit has uncorrectable faults, clearing the PHY register initialization zone bit, the PHY hardware reset zone bit and the loop abnormality zone bit, clearing the loop abnormality counter, transmitting error information and ending detection.
An ethernet interface circuit single event effect detection and correction device comprising:
the Ethernet interface circuit is used for establishing Ethernet communication connection, and acquiring measured PHY register information and loop feedback information from the Ethernet interface circuit in the test;
the processor circuit is used for controlling various functions of a carrier of the device and data receiving and transmitting, transferring test information or feedback information, and is an intermediate data channel between the detection circuit and the Ethernet interface circuit;
the power supply monitoring unit is used for acquiring power supply parameters;
the detection circuit is used for receiving and transmitting test information, analyzing the acquired test information, correcting single event effect error reporting information generated by the Ethernet interface circuit and timely feeding back uncorrectable faults;
the detection circuit includes a storage device: the system comprises a power supply parameter storage module, a physical layer (PHY) register storage module, a power supply parameter storage module and a power supply parameter storage module, wherein the power supply parameter storage module is used for storing corresponding threshold values of power supply parameters, pre-stored information of the PHY register, pre-stored state information of a processor, an abnormality lookup table of the processor, a pre-stored abnormality solution table and a checking program backup;
the pre-stored state information of the processor comprises pre-stored state lookup table information and pre-stored state data table information.
The Ethernet interface circuit is indirectly connected with the detection circuit through the processor circuit.
The detection circuit and the processor circuit are arranged separately, so that the system function and the detection function can be separated more effectively, and the working efficiency of an actual system is improved.
Furthermore, the processor circuit of the Ethernet interface circuit single event effect detection and correction device is built by taking an MCU or an FPGA as a core.
Compared with the prior art, the invention has the following advantages and beneficial effects:
1. the applicant researches find that fault detection is performed on each branch of the power supply, so that the fault detection is beneficial to more rapidly preventing the paralysis or burnout of an Ethernet interface circuit;
2. the method for combining PHY register detection and loop detection ensures that the abnormality of the whole Ethernet interface circuit is found in time, so that the detection result is more comprehensive and accurate, and the problem that the Ethernet interface circuit is paralyzed or burnt out due to the single event effect of the Ethernet interface circuit is solved;
3. modularized detection, subdivision and priority setting make the abnormal position positioning more accurate and take countermeasures more easily;
4. the single-particle locking and single-particle overturning can be effectively identified and processed, the reliability of the system is improved, and reliable guarantee is provided for the development of the space Internet.
Drawings
In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the drawings that are needed in the examples will be briefly described below, it being understood that the following drawings only illustrate some examples of the present invention and therefore should not be considered as limiting the scope, and that other related drawings may be obtained from these drawings without inventive effort for a person skilled in the art. In the drawings:
FIG. 1 is a schematic view of the device connection provided in example 1;
FIG. 2 is a main flow chart of the present invention;
FIG. 3 is a flow chart of power branch anomaly correction;
fig. 4 is a flow chart of ethernet interface circuit PHY register correction.
Detailed Description
For the purpose of making apparent the objects, technical solutions and advantages of the present invention, the present invention will be further described in detail with reference to the following examples and the accompanying drawings, wherein the exemplary embodiments of the present invention and the descriptions thereof are for illustrating the present invention only and are not to be construed as limiting the present invention.
Example 1
As shown in fig. 1, embodiment 1 provides an ethernet interface circuit single event effect detection and correction device, which is applied to a space station.
The Ethernet interface circuit is connected with the processor circuit through one or more connection modes of MII/RMII/SGMII/SMII/GMII, and is used for reading PHY register information and receiving and transmitting loop-back test information of the Ethernet circuit, and an 88E1111 chip is used for the PHY chip.
The connection mode of the processor circuit and the service circuit can be changed according to different requirements, and the preferred connection modes comprise LVDS, RS422, CAN, SPI, I C and I/O modes.
The processor circuit is matched with 2 high-reliability NOR Flash for storing processor program backup, and the preferred processor model is the xc7k325T of xilinx.
Specifically, the processor circuit is connected with the detection circuit through two paths of synchronous RSs 422, one path is used for sending instructions, data and loop test information, and the other path is used for receiving PHY register values and loop feedback information transferred by the processor.
Specifically, the core device of the detection circuit is STM32F407ZGT6, the self-contained software watchdog and the hardware watchdog are protected, and three SPI Flash is used for storing preset information and self-program backup.
Specifically, the detection circuit is connected with the power supply monitoring circuit through the I2C, the core device of the power supply monitoring circuit is ina219, and the voltage, the current and the power information of the power supply branch circuit can be detected simultaneously.
Specifically, the detection circuit realizes the function of re-powering up by controlling the on-off of the power switch.
Example 2
As shown in fig. 2 to 4, embodiment 2 provides a method for detecting and correcting a single event effect of an ethernet interface circuit for embodiment 1, wherein after a system is initialized for a specified time, the ethernet interface circuit starts to be detected, and the method comprises the following steps:
step 1: power condition detection
A1, reading data in a power supply monitoring circuit through I2C, and reading power supply information of different power supply branches, such as current voltage V, current I and power P;
a2, comparing the data in the power supply monitoring circuit with a corresponding threshold value in the SPI Flash, and judging the current state of each branch of the power supply;
a21, if the data in the power supply monitoring circuit exceeds the corresponding threshold range in the SPI Flash, the current power supply branch is abnormal, the power supply switch of the corresponding power supply branch is controlled to be electrified again, the stay time between the switches is T1, the count value of cout1 is increased by 1, and the initial value of cout1 is 0;
a211, if the count1 is smaller than 10 and the abnormality is solved after the power is turned on again, judging that the single-particle locking occurs to the power supply branch corresponding to the abnormal position, resetting the count1, and executing the step 2;
a212, if cout1 is not less than 10 and the abnormality is not solved after the power is turned on again, judging that uncorrectable errors occur in the system, switching off the switch of the corresponding power supply branch, and transmitting error information, and resetting cout 1.
And A22, if the data in the power supply monitoring circuit does not exceed the corresponding threshold range in the SPI Flash, the current power supply branch is not abnormal, and the step 2 is executed.
Step 2: processor state detection
B1, checking state information or active scanning target area data issued by a processor at regular time with a preset state lookup table or data table information to judge whether abnormality occurs;
b11, if the state information issued by the processor at regular time or the data of the active scanning target area is inconsistent with the information of the preset state lookup table or the data table, the processor is abnormal;
if the coutF is less than 10, performing correction processing according to one or more combination modes of software reset, hardware reset, refreshing again or powering up again according to an abnormality lookup table prepared in advance, returning to the step 1 for execution, and adding 1 to the coutF, wherein the initial value of the coutF is 0;
b112, if the coutF is not less than 10, judging that the error can not be corrected by the processor, closing a power inlet switch, resetting the coutF, transmitting error information and ending detection;
b12, if the state information issued by the processor at regular time or the data of the active scanning target area is consistent with the information of the preset state lookup table or the data table, the processor is not abnormal;
b2, if the processor is abnormal or the abnormality correction is successful, the coutF is cleared, and the step 3 is executed;
and B3, for the normal operation of the processor, performing software refreshing on the processor and performing program checking on the program memory at intervals.
Step 3: ethernet interface circuit PHY register detection
C1, firstly, reading current PHY register information, comparing the current PHY register information with pre-stored information in a storage device, and judging whether the PHY register is abnormal or not;
if the current PHY register information is inconsistent with the pre-stored information in the storage device, the current Ethernet interface is abnormal, the PHY register is 000, single event upset is preliminarily judged, the PHY register initialization operation is carried out, then the step 1 is returned, and the abnormal PHY register of the Ethernet interface is set to be 001;
c111, if abnormality occurs, and the abnormal PHY register of the Ethernet interface is 001, carrying out hardware reset through a reset pin of the PHY chip, returning to the step 1, and setting the abnormal PHY register of the Ethernet interface to 010;
c1111, if abnormality occurs, and meanwhile, the abnormal PHY register of the Ethernet interface is 010 and count2 is more than 0 and less than 10, then judging that the abnormality is not single event upset, powering up the Ethernet interface circuit again, adding 1 to count2, and returning to step 1 after the initial value of the count2 is 0;
c1112, if abnormality occurs, and meanwhile, the abnormal PHY register of the Ethernet interface is 010 and count2 is not less than 10, uncorrectable faults occur in the Ethernet circuit, the initialization flag bit of the PHY register and the reset flag bit of PHY hardware are cleared, count2 is cleared, error information is sent down, and detection is finished;
and C2, if the current PHY register information is consistent with the pre-stored information in the storage device, no abnormality occurs, and the step 4 is executed.
Step 4: ethernet interface circuit loop test
D1, configuring a PHY register, starting a loop mode, sending test information, and detecting whether loop feedback test information is received or not;
if no feedback test information is received, an abnormality occurs and the countL is smaller than 10, the step 3 is skipped, the countL is added with 1, and the initial value of the countL is 0;
d12, if the abnormality occurs and the countL is not less than 10, powering on the Ethernet interface circuit again, and positioning a loop abnormality zone bit, if the loop abnormality zone bit exists and the abnormality occurs, judging that uncorrectable errors occur in the Ethernet interface circuit, clearing the PHY register initialization zone bit and the PHY hardware reset zone bit, clearing the countL, transmitting error information and ending detection;
and D2, if no abnormality occurs, judging that the Ethernet interface circuit is normal, and if no single event upset or single event locking occurs, setting an Ethernet interface abnormal PHY register to be 000, resetting the coutL, ending the detection, and waiting for the next detection to start.
Example 3
Compared with embodiment 1, the difference of this embodiment 3 is that the ethernet interface circuit single event effect detection and correction device has an inspection circuit, and the inspection circuit incorporates the detection function into the processor circuit, so as to realize direct connection between the ethernet interface circuit and the inspection circuit, and can more quickly respond to the single event upset or locking, thereby solving the problem that the ethernet interface circuit is broken down or burned out due to the single event effect of the ethernet interface circuit in the space environment.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the scope of the invention, but to limit the invention to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (8)
1. The method for detecting and correcting the single event effect of the Ethernet interface circuit is characterized by comprising the following steps:
s1, detecting the power supply condition:
s11, judging whether the power supply branch parameters exceed corresponding thresholds in the storage equipment;
s111, if the power supply branch abnormality exceeds a corresponding threshold value in the storage equipment, primarily judging that the power supply branch abnormality is single-particle locking, and correcting the power supply branch abnormality;
s112, if the corresponding threshold value in the storage device is not exceeded, executing S2;
s2, detecting an Ethernet interface PHY register:
s21, judging whether the current PHY register information is consistent with prestored information in a storage device;
s211, if the information is inconsistent with the pre-stored information in the storage device, initially judging that the abnormality of the PHY register is single event upset or single event locking, and correcting the abnormality of the PHY register;
s212, if the information is consistent with the pre-stored information in the storage device, executing S3;
s3, ethernet interface loop detection:
s31, configuring a PHY register, starting a loop mode and sending test information;
s32, detecting whether loop feedback test information is received or not;
s321, if loop feedback test information is not received, initially judging that single event upset or single event locking is carried out, and returning to S2 to carry out loop abnormality correction;
s322, if the feedback test information is received, the Ethernet interface circuit is judged to be normal.
2. The method for detecting and correcting single event effect of ethernet interface circuit according to claim 1, wherein after said power condition detection, before said ethernet interface PHY register detection, further comprising a processor state detection, said processor state detection comprising the steps of:
f1, reading state information sent by a processor;
f2, comparing the state information with the pre-stored state information in the storage device, and judging whether the state information sent by the processor is consistent with the pre-stored state information in the storage device;
f21, if the state information sent by the processor is inconsistent with the pre-stored state information in the storage device, the processor is abnormal, and processor abnormality correction is carried out;
and f22, if the state information sent by the processor is consistent with the pre-stored state information in the storage device, executing the detection of the PHY register of the Ethernet interface.
3. The method of claim 2, wherein the processor performs a software refresh at intervals.
4. The method for detecting and correcting single event effect of ethernet interface circuit according to claim 1, wherein said method for correcting power branch abnormality comprises the steps of:
a1, re-electrifying the corresponding power supply branch, adding 1 to a power supply electrifying counter, and judging whether the abnormality of the corresponding power supply branch is solved;
a21, if the abnormality of the corresponding power supply branch is solved, judging that the single particle locking of the corresponding power supply branch at the abnormal position occurs;
a22, if the abnormality of the corresponding power supply branch is not solved, judging whether the power supply power-on counter is not less than 10 times;
a221, if the power-on counter is smaller than 10 times, re-electrifying the corresponding power branch;
and a222, if the power-on counter is not less than 10 times, judging that the system is uncorrectable in error corresponding to the power branch generation system at the abnormal position, closing the power branch corresponding to the abnormal position, resetting the power-on counter, transmitting error information and ending detection.
5. The method for detecting and correcting single event effect of ethernet interface circuit according to claim 2, wherein said method for correcting processor anomalies comprises the steps of:
b1, if the processor abnormality counter is smaller than 10 times, selecting one or more combination modes of software reset, hardware reset, refreshing again or powering on again to correct, and returning to power condition detection;
b2, adding 1 to the processor exception counter once in each processing;
and b3, if the processor abnormality counter is not less than 10 times, judging that the fault which can not be corrected by the processor occurs, resetting the processor abnormality counter, transmitting error information and ending detection.
6. The method for detecting and correcting single event effect of ethernet interface circuit according to claim 1, wherein said PHY register anomaly correction method comprises the steps of:
c1, judging whether the PHY register has a flag bit set or not;
c11, if the PHY register has no flag bit, initially judging that the abnormality of the PHY register is single event upset, performing PHY register initialization operation, returning to power condition detection, and positioning the PHY register initialization flag bit;
c12, if the PHY register initialization flag bit is set, judging whether the PHY hardware reset flag bit is set;
c121, if the PHY hardware reset flag bit is not set, judging that the PHY register is abnormal and turned over by a single event, triggering a reset pin of the PHY chip to carry out hardware reset, returning to power condition detection, setting a PHY hardware reset flag, and clearing an PHY register initialization flag bit;
c122, if the PHY hardware reset flag is set, judging that the PHY power-up counter is not less than 10;
c1221, if the PHY power-on counter is smaller than 10, judging that the PHY register is abnormally locked by single particles, powering on the Ethernet interface circuit again, adding 1 to the PHY power-on counter, and returning to the power condition detection;
and c1222, if the PHY power-on counter is not less than 10, judging that the Ethernet interface circuit fails in an uncorrectable way, clearing the PHY register initialization flag bit and the PHY hardware reset flag bit, clearing the PHY power-on counter, transmitting error information and ending detection.
7. The method for detecting and correcting single event effect of ethernet interface circuit according to claim 1, wherein said method for correcting loop anomalies comprises the steps of:
d1, judging whether the loop abnormity counter is not less than 10;
d2, if the loop-back exception counter is smaller than 10, returning to the detection of the Ethernet interface PHY register, and adding 1 to the loop-back exception counter;
and d3, if the loop abnormality counter is not less than 10, powering on the Ethernet interface circuit again, positioning the loop abnormality flag bit, if the loop abnormality flag bit exists and is abnormal, judging that the Ethernet interface circuit has uncorrectable faults, clearing the PHY register initialization flag bit and the PHY hardware reset flag bit, clearing the loop abnormality counter, transmitting error information and ending detection.
8. An ethernet interface circuit single event effect detection and correction device, comprising:
the Ethernet interface circuit is used for establishing Ethernet communication connection and acquiring measured PHY register information and loop feedback information;
the processor circuit is used for controlling various functions of the device carrier and data receiving and transmitting, transferring test information or feedback information;
the power supply monitoring unit is used for acquiring power supply parameters;
the detection circuit is used for receiving and transmitting the test information, analyzing the acquired test information, correcting single event effect error reporting information generated by the Ethernet interface circuit, and timely feeding back uncorrectable faults;
the Ethernet interface circuit is indirectly connected with the detection circuit through the processor circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111509986.1A CN114189397B (en) | 2021-12-10 | 2021-12-10 | Device and method for detecting and correcting single event effect of Ethernet interface circuit |
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