CN114337611A

CN114337611A - Three-node overturning self-recovery latch based on cyclic feedback C unit

Info

Publication number: CN114337611A
Application number: CN202111517128.1A
Authority: CN
Inventors: 闫爱斌; 位少杰; 李志星; 崔杰; 周勇; 倪天明; 黄正峰
Original assignee: Anhui University
Current assignee: Anhui University
Priority date: 2021-12-13
Filing date: 2021-12-13
Publication date: 2022-04-12

Abstract

The invention relates to a three-node overturning self-recovery latch based on a cyclic feedback C unit, which comprises a double-cyclic structure storage module and four transmission gates, wherein the double-cyclic structure storage module consists of twelve two-input C units and comprises a first C unit CE1 to a twelfth C unit CE 12; the four transmission gates include a first transmission gate TG1 to a fourth transmission gate TG 4; the signal inputs of the four transmission gates are all used as the data input D of the latch, and the output of the fifth C-cell CE5 is used as the data output of the latch. The invention has high reliability, can tolerate the turnover of any three nodes and can be recovered; the use of fewer MOS tubes reduces the area and power consumption overhead, improves the tolerance capability of the latch and has more excellent performance; with low delay, the invention creates a more efficient path and therefore low transmission delay, since in the transparent mode there is only one transmission gate between the input and the output.

Description

Three-node overturning self-recovery latch based on cyclic feedback C unit

Technical Field

The invention relates to the technical field of anti-interference reinforced latch of a nanometer integrated circuit, in particular to a three-node overturning self-recovery latch based on a cyclic feedback C unit.

Background

The development of microelectronic fabrication processes in recent years has brought integrated circuits into the nanometer era. Under the nanometer technology, the characteristic size of the transistor is continuously reduced, so that the power consumption and the performance of the integrated circuit are improved, but the integrated circuit is easily interfered by space radiation, namely, soft errors are easily generated. Soft errors refer to the fact that the logic state of a circuit node changes due to external interference under the condition that a hardware circuit is not damaged, and the soft errors mainly come from interference of high-energy particles in space radiation, such as neutrons, alpha particles, protons, heavy ions and electrons. Therefore, the strengthening technology of the circuit is widely applied to the aspects of aerospace.

In terms of radiation hardening of integrated circuit cells, related researchers are more inclined to look at the design of latches and flip-flops. Due to the fact that the latch is simple in structure, under the nanometer technology, under the space radiation environment with complex environment and strong interference, the unreinforced latch is easy to generate node logic turnover, even multi-node turnover, and therefore huge challenges are brought to design and application of the nanoscale latch. Also because of this, for the design of the multi-node resistant hardened latch, we should also mention the schedule.

At present, many latch designs resistant to multi-node flipping are available, but most of these latches have the following problems: firstly, the latch can not carry out self-recovery on the double-node upset, namely when the double nodes of the latch are logically overturned simultaneously, although the correct value can be output, at least one overturned node can not be recovered to the original correct value; secondly, the latch cannot tolerate the simultaneous overturning of the three nodes, namely the latch cannot output a correct value; thirdly, the latch can not carry out self-recovery on the three-node turnover, namely when the three latch nodes are simultaneously turned over, although the correct logic value can be finally output, the turned-over nodes can not be recovered to the original state; fourthly, the latch which can tolerate multi-node turnover and is self-recovery has poor performance and large power consumption, area and delay.

Disclosure of Invention

The invention aims to provide a three-node overturning self-recovery latch based on a cyclic feedback C unit, which has low area overhead and low delay and can meet the high reliability requirement of complete self-recovery of any three nodes.

In order to achieve the purpose, the invention adopts the following technical scheme: a three-node flip self-recovery latch based on a cyclic feedback C unit comprises a double-cyclic structure storage module and four transmission gates, wherein the double-cyclic structure storage module consists of twelve two-input C units, and the twelve two-input C units comprise a first C unit CE1, a second C unit CE2, a third C unit CE3, a fourth C unit CE4, a fifth C unit CE5, a sixth C unit CE6, a seventh C unit CE7, an eighth C unit CE8, a ninth C unit CE9, a tenth C unit CE10, an eleventh C unit CE11 and a twelfth C unit CE 12; the four transmission gates include a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3 and a fourth transmission gate TG 4; the signal input ends of the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3 and the fourth transmission gate TG4 are all used as the data input end D of the latch, and the output end of the fifth C cell CE5 is used as the data output end of the latch.

A first signal input terminal of the first C cell CE1 is connected to the output terminal N6 of the sixth C cell CE6, a second signal input terminal of the first C cell CE1 is connected to the output terminal N8 of the eighth C cell CE8, and an output terminal N1 of the first C cell CE1 is connected to a first input terminal of the second C cell CE2 and a second input terminal of the twelfth C cell CE 12; a second signal input terminal of the second C cell CE2 is connected to the output terminal N9 of the ninth C cell CE9, and an output terminal N2 of the second C cell CE2 is connected to a first input terminal of the third C cell CE3 and a first input terminal of the seventh C cell CE 7; a second signal input terminal of the third C cell CE3 is connected to the output terminal N10 of the tenth C cell CE10, and an output terminal N3 of the third C cell CE3 is connected to a first input terminal of the fourth C cell CE4 and a first input terminal of the eighth C cell CE 8; a second signal input terminal of the fourth C cell CE4 is connected to the output terminal N11 of the eleventh C cell CE11, and the output terminal N4 of the fourth C cell CE4 is connected to a first input terminal of the fifth C cell CE5 and a second input terminal of the ninth C cell CE 9; a second signal input terminal of the fifth C cell CE5 is connected to the output terminal N12 of the twelfth C cell CE12, and an output terminal N5 of the fifth C cell CE5 is connected to a first input terminal of the sixth C cell CE6 and a first input terminal of the tenth C cell CE 10; a second signal input terminal of the sixth C cell CE6 is connected to the output terminal N7 of the seventh C cell CE7, and the output terminal N6 of the sixth C cell CE6 is connected to the first input terminal of the eleventh C cell CE 11; a second signal input terminal of the seventh C cell CE7 is connected to the output terminal N12 of the twelfth C cell CE12, and the output terminal N7 of the seventh C cell CE7 is connected to a second input terminal of the sixth C cell CE6 and a second input terminal of the eighth C cell CE 8; a first signal input terminal of the ninth C-cell CE9 is connected to the output terminal N8 of the eighth C-cell CE 8; a second signal input terminal of the tenth C-cell CE10 is connected to the output terminal N9 of the ninth C-cell CE 9; a second signal input terminal of the eleventh C-cell CE11 is connected to the output terminal N10 of the tenth C-cell CE 10; a first signal input terminal of the twelfth C-cell CE12 is connected to the output terminal N11 of the eleventh C-cell CE 11.

A signal output end of the first transmission gate TG1 is connected to a first input end of a fourth C cell CE4 and a first input end of an eighth C cell CE8, respectively; a signal output end of the second transmission gate TG2 is connected to a first signal input end of the sixth C unit and a first input end of the tenth C unit CE10, respectively; a signal output end of the third transmission gate TG3 is connected to a second input end of the sixth C cell CE6 and a second input end of the eighth C cell CE8, respectively; a signal output terminal of the fourth transmission gate TG4 is connected to a second input terminal of the second C cell CE2 and a second input terminal of the tenth C cell CE10, respectively.

The first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3 and the fourth transmission gate TG4 are all composed of a PMOS transistor and an NMOS transistor, and the sources of the PMOS transistor and the NMOS transistor are connected together and used as the input of the transmission gates; the drains of the PMOS transistor and the NMOS transistor are connected together and used as the output of the transmission gate; the gate of the NMOS transistor is connected to the system clock signal CLK, and the gate of the PMOS transistor is connected to the inverted system clock signal NCK.

The twelve two-input C units have the same structure, the first C unit CE1 consists of two PMOS tubes and two NMOS tubes, the two PMOS tubes comprise a first PMOS tube MP11 and a second PMOS tube MP12, and the two NMOS tubes comprise a first NMOS tube MN11 and a second NMOS tube MN 12;

the gate of the first PMOS transistor MP11 is connected to the gate of the first NMOS transistor MN11, and the connection point is the first signal input end of the first C unit CE 1; the gate of the second PMOS transistor MP12 is connected to the gate of the second NMOS transistor MN12, and the connection point is the second signal input end of the first C unit CE 1; the drain electrode of the first PMOS tube MP11 is connected with the source electrode of the second PMOS tube MP 12; the drain electrode of the second PMOS tube MP12 is connected with the drain electrode of the first NMOS tube MN 11; the source electrode of the first NMOS transistor MN11 is connected with the drain electrode of the second NMOS transistor MN 12; the source electrode of the first PMOS transistor MP11, the substrate of the first PMOS transistor MP11 and the substrate of the second PMOS transistor MP12 are all connected with a power supply VDD; the substrate of the first NMOS transistor MN11, the substrate of the second NMOS transistor MN12 and the source of the second NMOS transistor MN12 are all grounded.

When the system clock signal CLK = 0 and the inverted system clock signal NCK = 1, the signal output terminal N5 of the fifth C-cell CE5 serves as the data output terminal of the latch; the signal output terminal of the second transmission gate TG2 serves as the data output terminal of the latch when the system clock signal CLK = 1 and the inverted system clock signal NCK = 0.

According to the technical scheme, the beneficial effects of the invention are as follows: firstly, the reliability is high, any three-node turnover can be tolerated and self-recovery can be realized; secondly, fewer MOS tubes are used, so that compared with the existing latch, the area and power consumption overhead are reduced, the tolerance capability of the latch is improved, and the latch has more excellent performance; third, with low latency, the present invention establishes a more efficient path and therefore low transmission delay, since there is only one transmission gate between the input and the output in the transparent mode.

Drawings

Fig. 1 is a schematic circuit diagram of the present invention.

Fig. 2 is a circuit schematic of four transmission gates in the present invention.

Fig. 3 is a schematic circuit diagram of the first C cell CE1 in fig. 1.

Detailed Description

As shown in fig. 1, a three-node flipped self-recovery latch based on a cyclic feedback C unit includes a dual-cycle structure storage module and four transmission gates, where the dual-cycle structure storage module is composed of twelve two-input C units, and the twelve two-input C units include a first C unit CE1, a second C unit CE2, a third C unit CE3, a fourth C unit CE4, a fifth C unit CE5, a sixth C unit CE6, a seventh C unit CE7, an eighth C unit CE8, a ninth C unit CE9, a tenth C unit CE10, an eleventh C unit CE11, and a twelfth C unit CE 12; the four transmission gates include a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3 and a fourth transmission gate TG 4; the signal input ends of the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3 and the fourth transmission gate TG4 are all used as the data input end D of the latch, and the output end of the fifth C cell CE5 is used as the data output end of the latch.

As shown in fig. 1 and 2, the signal output terminal of the first transmission gate TG1 is connected to the first input terminal of the fourth C cell CE4 and the first input terminal of the eighth C cell CE8, respectively; a signal output end of the second transmission gate TG2 is connected to a first signal input end of the sixth C unit and a first input end of the tenth C unit CE10, respectively; a signal output end of the third transmission gate TG3 is connected to a second input end of the sixth C cell CE6 and a second input end of the eighth C cell CE8, respectively; a signal output terminal of the fourth transmission gate TG4 is connected to a second input terminal of the second C cell CE2 and a second input terminal of the tenth C cell CE10, respectively.

For each C unit in the double-circulation structure storage module, if the input end of the next C unit connected with the C unit is not fed back, the output end of the C unit feeds back to the input ends to be fed back until the corresponding input ends of all the C units in the ring are fed back.

Finally, all input ends of all C units are fed back to achieve circular interlocking.

As shown in fig. 3, the twelve two-input C units have the same structure, the first C unit CE1 is composed of two PMOS transistors including a first PMOS transistor MP11 and a second PMOS transistor MP12, and two NMOS transistors including a first NMOS transistor MN11 and a second NMOS transistor MN 12;

The truth table of the two-input C cells (the first C cell CE1 through the twelfth C cell CE 12) is shown in table 1 below:

table 1 above is a truth table for a two-input C cell. As can be seen from the table, when the first signal input terminal and the second signal input terminal have the same logic value, the signal output terminal will output the opposite logic value to the input; when the first signal input terminal and the second signal input terminal have different logic values, the signal output terminal enters a holding state and outputs the logic value in the previous state. It can be seen that the two-input C cells (the first C cell CE1 through the twelfth C cell CE 12) can be used to mask the logic value inversion of the node, i.e., prevent the part of the logic value inversion in the signal input terminal from propagating to the signal output terminal. When the logic values of the two signal input ends are all inverted, the logic value of the output end is also inverted. Therefore, the logic value of the output end can be restored to the original value only when the logic values of the two signal input ends are restored to the original values.

The normal operation of the latch proposed by the present invention is explained below.

When CLK = 1, NCK = 0, the structure operates in the transparent mode. At this time, the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3 and the fourth transmission gate TG4 are turned on, Q (N5), N3, N7 and N9 are initialized to the value of D, and the initialized nodes determine the values of the nodes N1, N2, N4, N6, N8, N10, N11 and N12 in fig. 1 through the C unit, that is, all the nodes are initialized.

When CLK = 0 and NCK = 1, the latch operates in the latch mode, and the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, and the fourth transmission gate TG4 are turned off, so that N3 is determined by the output terminal of the third C cell CE3, Q (N5) is determined by the output terminal of the fifth C cell CE5, N7 is determined by the output terminal of the seventh C cell CE7, and N9 is determined by the output terminal of the ninth C cell CE 9. Since the values of the nodes N1, N2, N4, N6, N8, N10, N11, and N12 are initialized in the transparent mode, in the cyclic storage module, the nodes N3, Q (N5), N7, and N9 feed back to the nodes N6, N8, and N10 through three two-input C units, the nodes N6, N8, and N10 feed back to the nodes N1 and N11 through two-input C units, the nodes N1, N3, N9, and N11 feed back to the nodes N2, N4, and N12 through three two-input C units, and the nodes N2, N4, N8, N10, and N12 feed back to the nodes N3, Q (N5), N7, and N9 through four two-input C units, so as to form several feedback loops. The latch can effectively hold data. In summary, the latch can work normally.

The principle of the fault-tolerant operation of the latch proposed by the present invention is explained below. The case of internal three-node rollover (TNU) is discussed first. According to the symmetry and the cyclic feedback rule of the latch, the analysis shows that the outer ring and the inner ring can be regarded as the same type, and each node in the ring has the same position. Only the following two representative cases need to be considered: (1) the three nodes simultaneously generate TNU on a ring (2) the three nodes simultaneously generate TNU, wherein two nodes are in the same ring, and the other node is in the same ring;

before analyzing the fault tolerance principle, three properties are introduced first:

properties 1: for any two-input C cell, when its inputs are all correct values, it will output the correct value regardless of whether its output is affected.

Properties 2: for any two-input C cell, when one of its inputs is flipped and its output is not flipped, it will still output the correct value.

Properties 3: for any two-input C unit, when the two inputs are all inverted, it will output wrong value; when one of its inputs toggles concurrently with its output, it will hold the wrong output. At this point, the input that needs to be flipped is all restored first, and then it will output the correct value.

For the case of (1), due to the loop characteristics of the loop storage module, the critical TNU sequences < N1, N2, N3>, < N1, N2, N4>, < N1, N3, N5> may be selected accordingly.

When TNU occurs for < N1, N2, N3>, the second C-unit CE2 and the third C-unit CE3 satisfy property 3, the fourth C-unit CE4 satisfies property 2, and the other C-units satisfy property 1. Therefore, CEs other than the second C cell CE2 and the third C cell CE3 may output correct values, and obviously, the sixth C cell CE6 and the eighth C cell CE8 will output correct values, so N1 restores the original values first. Then the inputs at the input of the second C cell CE2 are all the original values and N2 restores the original values. Similarly, N3 is also restored to the original value, i.e., < N1, N2, N3> can be recovered from TNU.

When TNU occurs for < N1, N2, N4>, the second C-unit CE2 satisfies property 3, the third C-unit CE3 and the fifth C-unit CE5 satisfy property 2, and the other C-units satisfy property 1. Therefore, the CEs except the second C cell CE2 can output correct values, and obviously, the sixth C cell CE6 and the eighth C cell CE8 will output correct values, so N1 restores the original values first. Likewise, N4 may also recover its original value. Then the inputs at the input of the second C-cell CE2 are all the same value, and N2 recovers the value, i.e. < N1, N2, N4> can be recovered from TNU.

When TNU occurs for < N1, N3, N5>, the second C-unit CE2, the fourth C-unit, the sixth C-unit, the eighth C-unit, the tenth C-unit, the twelfth C-unit satisfy property 2, and the remaining all C-units satisfy property 1. Obviously, the sixth C cell CE6 and the eighth C cell CE8 will output correct values, so N1 restores the original values first. In the same way, the original values of N3 and N5, namely < N1, N2 and N3> can be recovered from TNU. Through analysis, the latch can realize the TNU self-recovery function under the condition.

For the case of (2), due to the cyclic nature of the cyclic storage module, the critical TNU sequences < N1, N2, N8>, < N1, N2, N9>, < N1, N3, N10>, < N1, N3, N9> may thus be selected.

When TNU occurs for < N1, N2, N8>, the first C-unit CE1 and the second C-unit CE2 satisfy property 3, the twelfth C-unit CE12, the third C-unit CE3, and the ninth C-unit CE9 satisfy property 2, and the other C-units satisfy property 1. Therefore, the CEs except the first C cell CE1 and the second C cell CE 8926 can output correct values, and obviously, the outputs of the output terminals of the third C cell CE3 and the seventh C cell CE7 are still the same values, and then the N8 is restored to the same values. Subsequently, the input of the first C unit is restored to the original value, N1 is restored to the original value, and similarly, N2 is restored to the original value, i.e., < N1, N2, N8> can be restored from TNU

When TNU occurs for < N1, N2, N9>, the second C-unit CE2 satisfies property 3, the third C-unit CE3, the fourth C-unit CE4, the eighth C-unit CE8, the tenth C-unit CE10, and the twelfth C-unit CE12 satisfy property 2, and the other C-units satisfy property 1. Therefore, the CEs except the second C cell CE2 can output correct values, and obviously, the outputs of the sixth C cell CE6 and the eighth C cell CE8 are still the same values, so that N1 is restored to the same values, and similarly, N9 is restored to the same values. The outputs at the outputs of the first C-unit CE1 and the ninth C-unit CE9 are all restored to the original value, and N2 is restored to the original value, i.e., < N1, N2, N9> can be restored from TNU.

When TNU occurs for < N1, N3, N10>, the third C-unit CE3 satisfies property 3, the second C-unit CE2, the fourth C-unit CE4, the eighth C-unit CE8, the eleventh C-unit CE11, and the twelfth C-unit CE12 satisfy property 2, and the other C-units satisfy property 1. Therefore, all CEs except the third C unit CE3 can output correct values, and obviously, if the input of the first C unit CE1 is still the original value, N1 is restored to the original value, and similarly, if N10 is restored to the original value, the input of the third C unit CE3 is restored to the original value, and N3 is restored to the original value, that is, < N1, N3, N10> can be restored from the TNU.

When TNU occurs at < N1, N3, N9>, the second C cell CE2 satisfies property 3, the N2 generates a flip output error value, the fourth C cell CE4, the eighth C cell CE8, the tenth C cell CE10, and the twelfth C cell CE12 satisfy property 2, and the other C cells satisfy property 1. Therefore, the CEs except the second C cell CE2 can all output correct values, and obviously, the input of the first C cell CE1 is still the same value, so N1 is restored to the same value, and similarly, N9 is restored to the same value. The input at the input of the second C element CE2 is changed to the original value, and N2 is restored to the original value. The input at the input of the third C-element CE3 is changed to the original value, and N3 is restored to the original value, i.e., < N1, N3, N9> can be recovered from the TNU. Through analysis, the latch can realize the TNU self-recovery function under the condition.

From the above analysis, the latch is completely self-recovering for any three-node flip, and obviously, single-node flip and double-node flip can also be self-recovering.

In summary, the present invention improves the reliability of the latch circuit. Compared with the existing latch, the invention reduces the area and power consumption overhead, improves the tolerance capability of the latch and has more excellent performance. Furthermore, since in the transparent mode there is only one transmission gate between the input and the output, the invention creates a more efficient path and hence a low transmission delay. The invention is suitable for integrated circuits and systems with high reliability requirements in a strong radiation environment, and can be widely applied to the fields of nuclear tests, aerospace and the like with high requirements on the reliability of the latch.

Claims

1. The utility model provides a three-node upset self-resuming latch based on cyclic feedback C unit which characterized in that: the dual-cycle structure memory module comprises a dual-cycle structure memory module and four transmission gates, wherein the dual-cycle structure memory module consists of twelve two-input C units, and the twelve two-input C units comprise a first C unit CE1, a second C unit CE2, a third C unit CE3, a fourth C unit CE4, a fifth C unit CE5, a sixth C unit CE6, a seventh C unit CE7, an eighth C unit CE8, a ninth C unit CE9, a tenth C unit CE10, an eleventh C unit CE11 and a twelfth C unit CE 12; the four transmission gates include a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3 and a fourth transmission gate TG 4; the signal input ends of the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3 and the fourth transmission gate TG4 are all used as the data input end D of the latch, and the output end of the fifth C cell CE5 is used as the data output end of the latch.

2. The three-node flipped self-healing latch based on a cyclic feedback C-cell of claim 1, characterized in that: a first signal input terminal of the first C cell CE1 is connected to the output terminal N6 of the sixth C cell CE6, a second signal input terminal of the first C cell CE1 is connected to the output terminal N8 of the eighth C cell CE8, and an output terminal N1 of the first C cell CE1 is connected to a first input terminal of the second C cell CE2 and a second input terminal of the twelfth C cell CE 12; a second signal input terminal of the second C cell CE2 is connected to the output terminal N9 of the ninth C cell CE9, and an output terminal N2 of the second C cell CE2 is connected to a first input terminal of the third C cell CE3 and a first input terminal of the seventh C cell CE 7; a second signal input terminal of the third C cell CE3 is connected to the output terminal N10 of the tenth C cell CE10, and an output terminal N3 of the third C cell CE3 is connected to a first input terminal of the fourth C cell CE4 and a first input terminal of the eighth C cell CE 8; a second signal input terminal of the fourth C cell CE4 is connected to the output terminal N11 of the eleventh C cell CE11, and the output terminal N4 of the fourth C cell CE4 is connected to a first input terminal of the fifth C cell CE5 and a second input terminal of the ninth C cell CE 9; a second signal input terminal of the fifth C cell CE5 is connected to the output terminal N12 of the twelfth C cell CE12, and an output terminal N5 of the fifth C cell CE5 is connected to a first input terminal of the sixth C cell CE6 and a first input terminal of the tenth C cell CE 10; a second signal input terminal of the sixth C cell CE6 is connected to the output terminal N7 of the seventh C cell CE7, and the output terminal N6 of the sixth C cell CE6 is connected to the first input terminal of the eleventh C cell CE 11; a second signal input terminal of the seventh C cell CE7 is connected to the output terminal N12 of the twelfth C cell CE12, and the output terminal N7 of the seventh C cell CE7 is connected to a second input terminal of the sixth C cell CE6 and a second input terminal of the eighth C cell CE 8; a first signal input terminal of the ninth C-cell CE9 is connected to the output terminal N8 of the eighth C-cell CE 8; a second signal input terminal of the tenth C-cell CE10 is connected to the output terminal N9 of the ninth C-cell CE 9; a second signal input terminal of the eleventh C-cell CE11 is connected to the output terminal N10 of the tenth C-cell CE 10; a first signal input terminal of the twelfth C-cell CE12 is connected to the output terminal N11 of the eleventh C-cell CE 11.

3. The three-node flipped self-healing latch based on a cyclic feedback C-cell of claim 1, characterized in that: a signal output end of the first transmission gate TG1 is connected to a first input end of a fourth C cell CE4 and a first input end of an eighth C cell CE8, respectively; a signal output end of the second transmission gate TG2 is connected to a first signal input end of the sixth C unit and a first input end of the tenth C unit CE10, respectively; a signal output end of the third transmission gate TG3 is connected to a second input end of the sixth C cell CE6 and a second input end of the eighth C cell CE8, respectively; a signal output terminal of the fourth transmission gate TG4 is connected to a second input terminal of the second C cell CE2 and a second input terminal of the tenth C cell CE10, respectively.

4. The three-node flipped self-healing latch based on a cyclic feedback C-cell according to claim 1 or 3, characterized in that: the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3 and the fourth transmission gate TG4 are all composed of a PMOS transistor and an NMOS transistor, and the sources of the PMOS transistor and the NMOS transistor are connected together and used as the input of the transmission gates; the drains of the PMOS transistor and the NMOS transistor are connected together and used as the output of the transmission gate; the gate of the NMOS transistor is connected to the system clock signal CLK, and the gate of the PMOS transistor is connected to the inverted system clock signal NCK.

5. The three-node flipped self-healing latch based on a cyclic feedback C-cell of claim 1, characterized in that: the twelve two-input C units have the same structure, the first C unit CE1 consists of two PMOS tubes and two NMOS tubes, the two PMOS tubes comprise a first PMOS tube MP11 and a second PMOS tube MP12, and the two NMOS tubes comprise a first NMOS tube MN11 and a second NMOS tube MN 12;

6. The three-node flipped self-healing latch based on a cyclic feedback C-cell of claim 1, characterized in that: when the system clock signal CLK = 0 and the inverted system clock signal NCK = 1, the signal output terminal N5 of the fifth C-cell CE5 serves as the data output terminal of the latch; the signal output terminal of the second transmission gate TG2 serves as the data output terminal of the latch when the system clock signal CLK = 1 and the inverted system clock signal NCK = 0.