CN107332552B - Tolerant double-point flip latch based on double-input phase inverter - Google Patents
Tolerant double-point flip latch based on double-input phase inverter Download PDFInfo
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- CN107332552B CN107332552B CN201710538183.6A CN201710538183A CN107332552B CN 107332552 B CN107332552 B CN 107332552B CN 201710538183 A CN201710538183 A CN 201710538183A CN 107332552 B CN107332552 B CN 107332552B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/0033—Radiation hardening
- H03K19/00338—In field effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
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- H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
Abstract
The invention provides a tolerant double-point overturning latch based on a double-input inverter, which comprises at least three inverter channels; each path of phase inverter channel comprises an input transmission gate, six double-input phase inverters and an output transmission gate which are connected in sequence; the input transmission gate and the output transmission gate are both CMOS transmission gates and are provided with input ends, output ends, P ends and N ends, and the double-input phase inverter is provided with a first input end, a second input end and an output end. Compared with the prior art, the invention has the beneficial effects that: compared with the traditional single-particle single-point upset resistant sequential element, the single-particle single-point upset tolerant sequential element disclosed by the invention can tolerate single-particle single-point upset and single-particle double-point upset, and the reliability of the circuit is greatly improved.
Description
Technical Field
The invention relates to the field of integrated circuit design, in particular to the field of anti-radiation reinforcement design of an integrated circuit, and specifically relates to a double-point turnover tolerant latch based on a double-input inverter.
Background
For digital circuits applied in space environment, especially for sequential circuits, single event upset can seriously affect the correctness of chip functions. Most of the existing reinforcement technologies are directed to SEU, but as the size of an integrated circuit is reduced and the power supply voltage of a chip is reduced, the key charges which can be stored in the internal nodes of the circuit are greatly reduced. Research shows that after the integrated circuit technology enters 90nm, the probability of single-particle double-point upset caused by radiation effect gradually rises, and therefore the performance of the circuit is affected. In a sequential element (such as a latch), the single event effect is mainly expressed as single event single-point upset and single event double-point upset. The single-particle single-point upset can be explained as that the charge generated by a single particle is collected by one node in the latch, and the logic state of the node is changed to cause the data latched by the latch to be overturned; the single-event double-point upset can be explained as that the charge generated by a single event is shared between two nodes of a latch, and the logic states of the two nodes are changed simultaneously, so that the data latched by the latch is also inverted.
In the early development stage of integrated circuits, the space between circuit nodes is large, and the charge sharing effect is not obvious, so that single-particle single-point upset occupies a dominant position, and a plurality of strengthened sequential elements resisting the single-particle single-point upset appear. With the continuous development of integrated circuits, the sizes of transistors are gradually reduced, and the distances between circuit nodes are smaller and smaller. This results in an increased probability that the charge generated by a single event is shared by two nodes, and single event double-dot inversion becomes more severe. This puts higher demands on the anti-irradiation reinforcement design of the integrated circuit, and the reinforcement design of resisting single-particle double-point upset becomes a research hotspot. Latches are frequently used memory cells in circuits, and are particularly important for the reinforcement of latches. Common Design hardening methods (RHBD) include code-level hardening, circuit-level hardening, layout-level hardening, and the like. The circuit level reinforcement method is used for example for classical multi-mode redundancy, for example, single-particle single-point upset tolerance by using triple-mode redundancy and single-particle double-point upset tolerance by using quintic-mode redundancy. But this type of approach introduces a large latency overhead and power consumption overhead.
Disclosure of Invention
In order to solve the technical defects in the prior art, the invention provides the double-point upset tolerant latch based on the double-input inverter, the latch can tolerate single-particle single-point upset and single-particle double-point upset, the problem that the latch data upset caused by high-energy radiation particles causes circuit failure is solved, and the reliability of the circuit is greatly improved.
The invention is realized by the following technical scheme:
a tolerant double-point flip latch based on a double-input inverter is characterized by comprising at least three inverter channels; each path of the phase inverter channel comprises an input transmission gate, six double-input phase inverters and an output transmission gate which are connected in sequence; the input transmission gate and the output transmission gate are both CMOS transmission gates and are provided with input ends, output ends, P ends and N ends, and the double-input phase inverter is provided with a first input end, a second input end and an output end;
the input ends of all the input transmission gates are used as the data input end of the latch together;
in one channel of phase inverter, the first input end of a first double-input phase inverter is respectively connected with the output end of an input transmission gate and the output end of an output transmission gate in the channel, and the second input end of the double-input phase inverter is respectively connected with the output end of the input transmission gate and the output end of the output transmission gate in the other channel of phase inverter;
in one channel of the phase inverter, the first input end of the latter double-input phase inverter is connected with the output end of the former double-input phase inverter in the channel, and the second input end of the double-input phase inverter is connected with the output end of the former double-input phase inverter at the corresponding position in the other channel of the phase inverter;
in one channel of phase inverter, the output end of the last double-input phase inverter is connected with the input end of an output transmission gate in the channel;
the output end of the input transmission gate and the output end of the output transmission gate in one path of the inverter channel are jointly used as the data output end of the latch;
the N ends of all input transmission gates and the P ends of all output transmission gates are used as a first clock signal input end of the latch together; the P ends of all the input transmission gates and the N ends of all the output transmission gates are used as a second clock signal input end of the latch together. Compared with the prior art, the invention has the beneficial effects that:
compared with the traditional single-particle single-point upset resistant sequential element, the single-particle single-point upset tolerant sequential element disclosed by the invention can tolerate single-particle single-point upset and single-particle double-point upset, and the reliability of the circuit is greatly improved.
Drawings
Fig. 1 is a schematic diagram of a two-point flip tolerant latch based on a two-input inverter according to the present invention.
Fig. 2 is a schematic diagram of a two-input inverter.
Throughout the drawings, the same reference numerals are used to designate the same elements or structures, including:
the circuit comprises a first input transmission gate 1, a second input transmission gate 2, a third input transmission gate 3, a first output transmission gate 4, a second output transmission gate 5, a third output transmission gate 6, a first dual-input inverter 7, a second dual-input inverter 8, a third dual-input inverter 9, a fourth dual-input inverter 10, a fifth dual-input inverter 11, a sixth dual-input inverter 12, a seventh dual-input inverter 13, an eighth dual-input inverter 14, a ninth dual-input inverter 15, a tenth dual-input inverter 16, an eleventh dual-input inverter 17, a twelfth dual-input inverter 18, a thirteenth dual-input inverter 19, a fourteenth dual-input inverter 20, a fifteenth dual-input inverter 21, a sixteenth dual-input inverter 22, a seventeenth dual-input inverter 23 and an eighteenth dual-input inverter 24.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the detailed description and specific examples, while indicating the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.
Example 1:
a tolerant double-point flip latch based on a double-input inverter comprises at least three inverter channels; each path of phase inverter channel comprises an input transmission gate, six double-input phase inverters and an output transmission gate which are connected in sequence; the input transmission gate and the output transmission gate are both CMOS transmission gates and are provided with input ends, output ends, P ends and N ends, and the double-input phase inverter is provided with a first input end, a second input end and an output end.
The inputs of all input transmission gates together serve as the data input of the latch.
In one channel of the phase inverter, the first input end of a first double-input phase inverter is respectively connected with the output end of the input transmission gate and the output end of the output transmission gate in the channel, and the second input end of the double-input phase inverter is respectively connected with the output end of the input transmission gate and the output end of the output transmission gate in the other channel of the phase inverter.
In one channel of the phase inverter, the first input end of the latter double-input phase inverter is connected with the output end of the former double-input phase inverter in the channel, and the second input end of the double-input phase inverter is connected with the output end of the former double-input phase inverter at the corresponding position in the other channel of the phase inverter.
In one channel of the phase inverter, the output end of the last double-input phase inverter is connected with the input end of the output transmission gate in the channel.
And the output end of the input transmission gate and the output transmission gate in one channel of the phase inverter channel are jointly used as the data output end of the latch.
The N ends of all the input transmission gates and the P ends of all the output transmission gates are used as a first clock signal input end of the latch together; the P ends of all the input transmission gates and the N ends of all the output transmission gates are used as a second clock signal input end of the latch together.
Example 2:
as shown in fig. 1, this embodiment provides a specific example of a two-point flip-flop tolerant latch based on a two-input inverter, and this embodiment adopts six transmission gates and eighteen two-input inverters, and the specific structure includes: a first inverter channel, a second inverter channel, and a third inverter channel; wherein:
the first inverter channel comprises a first input transmission gate 1, a first dual-input inverter 7, a second dual-input inverter 8, a third dual-input inverter 9, a fourth dual-input inverter 10, a fifth dual-input inverter 11, a sixth dual-input inverter 12 and a first output transmission gate 4.
The second inverter channel comprises a second input transmission gate 2, a seventh two-input inverter 13, an eighth two-input inverter 14, a ninth two-input inverter 15, a tenth two-input inverter 16, an eleventh two-input inverter 17, a twelfth two-input inverter 18 and a second output transmission gate 5.
The third inverter channel comprises a third input transmission gate 3, a thirteenth two-input inverter 19, a fourteenth two-input inverter 20, a fifteenth two-input inverter 21, a sixteenth two-input inverter 22, a seventeenth two-input inverter 23, an eighteenth two-input inverter 24 and a third output transmission gate 6.
The three input transmission gates and the three output transmission gates are all CMOS transmission gates and are provided with input ends, output ends, P ends and N ends; eighteen dual-input inverters each include a first input, a second input, and an output.
The input terminal of the first input transmission gate 1, the input terminal of the second input transmission gate 2 and the input terminal of the third input transmission gate 3 are used as the data input terminal of the latch together.
A first input terminal of the first dual-input inverter 7 is connected to the output terminal of the first input transmission gate 1 and the output terminal of the first output transmission gate 4, respectively, and a second input terminal of the first dual-input inverter 7 is connected to the output terminal of the third input transmission gate 3 and the output terminal of the third output transmission gate 6, respectively.
A first input of the second two-input inverter 8 is connected to the output of the first two-input inverter 7, and a second input of the second two-input inverter 8 is connected to the output of the thirteenth two-input inverter 19.
A first input terminal of the third two-input inverter 9 is connected to an output terminal of the second two-input inverter 8, and a second input terminal of the third two-input inverter 9 is connected to an output terminal of the fourteenth two-input inverter 20.
A first input of the fourth two-input inverter 10 is connected to an output of the third two-input inverter 9, and a second input of the fourth two-input inverter 10 is connected to an output of the fifteenth two-input inverter 21.
A first input end of the fifth two-input inverter 11 is connected to an output end of the fourth two-input inverter 10, and a second input end of the fifth two-input inverter 11 is connected to an output end of the sixteenth two-input inverter 22.
A first input end of the sixth dual-input phase inverter 12 is connected with an output end of the fifth dual-input phase inverter 11, a second input end of the sixth dual-input phase inverter 12 is connected with an output end of the seventeenth dual-input phase inverter 23, and an output end of the sixth dual-input phase inverter 12 is connected with an input end of the first output transmission gate 4.
A first input end of the seventh dual-input inverter 13 is connected with an output end of the second input transmission gate 2 and an output end of the second output transmission gate 5, respectively, and a second input end of the seventh dual-input inverter 13 is connected with an output end of the first input transmission gate 1 and an output end of the first output transmission gate 4, respectively.
A first input terminal of the eighth two-input inverter 14 is connected to an output terminal of the seventh two-input inverter 13, and a second input terminal of the eighth two-input inverter 14 is connected to an output terminal of the first two-input inverter 7.
A first input terminal of the ninth two-input inverter 15 is connected to an output terminal of the eighth two-input inverter 14, and a second input terminal of the ninth two-input inverter 15 is connected to an output terminal of the second two-input inverter 8.
A first input end of the tenth two-input inverter 16 is connected to an output end of the ninth two-input inverter 15, and a second input end of the tenth two-input inverter 16 is connected to an output end of the third two-input inverter 9.
A first input terminal of the eleventh two-input inverter 17 is connected to an output terminal of the tenth two-input inverter 16, and a second input terminal of the eleventh two-input inverter 17 is connected to an output terminal of the fourth two-input inverter 10.
A first input end of the twelfth two-input inverter 18 is connected with an output end of the eleventh two-input inverter 17, a second input end of the twelfth two-input inverter 18 is connected with an output end of the fifth two-input inverter 11, and an output end of the twelfth two-input inverter 18 is connected with an input end of the second output transmission gate 5.
A first input terminal of the thirteenth two-input inverter 19 is connected to the output terminal of the third input transmission gate 3 and the output terminal of the third output transmission gate 6, respectively, and a second input terminal of the seventh two-input inverter 13 is connected to the output terminal of the second input transmission gate 2 and the output terminal of the second output transmission gate 5, respectively.
A first input terminal of the fourteenth two-input inverter 20 is connected to an output terminal of the thirteenth two-input inverter 19, and a second input terminal of the fourteenth two-input inverter 20 is connected to an output terminal of the seventh two-input inverter 13.
A first input terminal of the fifteenth two-input inverter 21 is connected to an output terminal of the fourteenth two-input inverter 20, and a second input terminal of the fifteenth two-input inverter 21 is connected to an output terminal of the eighth two-input inverter 14.
A first input terminal of the sixteenth two-input inverter 22 is connected to the output terminal of the fifteenth two-input inverter 21, and a second input terminal of the sixteenth two-input inverter 22 is connected to the output terminal of the ninth two-input inverter 15.
A first input end of the seventeenth two-input inverter 23 is connected to an output end of the sixteenth two-input inverter 22, and a second input end of the seventeenth two-input inverter 23 is connected to an output end of the tenth two-input inverter 16.
A first input end of the eighteenth dual-input inverter 24 is connected with an output end of the seventeenth dual-input inverter 23, a second input end of the eighteenth dual-input inverter 24 is connected with an output end of the eleventh dual-input inverter 17, and an output end of the eighteenth dual-input inverter 24 is connected with an input end of the third output transmission gate 6.
The input of the first output transmission gate 4 and the output of the first output transmission gate 4 together serve as the output of the latch.
The N ends of the first input transmission gate 1, the second input transmission gate 2 and the third input transmission gate 3 and the P ends of the first output transmission gate 4, the second output transmission gate and the third output transmission gate 6 are used as a first clock signal input end of the latch together; the P ends of the first input transmission gate 1, the second input transmission gate 2 and the third input transmission gate 3 and the N ends of the first output transmission gate 4, the second output transmission gate and the third output transmission gate 6 are used as a second clock signal input end of the latch together. In this embodiment, a specific structure of a dual-input inverter is shown in fig. 2, and the dual-input inverter includes a PMOS transistor MP1 and an NMOS transistor MN 1; the grid electrode of the PMOS tube MP1 is connected with a first input end IN1 of the double-input phase inverter, and the grid electrode of the NMOS tube MN1 is connected with a second input end IN2 of the double-input phase inverter; the source electrode of the PMOS tube MP1 and the substrate of the PMOS tube MP1 are both connected with a power supply, and the source electrode of the NMOS tube MN1 and the substrate of the NMOS tube MN1 are both connected with the ground; the drain electrode of the PMOS tube MP1 and the drain electrode of the NMOS tube MN1 are both connected with the output end OUT of the dual-input inverter.
As can be seen from table 1, when the logic values obtained by the first signal input terminal IN1 and the second signal input terminal IN2 are both 0 or both 1, the signal output terminal OUT provides the opposite logic value, and the two-input inverter behaves as an inverter; when the logic value of the first signal input terminal IN1 changes from 0 to 1 and the logic value of the second signal input terminal IN2 remains unchanged, the signal output terminal OUT enters a hold state; when the logic value of the second signal input terminal IN2 changes from 0 to 1 and the logic value of the first signal input terminal IN1 remains unchanged, the logic value of the signal output terminal OUT changes from 1 to 0; when the logic value of the first signal input terminal IN1 changes from 1 to 0 and the logic value of the second signal input terminal IN2 remains unchanged, the signal output terminal OUT enters a hold state; when the logic value of the first signal input terminal IN1 is unchanged while the logic value of the second signal input terminal IN2 is changed from 1 to 0, the signal output terminal OUT enters a hold state.
| IN1 | IN2 | OUT |
| 0→1 | 0 | 1 (invariable) |
| 0 | 0→1 | 1→0 |
| 1→0 | 1 | 0 (invariable) |
| 1 | 1→0 | 0 (invariable) |
Table 1 dual input inverter truth table in latch
The specific technical principle of the embodiment is as follows:
the principle of the invention against single particle double-dot inversion is discussed next. Considering that a reinforcement design can tolerate single-particle single-point upset certainly if single-particle double-node upset can be tolerated, the analysis and discussion of the single-particle single-point upset can be skipped.
Referring to fig. 1, when the first clock signal input terminal CLK is at a low level and the second clock signal input terminal CLKB is at a high level, the first input transmission gate 1, the second input transmission gate 2, and the third input transmission gate 3 are turned off, the first output transmission gate 4, the second output transmission gate 5, and the third output transmission gate 6 are turned on, and the latch operates in a latch period. At this time, eighteen dual-input inverters are in a highly redundant state, and are used for holding data and tolerating double-node inversion. During the latch period, assuming that the latch holds a logic value of 0, the same can discuss the case when the logic value 1 is held, that is, the logic value of the data output terminal qout is 0, the logic values of the internal nodes a1, a2, A3, C1, C2, C3, E1, E2, E3, G1, G2, and G3 are 0, and the logic values of B1, B2, B3, D1, D2, D3, F1, F2, and F3 are 1. Assuming that a single particle bombards a latch, the charge generated by ionization is shared between internal nodes a1 and B1, which can discuss the situation that the charge is shared between any pair of nodes a1, a2, A3, B1, B2, B3, C1, C2, C3, D1, D2, D3, E1, E2, E3, F1, F2, F3, G1, G2, and G3, that is, the logic of nodes a1 and B1 is flipped at the same time, the logic of node a1 is flipped to 1, and the logic of node B1 is flipped to 0. At this time, the logic values of the two input ends of the first dual-input inverter 7, the second dual-input inverter 8, the fourth dual-input inverter 10 and the fifth dual-input inverter 11 are all different, the logic value of the output end B2 of the second dual-input inverter 8 is changed from 1 to 0, the logic value of the output end C2 of the fourth dual-input inverter 11 is changed from 0 to 1, the logic value of the output end D3 of the ninth dual-input inverter 15 is changed from 1 to 0, the error signal is blocked by the tenth dual-input inverter 16, the eleventh dual-input inverter 17 and the twelfth dual-input inverter 18, the sixteenth dual-input inverter 22, the seventeenth dual-input inverter 23 and the eighteenth dual-input inverter 24 restore the a1 to the correct logic value, then the B1 and B2 to the correct logic values, and then the C2 and D3 to the correct logic values. The affected nodes a1 and B1 are then both able to achieve self-recovery.
The invention has the advantages that the invention is described by combining the technical principle:
the problem of double-node overturning caused by single particle bombardment is solved, and the reliability of the circuit is improved. When any two nodes (any two nodes of A1, A2, A3, B1, B2, B3, C1, C2, C3, D1, D2, D3, E1, E2, E3, F1, F2, F3, G1, G2 and G3) are logically overturned due to the bombardment of single particles, the overturned node pair can be self-restored to a correct logic value through eighteen DINV cells. The invention is suitable for integrated circuit systems with high reliability and can be applied to the fields of aerospace, aviation and the like.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (3)
1. A tolerant double-point flip latch based on a double-input inverter is characterized by comprising at least three inverter channels; each path of the phase inverter channel comprises an input transmission gate, six double-input phase inverters and an output transmission gate which are connected in sequence; the input transmission gate and the output transmission gate are both CMOS transmission gates and are provided with input ends, output ends, P ends and N ends, and the double-input phase inverter is provided with a first input end, a second input end and an output end;
the input ends of all the input transmission gates are used as the data input end of the latch together;
in one channel of phase inverter, the first input end of a first double-input phase inverter is respectively connected with the output end of an input transmission gate and the output end of an output transmission gate in the channel, and the second input end of the double-input phase inverter is respectively connected with the output end of the input transmission gate and the output end of the output transmission gate in the other channel of phase inverter;
in one channel of the phase inverter, the first input end of the latter double-input phase inverter is connected with the output end of the former double-input phase inverter in the channel, and the second input end of the double-input phase inverter is connected with the output end of the former double-input phase inverter at the corresponding position in the other channel of the phase inverter;
in one channel of phase inverter, the output end of the last double-input phase inverter is connected with the input end of an output transmission gate in the channel;
the output end of the input transmission gate and the output end of the output transmission gate in one path of the inverter channel are jointly used as the data output end of the latch;
the N ends of all input transmission gates and the P ends of all output transmission gates are used as a first clock signal input end of the latch together; the P ends of all the input transmission gates and the N ends of all the output transmission gates are used as a second clock signal input end of the latch together.
2. The dual-input inverter based double-point flip tolerant latch of claim 1, comprising: a first inverter channel, a second inverter channel, and a third inverter channel; wherein the content of the first and second substances,
the first phase inverter channel comprises a first input transmission gate, a first double-input phase inverter, a second double-input phase inverter, a third double-input phase inverter, a fourth double-input phase inverter, a fifth double-input phase inverter, a sixth double-input phase inverter and a first output transmission gate;
the second phase inverter channel comprises a second input transmission gate, a seventh double-input phase inverter, an eighth double-input phase inverter, a ninth double-input phase inverter, a tenth double-input phase inverter, an eleventh double-input phase inverter, a twelfth double-input phase inverter and a second output transmission gate;
the third inverter channel comprises a third input transmission gate, a thirteenth dual-input inverter, a fourteenth dual-input inverter, a fifteenth dual-input inverter, a sixteenth dual-input inverter, a seventeenth dual-input inverter, an eighteenth dual-input inverter and a third output transmission gate;
the three input transmission gates and the three output transmission gates are all CMOS transmission gates and are provided with input ends, output ends, P ends and N ends; the eighteen double-input phase inverters comprise a first input end, a second input end and an output end;
the input end of the first input transmission gate, the input end of the second input transmission gate and the input end of the third input transmission gate are used as the data input end of the latch together;
a first input end of the first double-input inverter is connected with an output end of the first input transmission gate and an output end of the first output transmission gate respectively, and a second input end of the first double-input inverter is connected with an output end of the third input transmission gate and an output end of the third output transmission gate respectively;
a first input end of the second dual-input inverter is connected with an output end of the first dual-input inverter, and a second input end of the second dual-input inverter is connected with an output end of the thirteenth dual-input inverter;
a first input end of the third dual-input inverter is connected with an output end of the second dual-input inverter, and a second input end of the third dual-input inverter is connected with an output end of the fourteenth dual-input inverter;
a first input end of the fourth dual-input phase inverter is connected with an output end of the third dual-input phase inverter, and a second input end of the fourth dual-input phase inverter is connected with an output end of the fifteenth dual-input phase inverter;
a first input end of the fifth dual-input phase inverter is connected with an output end of the fourth dual-input phase inverter, and a second input end of the fifth dual-input phase inverter is connected with an output end of the sixteenth dual-input phase inverter;
a first input end of the sixth dual-input phase inverter is connected with an output end of the fifth dual-input phase inverter, a second input end of the sixth dual-input phase inverter is connected with an output end of the seventeenth dual-input phase inverter, and an output end of the sixth dual-input phase inverter is connected with an input end of the first output transmission gate;
a first input end of the seventh dual-input phase inverter is connected with an output end of the second input transmission gate and an output end of the second output transmission gate respectively, and a second input end of the seventh dual-input phase inverter is connected with an output end of the first input transmission gate and an output end of the first output transmission gate respectively;
a first input end of the eighth dual-input inverter is connected with an output end of the seventh dual-input inverter, and a second input end of the eighth dual-input inverter is connected with an output end of the first dual-input inverter;
a first input end of the ninth dual-input inverter is connected with an output end of the eighth dual-input inverter, and a second input end of the ninth dual-input inverter is connected with an output end of the second dual-input inverter;
a first input end of the tenth dual-input phase inverter is connected with an output end of the ninth dual-input phase inverter, and a second input end of the tenth dual-input phase inverter is connected with an output end of the third dual-input phase inverter;
a first input end of the eleventh dual-input phase inverter is connected with an output end of the tenth dual-input phase inverter, and a second input end of the eleventh dual-input phase inverter is connected with an output end of the fourth dual-input phase inverter;
a first input end of the twelfth dual-input phase inverter is connected with an output end of the eleventh dual-input phase inverter, a second input end of the twelfth dual-input phase inverter is connected with an output end of the fifth dual-input phase inverter, and an output end of the twelfth dual-input phase inverter is connected with an input end of the second output transmission gate;
a first input end of the thirteenth dual-input phase inverter is connected with an output end of the third input transmission gate and an output end of the third output transmission gate respectively, and a second input end of the seventh dual-input phase inverter is connected with an output end of the second input transmission gate and an output end of the second output transmission gate respectively;
a first input end of the fourteenth dual-input inverter is connected with an output end of the thirteenth dual-input inverter, and a second input end of the fourteenth dual-input inverter is connected with an output end of the seventh dual-input inverter;
a first input end of the fifteenth two-input inverter is connected with an output end of the fourteenth two-input inverter, and a second input end of the fifteenth two-input inverter is connected with an output end of the eighth two-input inverter;
a first input end of the sixteenth dual-input phase inverter is connected with an output end of the fifteenth dual-input phase inverter, and a second input end of the sixteenth dual-input phase inverter is connected with an output end of the ninth dual-input phase inverter;
a first input end of the seventeenth dual-input phase inverter is connected with an output end of the sixteenth dual-input phase inverter, and a second input end of the seventeenth dual-input phase inverter is connected with an output end of the tenth dual-input phase inverter;
a first input end of the eighteenth dual-input phase inverter is connected with an output end of the seventeenth dual-input phase inverter, a second input end of the eighteenth dual-input phase inverter is connected with an output end of the eleventh dual-input phase inverter, and an output end of the eighteenth dual-input phase inverter is connected with an input end of the third output transmission gate;
the input end of the first output transmission gate and the output end of the first output transmission gate are used as the output end of the latch together
The N ends of the first input transmission gate, the second input transmission gate and the third input transmission gate and the P ends of the first output transmission gate, the second output transmission gate and the third output transmission gate are used as a first clock signal input end of the latch together; the P ends of the first input transmission gate, the second input transmission gate and the third input transmission gate and the N ends of the first output transmission gate, the second output transmission gate and the third output transmission gate are used as a second clock signal input end of the latch together.
3. The dual-input inverter-based double-point flip tolerant latch of claim 1 or 2, wherein the dual-input inverter comprises a PMOS transistor MP1 and an NMOS transistor MN 1; the grid electrode of the PMOS tube MP1 is connected with a first input end IN1 of the dual-input inverter, and the grid electrode of the NMOS tube MN1 is connected with a second input end IN2 of the dual-input inverter; the source electrode of the PMOS transistor MP1 and the substrate of the PMOS transistor MP1 are both connected with a power supply, and the source electrode of the NMOS transistor MN1 and the substrate of the NMOS transistor MN1 are both connected with the ground; the drain electrode of the PMOS tube MP1 and the drain electrode of the NMOS tube MN1 are both connected with the output end OUT of the dual-input phase inverter.
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