WO1996023355A1

WO1996023355A1 - A high-speed latch circuit including multiple transmission gates and a pipelined microprocessor employing the same

Info

Publication number: WO1996023355A1
Application number: PCT/US1996/000676
Authority: WO
Inventors: Marty L. Pflum; David B. Witt
Original assignee: Advanced Micro Devices, Inc.
Priority date: 1995-01-25
Filing date: 1996-01-22
Publication date: 1996-08-01
Also published as: JPH09511117A; CN1147882A; EP0752174A1

Abstract

A latch circuit is provided wherein a first transmission gate is electrically coupled in series with a second transmission gate between an input line and an output line. The latch circuit is controlled by a single clock signal wherein a delay element is employed to simultaneously enable both transmission gates upon an edge of the clock signal. The length of time during which both transmission gates are enabled is determined by an electrical delay associated with the delay element. When both transmission gates are enabled, the input line is electrically coupled to the output line. A keeper circuit at the output of the second transmission gate retains a logical value at the output of the latch after the input line is decoupled from the output line. In one implementation, the delay element is implemented with a set of serially coupled inverters, and the length of the time delay controls the time window during which both transmission gates are enabled. The latch circuit may be employed between pipeline stages in a processor.

Description

A HIGH-SPEED LATCH CIRCUIT INCLUDING

MULTIPLE TRANSMISSION GATES AND A PIPELINED

MICROPROCESSOR EMPLOYING THE SAME

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to latch circuits and more particularly to latch circuits employed within pipelined microprocessors.

2. Description of the Relevant Art

Almost all modern microprocessors use a technique called pipelining to increase throughput at relatively low cost. Pipelining involves partitioning a process with "n" steps into "n" hardware stages separated by memory elements called registers which hold intermediate results. There is one pipeline stage for each step in the process, and these stages are connected in the same order that the steps are performed. By allowing each of the "n" stages to operate concurrently, the pipelined process can potentially operate at "n" times the rate of the non-pipelined process.

Pipelining is desirable when the propagation delay times of the stages are large relative to the propagation delay times of the registers. If the propagation delay times associated with the registers are significant compared to the propagation delay times of the stages, the performance benefits of pipelining are diminished. The propagation delay times of the registers continue to be barriers to achieving the theoretical "n"-fold increase in throughput. As a result, particularly close attention is paid to the designs of registers between pipeline stages in microprocessors. Every effort is made to minimize the propagation delay times of these registers.

A plurality of single latches is often used to implement a registers coupled between stages in pipelined microprocessors. Figure 1 is a schematic diagram of a typical single latch employed between pipeline stages wherein a clock signal CLK and its complement are provided to control a transmission gate 104. When the CLK signal is logic high, transmission gate 104 is enabled, thereby electrically coupling 3355 PCJ7US96/00676

input signal IN to node A. Inverter 106 drives output terminal OUT with the complement of the logical value at node A. Inverter 108 is a "trickle" feedback inverter provided to retain the logical value at node A after transmission gate 104 is disabled. Such a trickle inverter is characterized as a "weak" inverter whereby its output may be overpowered by the input signal IN when transmission gate 104 is enabled.

The simplicity of single latches results in relatively short propagation delay times and low costs. For the latch circuit of Figure 1, output signal OUT is the logical complement of the input signal IN as long as clock signal CLK is logic high, and remains the logical complement of the last value of IN when CLK transition to logic low. This "transparency" property of latches may cause timing problems if the same clock signal is used to control the latch circuits associated with two successive pipeline stages. That is, if the latches of two successive pipeline stages are enabled simultaneously for a period of time longer than the propagation delay time of the first pipeline stage, a timing problem typically referred to as a race condition is created. When a race condition occurs, changes in logic levels may pass through the first stage and permanently into the second stage during the same clock cycle, thus leading to logic errors. Therefore, to eliminate possible race conditions, pipelined processors have long employed a technique of supplying alternate latches with clock signals which do not overlap (i.e., never enable two successive latches simultaneously).

As integrated circuit manufacturing processes improve, more and more devices and their interconnections are placed on a single dice or "chip." For very high speed microprocessors, the ability to generate and distribute high resolution two-phase clock signals which do not overlap is greatly diminished due to the capacitive loading on the clock drivers. "Clock skew" occurs when two clock signals travel along different paths with different delay times, arriving at different latches at different times. If this clock skew is severe enough, one clock signal may overlap the other, thus creating the possibility of race conditions as discussed previously. Relatively slow rise and fall times of the clock signals may further increase the effective overlapping. SUMMARY OF THE INVENTION

The problems outlined above are in large part solved by a high-speed latch circuit including multiple transmission gates in accordance with the present invention. In one embodiment, a latch circuit is provided wherein a first transmission gate is electrically coupled in series with a second transmission gate between an input line and an output line. The latch circuit is controlled by a single clock signal wherein a delay element is employed to simultaneously enable both transmission gates upon an edge of the clock signal. The length of time during which both transmission gates are enabled is determined by an electrical delay associated with the delay element. When both transmission gates are enabled, the input line is electrically coupled to the output line. A keeper circuit at the output of the second transmission gate retains a logical value at the output of the latch after the input line is decoupled from the output line by disabling the first transmission gate. In one implementation, the delay element is implemented with a set of serially coupled inverters, and the length of the time delay controls the time window during which both transmission gates are enabled.

When the latch circuit is employed between stages in a pipelined microprocessor, the latch circuit advantageously allows operation with a single clock signal with relatively low transition count. High frequencies of operation of the pipelined microprocessor are accommodated since the propagation time associated with the latch circuit is relatively low. Accordingly, the percent of delay cycle time utilized by the pipeline latch is relatively low. Race conditions may further be eliminated and capacitive loading of the clock driver may be reduced. In addition, by modifying the delay characteristics of the delay element, the latch circuit may be adjusted to operate optimally even if a new process technology is employed in fabrication to replace the one it was originally manufactured in. Finally, in one embodiment an inverter receiving the clock signal is configured with a relatively high trip point to ensure that ground noise does not falsely triggering the latch circuit.

The invention contemplates a latch circuit comprising a data input node for receiving an input signal, a first transmission gate having a first terminal coupled to the data input node and a second transmission gate. A first terminal of the second transmission gate is coupled to a second terminal of the first transmission gate, and a control terminal of the second transmission gate is coupled to receive a clock signal. A keeper circuit is also coupled to the second terminal of the second transmission gate, wherein the keeper circuit is capable of mamtaining a logic value at the second terminal of the second transmission gate. A delay element is finally coupled to a control terminal of the first transmission gate, wherein the delay element is capable of delaying the clock signal to thereby provide a delayed clock signal to the control terminal of the first transmission gate.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which:

Figure 1 is a schematic diagram of a typical static latch.

Figure 2 is a schematic diagram of a high-speed latch for single-clock systems which is enabled on the rising edge of the clock signal.

Figure 3 is a timing diagram associated with the operation of the high-speed latch for single-clock systems.

Figure 4 is a block diagram of a pipelined microprocessor employing latches controlled by a single system clock in accordance with the present invention.

Figure 5 is a schematic diagram of a high-speed latch for single-clock systems which is enabled on the falling edge of the clock signal.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.

DETAILED DESCRIPTION OF THE INVENTION

Referring next to Figure 2, a schematic diagram of a high-speed latch circuit 200 in accordance with the present invention is shown. Latch circuit 200 includes a first transmission gate 202, a second transmission gate 204, and an inverter 206 coupled serially between an input line 208 and an output line 210. The latch circuit 200 further comprises a pair of inverters 212 and 214 providing outputs to transmission gate 204. The input of inverter 212 is coupled to a clock input line 216. A delay element 218 is further coupled to the output of inverter 214. In the embodiment of Figure 2, delay element 218 includes inverters 220, 222 and 224. An inverter 226 is coupled between the output of delay element 218 and a control terminal of transmission gate 202, and a keeper circuit 228 is shown coupled to the input of inverter 206.

Keeper circuit 228 is illustrated with an inverter 230 coupled to a trickle inverter 232. As will be appreciated by those of skill in the art, keeper circuit 228 is employed to ensure that the logical value at node B is maintained even after an input signal IN is electrically decoupled from node B (i.e., by disabling transmission gate 202). Inverter 230 has as its input the logical value at node B and its output drives the logical complement of the logical value at node B. Inverter 232 is a weak "trickle" inverter which has as its input the logical complement of the logical value at node B, and its output drives node B with the same logic value present at node B. Thus, trickle inverter 232 enables the keeper circuit to maintain the logic value at node B, and yet allow the logical value at node B to be overpowered (and thus changed) changed by input signal IN.

The operation of latch 200 will next be described in conjunction with the timing diagram of Figure 3. Referring collectively to Figures 2 and 3, during a region A when clock signal CLK is low, the output of inverter 212 is logic high, and the output of inverter 214 is logic low. Transmission gate 204 is thus disabled. The output of delay element 218 is logic high, and the output of inverter 226 is logic low. Transmission gate 202 is thus enabled, electrically coupling input line 208 to node A. It is noted that while transmission gate 204 is disabled, input line 208 is decoupled from output line 210. This decoupling prevents input signals from passing though the latch during region A, thus preventing race conditions.

In the one embodiment, inverter 212 is configured with a relatively high trip point, thereby preventing noise on clock input line 216 from inadvertently triggering latch circuit 200. During region B when clock signal CLK exceeds the trip point of inverter 212, the output of inverter 212 transitions to logic low, and the output of inverter 214 transitions to logic high one gate delay later. Transmission gate 204 is thus enabled. It is noted that the control inputs of transmission gate 202 do not change until after signal CLK has propagated through delay element 218. Thus transmission gate 202 remains enabled during region B as determined by the delay time of delay element 218, and node B attains the logic value of input signal IN at input line 208. It will be appreciated that in doing so, input signal IN must overcome any charge sharing from node B to node A as well as overpower the drive current of "trickle" inverter 226 in keeper circuit 222.

After the high transition of the clock signal CLK has propagated through delay element 218, the output of delay element 218 transitions to logic low, and the output of inverter 226 transitions to logic high one gate delay later. Transmission gate 202 is thus disabled, electrically decoupling node A from input line 208. This marks the end of region B of Figure 3.

During region C when clock signal CLK is logic high, the output of inverter

212 is logic low and the output of inverter 214 is logic high. Transmission gate 204 thus remains enabled, electrically coupling node A to node B. At this time, the output of delay element 218 is logic low, and the output of inverter 226 is logic high. Thus transmission gate 202 is disabled. Output inverter 206 drives output line 210 with the logical complement of the logic value at node B. Keeper circuit 228 ensures the logic value at node B is retained even after the input signal IN is electrically decoupled from node B.

During region D, clock signal CLK drops below the trip point of inverter 212. The output of inverter 212 accordingly transitions to logic high, and the output of inverter 214 transitions to logic low. Transmission gate 204 is thus disabled, electrically decoupling node B from node A. The control inputs of transmission gate 202 will not change for a delay time as determined by delay element 218. Thus transmission gate 202 also remains disabled. Keeper circuit 228 continues to maintain the logic value stored at node B, and output inverter 206 drives output line 210 with the logical complement of the logic value stored at node B.

After the low transition of the clock signal CLK has propagated through delay element 218, the output of delay element 218 transitions to logic high, and the output of inverter 226 transitions to logic low one gate delay later. Transmission gate 202 is thus enabled, electrically coupling node A to input line 208 subsequent cycles of the clock signal CLK result in a similar operation. Referring now to Figure 4, a block diagram of generalized portion of a pipelined microprocessor 400 which employs a plurality of latch circuits 200A-200D each embodied in accordance with the schematic diagram of Figure 2 is shown. Each latch circuit 200 is controlled by a single system clock CLK at line 406. A combinational logic circuit 402 which forms a first pipeline stage "n" is coupled to latches 200 A and 200B. A second combinational logic circuit 404 which forms a pipeline stage "n+1", has its inputs coupled to latches 200A and 200B and its outputs coupled to latched 200C and 200D. Latches 200A-200D receive a common clock input CLK through clock line 406. It will be appreciated that additional latch circuits may be similarly coupled between the pipeline stages of microprocessor 400.

Microprocessor 400 is configured such that while operating, valid output signals of combinational logic circuit 402 (pipeline stage "n") are assumed to reach the IN terminals of latches 200 A and 200B by the end of region B of Figure 3. Likewise, valid output signals of combinational logic circuit 404 (pipeline stage "n+1") are assumed to reach the IN terminals of latches 200C and 200D by the end of region B of Figure 3. During region B of Figure 3, the outputs of combinational logic circuit 402 are stored in latches 200A and 200B, and the outputs of combinational logic circuit 404 are stored in latches 200C and 200D. The logical complements of the output signals from combinational logic circuit 402 as stored by latches 200A and 200B are thus provided to the input lines of combinational logic circuit 404 (pipeline stage "n+1") during regions C, D, and region A of the next cycle of system clock CLK. Similarly, the logical complements of the output signals from combinational logic circuit 404 as stored by latches 200C and 200D may be provided to the input lines of a subsequent pipeline stage (not shown) during regions C, D, and region A of the next cycle of system clock CLK.

A latch circuit configured in accordance with the present invention may be advantageously employed between stages in a pipelined microprocessor clocked by a single-phase clock signal. The structures of latches 200 and 500 allow implementation with relatively few transistors and result in low propagation delays in comparison to other latch structures. Since the input signal is electrically coupled through enabled transmission gates to the latch's output line for only a short duration over the clock period, race conditions may be eliminated. The capacitive loading on the clock driver of a system employing latch 200 may further be reduced by virtue of driving only a single inverter per latch. Furthermore, in one embodiment, the inverter coupled to the clock signal may be configured with a relatively high trip point to ensure that ground noise does not allow false triggering of the latch circuit. Adverse affects due to charge sharing from node A to node B are further prevented as a result of the switching arrangement of transmission gates 202 and 204.

Turning now to Figure 5, an alternate embodiment of a latch circuit 500 is shown wherein the latch 500 is enabled upon the falling edge of the clock signal CLK rather than the rising edge. It will be appreciated that in latch 500, inverter 214 may be configured with a relatively high trip point, thereby preventing noise on clock input line 216 from inadvertently triggering latch circuit 500.

Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.

Claims

WHAT IS CLAIMED IS:

1. A latch circuit comprising:

a data input node for receiving an input signal; a first transmission gate having a first terminal coupled to said data input node, a second terminal, and a control terminal; a second transmission gate having a first terminal, a second terminal, and a control terminal, wherein said first terminal of said second transmission gate is coupled to the second terminal of said first transmission gate, and wherein said control terminal of said second transmission gate is coupled to receive a clock signal; a keeper circuit coupled to the second terminal of the second transmission gate, wherein said keeper circuit is capable of maintaining a logic value at said second terminal of said second transmission gate; and a delay element coupled to said control terminal of said first transmission gate, wherein said delay element is capable of delaying said clock signal to thereby provide a delayed clock signal to said control terminal of said first transmission gate.

The latch circuit as recited in Claim 1 wherein said keeper circuit comprises:

a first inverter having an input terminal connected to the second terminal of said second transmission gate, and an output terminal; and a trickle inverter having an input terminal connected to the output terminal of the first inverter, and an output terminal connected to the input terminal of the keeper inverter.

The latch circuit as recited in Claim 1 wherein said delay element comprises:

a first inverter having an input terminal connected to receive said clock signal, and an output terminal; a second inverter having an input terminal connected to said output terminal of the first inverter, and an output terminal; and a third inverter having an input terminal connected to said output terminal of the second inverter, and an output terminal connected to said control terminal of said first transmission gate.

4. The latch circuit as recited in claim 1 further comprising a first inverter coupled in series with a second inverter, wherein an output line of said second inverter is coupled to an input line of said delay element whereby said clock signal propagates through said first and second inverters prior to propagating through said delay element.

5. The latch circuit as recited in claim 4 wherein an output line of said second inverter is coupled to said control terminal of said second transmission gate.

6. The latch circuit as recited in claim 5 wherein an output line of said first inverter is coupled to a second control terminal of said second transmission gate.

7. The latch circuit as recited in claim 1 further comprising an inverter having an output line coupled to an input line of said delay element whereby said clock signal propagates through said inverter prior to propagating through said delay element.

8. The latch circuit as recited in claim 7 wherein the output line of said inverter is coupled to said control terminal of said second transmission gate.

9. The latch circuit as recited in claim 1 further comprising a first inverter having an input line coupled to said second terminal of said second transmission gate.

10. The latch circuit as recited in claim 1 wherein said delay element includes a plurality of serially coupled inverters.

11. A latch circuit comprising: a data input node for receiving an input signal; a first transmission gate having a first terminal coupled to said data input node, a second terminal, and a control terminal; a second transmission gate having a first terminal, a second terminal, and a control terminal, wherein said first terminal of said second transmission gate is coupled to the second terminal of said first transmission gate, and said control terminal of said second transmission gate is coupled to receive a clock signal; a keeper circuit coupled to the second terminal of the second transmission gate, wherein said keeper circuit is capable of maintaining a logic value at said second terminal of said second transmission gate; a delay element coupled to said control terminal of said first transmission gate, wherein said delay element is capable of delaying said clock signal to thereby provide a delayed clock signal to said control terminal of said first transmission gate, and wherein said delay element includes a plurality of serially coupled inverters; a first inverter having an input terminal connected to the second terminal of said second transmission gate, and an output terminal; and a second inverter coupled in series with a third inverter, wherein an output line of said third inverter is coupled to an input line of said delay element whereby said clock signal propagates through said first and second inverters prior to propagating through said delay element.

12. The latch circuit as recited in claim 11 wherein an output line of said third inverter is coupled to said control terminal of said second transmission gate.

13. The latch circuit as recited in claim 12 wherein an output line of said second inverter is coupled to a second control terminal of said second transmission gate.

14. A latch circuit comprising: a data input node for receiving an input signal; a first transmission gate having a first terminal coupled to said data input node, a second terminal, and a control terminal; a second transmission gate having a first terminal, a second terminal, and a control terminal, wherein said first terminal of said second transmission gate is coupled to the second terminal of said first transmission gate; a keeper circuit coupled to the second terminal of the second transmission gate, wherein said keeper circuit is capable of maintaining a logic value at said second terminal of said second transmission gate; a first inverter having an input line for receiving a clock signal and an output line coupled to said control teπninal of said second transmission gate; a delay element having an output line coupled to said control terminal of said first transmission gate and an input line coupled to said output line of said first inverter, wherein said delay element is capable of delaying said clock signal to thereby provide a delayed clock signal to said control terminal of said first transmission gate.

15. A pipelined microprocessor comprising: a first combinational logic circuit forming a first pipeline stage within said microprocessor; a second combinational logic circuit forming a subsequent pipeline stage within said microprocessor; and a latch circuit coupled between an output line of said first combinational logic circuit and an input line of said second combinational logic circuit, said latch circuit including: a plurality of transmission gates serially couples between said first combinational logic circuit and said second combinational logic circuit, wherein a first of said plurality is controlled by a clock signal; and a delay element coupled to a second of said plurality of transmission gates, wherein said second of said plurality of transmission gates is controlled by a delayed version of said clock signal.

16. The pipelined microprocessor as recited in Claim 15 wherein the delay element comprises: a first inverter having an input terminal connected to receive said clock signal, and an output terminal; a second inverter having an input terminal connected to said output terminal of the first inverter, and an output terminal; and a third inverter having an input terminal connected to said output terminal of the second inverter, and an output terminal coupled to a control terminal of said second of said plurality of transmission gates.

17. The pipelined microprocessor as recited in claim 15 wherein said delay element includes a plurality of serially coupled inverters.

18. The pipelined microprocessor as recited in claim 15 further comprising an output inverter coupled between a first of said plurality of transmission gates and an output line of said latch circuit.

19. The pipelined microprocessor as recited in claim 18 further comprising a keeper circuit coupled to an input terminal of said output inverter, wherein said keeper circuit is capable of mamtaining a logic value at said input terminal of said output inverter.

20. The pipelined microprocessor as recited in claim 19 wherein said keeper circuit comprises: a first inverter having an input terminal connected to the input terminal of said output inverter; and a trickle inverter having an input terminal connected to an output terminal of said first inverter, and an output terminal connected to the input tenninal of said first inverter.

21. A pipelined microprocessor comprising: a first combinational logic circuit forming a first pipeline stage within said microprocessor; a second combinational logic circuit forming a subsequent pipeline stage within said microprocessor; and a latch circuit coupled between an output line of said first combinational logic circuit and an input line of said second combinational logic circuit, said latch circuit including: a data input node for receiving an input signal; a first transmission gate having a first terminal coupled to said data input node, a second terminal, and a control terminal; a second transmission gate is coupled to the second terminal of said first transmission gate, and said control terminal of said second transmission gate is coupled to receive a clock signal; a delay element coupled to said control terminal of said first transmission gate, wherein said delay element is capable of delaying said clock signal to thereby provide a delayed clock signal to said control terminal of said first transmission gate.

22. The pipelined microprocessor as recited in claim 21 wherein said delay element comprises: a first inverter having an input terminal connected to receive said clock signal, and an output terminal; a second inverter having an input terminal connected to said output terminal of the first inverter, and an output terminal; and a third inverter having an input terminal connected to said output terminal of the second inverter, and an output terminal connected to said control terminal of said first transmission gate.

23. The pipelined microprocessor as recited in claim 21 further comprising a first inverter having an input line coupled to said second terminal of said second transmission gate.

24. The pipelined microprocessor as recited in claim 21 wherein said delay element includes a plurality of serially coupled inverters.

25. A latch circuit comprising: a first transmission gate; a second transmission gate coupled to said first transmission gate; and a delay element coupled to said first transmission gate to thereby provide a delayed control signal to said first transmission gate.