CN114900176B - Three-point flip self-recovery latch based on heterogeneous C unit - Google Patents

Three-point flip self-recovery latch based on heterogeneous C unit Download PDF

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CN114900176B
CN114900176B CN202210510268.4A CN202210510268A CN114900176B CN 114900176 B CN114900176 B CN 114900176B CN 202210510268 A CN202210510268 A CN 202210510268A CN 114900176 B CN114900176 B CN 114900176B
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unit
error
avoidance
node
approximate
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CN114900176A (en
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黄正峰
宫周宇
李子帅
倪天明
詹文法
宋钛
鲁迎春
李桢旻
刘光柱
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Hefei University of Technology
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Hefei University of Technology
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits

Abstract

The invention discloses a three-point overturning self-recovery latch based on heterogeneous C units, which comprises a signal input module, a transmission module, a matrix storage module, an internal node module and a signal output module, wherein the signal input module is connected with the transmission module; the transmission module comprises a first transmission gate, a second transmission gate, a third transmission gate, a fourth transmission gate, a fifth transmission gate and a sixth transmission gate; the matrix storage module comprises a first error avoidance C unit, a first approximate C unit, a second error avoidance C unit, a second approximate C unit, a third error avoidance C unit, a third approximate C unit, a fourth error avoidance C unit, a fourth approximate C unit, a fifth error avoidance C unit, a fifth approximate C unit, a sixth error avoidance C unit and a sixth approximate C unit. The invention provides a radiation-resistant reinforced latch design which provides complete single-particle single-point, double-point and three-point overturning self-recovery capability, and simultaneously reduces the latch performance, area and power consumption expenditure caused by high-reliability design.

Description

Three-point flip self-recovery latch based on heterogeneous C unit
Technical Field
The invention relates to the technical field of nano integrated circuits, in particular to a three-point flip self-recovery latch based on heterogeneous C units.
Background
In severe radiation environments such as space, high energy particles seriously threaten the reliability of advanced integrated circuits. The single event effect caused by a single energetic particle has increasingly serious impact on advanced integrated circuits. Integrated circuits under nanotechnology are highly likely to cause the critical node level of their internal circuitry to flip after single-event bombardment, i.e., single-event flip. This can lead to circuit errors that can affect the proper operation of the overall system with serious consequences.
As the feature size of the integrated circuit is further reduced, the supply voltage and parasitic capacitance of the integrated circuit are further reduced, so that the level inversion on each node is more likely to occur; at the same time, the physical distance of the nodes is reduced, which leads to charge sharing, so that a single particle may cause logic value inversion of a plurality of nodes, including single particle double-point inversion and single particle three-point inversion, and even more, which provides new challenges for the design of the radiation-resistant reinforcement circuit. Therefore, development of a new tolerant multi-point flip circuit is imperative.
Since latches are an essential key element in large scale integrated circuits, researchers have proposed a range of single event upset resistant latch designs, but these designs currently suffer from the following problems:
1) Most single-particle single-point or double-point reinforcement designs, as described above, under advanced integrated circuit processes, the reliability of these designs has not been able to meet the requirements of the system;
2) Most of the blocking designs, while ensuring the correct output of the hardened latch, the internal nodes of the latch still remain soft errors from single event upset, and their reliability is not high enough in low speed applications due to leakage currents in the integrated circuit;
3) The three-point self-recovery latch can be realized at present, the cost is high while the reliability is improved, and the three main costs of delay, power consumption and area are large and good compromise cannot be obtained.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems in the related art to some extent. Therefore, an object of the present invention is to provide a three-point flip self-recovery latch based on heterogeneous C cells, which provides complete single-event single-point, double-point, three-point flip self-recovery capability, and reduces latch performance, area, and power consumption overhead caused by high reliability design.
The three-point overturning self-recovery latch based on the heterogeneous C unit comprises a signal input module, a transmission module, a matrix storage module, an internal node module and a signal output module;
The transmission module comprises a first transmission gate, a second transmission gate, a third transmission gate, a fourth transmission gate, a fifth transmission gate and a sixth transmission gate;
the matrix storage module comprises a first error avoidance C unit, a first approximate C unit, a second error avoidance C unit, a second approximate C unit, a third error avoidance C unit, a third approximate C unit, a fourth error avoidance C unit, a fourth approximate C unit, a fifth error avoidance C unit, a fifth approximate C unit, a sixth error avoidance C unit and a sixth approximate C unit;
the signal input module comprises a data input node D, a first clock input node CK and a second clock input node NCK;
the internal node module comprises an internal node I1, an internal node I2, an internal node I3, an internal node I4, an internal node I5, an internal node I6, an internal node I7, an internal node I8, an internal node I9, an internal node I10, an internal node I11 and an internal node I12;
the signal output module comprises a data output node Q;
the data input node D is connected with signal input nodes of the first transmission gate, the second transmission gate, the third transmission gate, the fourth transmission gate, the fifth transmission gate and the sixth transmission gate;
the first clock input node CK is respectively connected with the N-type clock signal input nodes of the first transmission gate, the second transmission gate, the third transmission gate, the fourth transmission gate, the fifth transmission gate and the sixth transmission gate; the second approximate C unit, the fourth approximate C unit and the sixth approximate C unit are connected with the P-type signal input node P 1 The method comprises the steps of carrying out a first treatment on the surface of the The P-type signal input nodes P of the second error-avoidance C unit, the fourth error-avoidance C unit and the sixth error-avoidance C unit 1 Connecting;
the second clock input node NCK is respectively connected with the P-type clock signal input nodes of the first transmission gate, the third transmission gate and the fifth transmission gate; the second approximate C unit, the fourth approximate C unit and the sixth approximate C unit are connected with the N-type signal input node N 1 The method comprises the steps of carrying out a first treatment on the surface of the N-type signal input nodes N of the second error-avoidance C unit, the fourth error-avoidance C unit and the sixth error-avoidance C unit 2 Connecting;
the internal node I1 is respectively connected with the P-type signal output node O of the first error avoidance C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of said second approximate C cell 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of the second error avoidance C unit 1 Connecting;
the internal node I2 is respectively connected with the complementary signal output node O of the second approximate C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the P-type signal input node P of the third error avoidance C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the P-type signal input node P of the third approximate C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the N-type signal input node N of the second error avoidance C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the The signal output node of the third transmission gate is connected;
the internal node I3 is respectively connected with the complementary signal output node O of the first approximate C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the N-type signal input node N of the second error avoidance C unit 3 The method comprises the steps of carrying out a first treatment on the surface of the N-type signal input node N of the fourth C-like cell 2 The method comprises the steps of carrying out a first treatment on the surface of the P-type signal input node P of the third error avoidance C unit 2 Connecting;
the internal node I4 is respectively connected with the N-type signal output node O of the second error avoidance C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of the third approximate C cell 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of the fifth error avoidance C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the The signal output node of the fourth transmission gate is connected;
the internal node I5 is respectively connected with the P-type signal output node O of the third error avoidance C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of the fourth C-like cell 1 The method comprises the steps of carrying out a first treatment on the surface of the Said firstComplementary signal input node C of four error-avoidance C units 1 Connecting;
the internal node I6 is respectively connected with the complementary signal output node O of the fourth approximate C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the P-type signal input node P of the fifth error avoidance C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the P-type signal input node P of the fifth approximate C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the N-type signal input node N of the fourth error avoidance C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the The signal output node of the fifth transmission gate is connected;
the internal node I7 is respectively connected with the complementary signal output node O of the third approximate C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the N-type signal input node N of the fourth error avoidance C unit 3 The method comprises the steps of carrying out a first treatment on the surface of the N-type signal input node N of the sixth approximate C unit 2 The method comprises the steps of carrying out a first treatment on the surface of the P-type signal input node P of the fifth error avoidance C unit 2 Connecting;
the internal node I8 is respectively connected with the N-type signal output node O of the fourth error avoidance C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of the fifth approximate C cell 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of the first error avoidance C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the The signal output node of the sixth transmission gate is connected;
the internal node I9 is respectively connected with the P-type signal output node O of the fifth error avoidance C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of the sixth approximate C cell 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of the sixth error avoidance C unit 1 Connecting;
the internal node I10 is respectively connected with the complementary signal output node O of the sixth approximate C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the P-type signal input node P of the first error avoidance C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the P-type signal input node P of the first approximate C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the N-type signal input node N of the sixth error avoidance C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the The signal output node of the first transmission gate is connected;
the internal node I11 is respectively connected with the complementary signal output node O of the fifth approximate C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the N-type signal input node N of the sixth error avoidance C unit 3 The method comprises the steps of carrying out a first treatment on the surface of the N-type signal input node N of the second approximate C unit 2 The method comprises the steps of carrying out a first treatment on the surface of the The first error avoidanceP-type signal input node P of C unit 2 Connecting;
the internal node I12 is respectively connected with the N-type signal output node O of the sixth error avoidance C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of the first approximate C cell 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of the third error avoidance C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the The signal output node of the second transmission gate is connected;
the data output node Q is connected with the internal node I6.
Preferably, the first transmission gate includes a first PMOS and a first NMOS, and sources of the first PMOS and the first NMOS are connected together to serve as a signal input node of the first transmission gate;
the drains of the first PMOS and the first NMOS are connected together to serve as a signal output node of a first transmission gate;
the first PMOS gate is connected with the second clock input node NCK through a P-type clock signal input node of the first transmission gate;
the first NMOS gate is an N-type clock signal input node of a first transmission gate and is connected with the first clock input node CK;
the third transmission gate and the fifth transmission gate have the same structure as the first transmission gate.
Preferably, the second transmission gate includes a second NMOS, and a source of the second NMOS is a signal input node of the second transmission gate; the drain electrode of the second NMOS is a signal output node of the second transmission gate; the second NMOS gate is connected with the first clock input node CK by an N-type clock signal input node of the second transmission gate;
The fourth transmission gate and the sixth transmission gate have the same structure as the second transmission gate.
Preferably, the first approximate C unit comprises a second PMOS, a third PMOS and a third NMOS, and the gate connection of the second PMOS and the third PMOS is used as a complementary input node C of the first approximate C unit 1 ；
The gate of the third PMOS is the P-type input node P of the first approximate C-cell 1 ；
The drain of the third PMOS and the drain of the third NMOS serve as the complementary output nodes O of the first approximate C cell 1 ；
The drain electrode of the second PMOS is connected with the source electrode of the third PMOS, the source electrodes of the second PMOS and the substrates of the second PMOS and the third PMOS are externally connected with a power supply VDD, and the source electrode of the third NMOS and the substrate of the third NMOS are grounded to GND;
the third approximate C unit and the fifth approximate C unit have the same structure as the first approximate C unit.
Preferably, the first error-avoidance C unit comprises a fourth PMOS, a fifth PMOS, a sixth PMOS and a fourth NMOS, wherein the grid of the fourth PMOS is connected with the grid of the fourth NMOS to serve as a complementary input node C of the first error-avoidance C unit 1 ；
The gate of the fifth PMOS is the P-type input node P of the first error-avoidance C unit 1 ；
The gate of the sixth PMOS is the P-type input node P of the first error-avoidance C unit 2 ；
The drain of the fifth PMOS is connected with the source of the sixth PMOS as the P-type output node O of the first error-avoidance C unit 1 ；
The drain electrode of the fourth PMOS is connected with the source electrode of the fifth PMOS, the drain electrode of the sixth PMOS is connected with the drain electrode of the fourth NMOS, the source electrode of the fourth PMOS and the substrates of the fourth PMOS, the fifth PMOS and the sixth PMOS are externally connected with a power supply VDD, and the source electrode of the fourth NMOS and the substrate of the fourth NMOS are grounded GND;
the third error-avoidance C unit and the fifth error-avoidance C unit have the same structure as the first error-avoidance C unit.
Preferably, the second approximate C unit comprises a seventh PMOS, an eighth PMOS, a fifth NMOS, a sixth NMOS, and a seventh NMOS, wherein the gate of the seventh PMOS and the gate of the seventh NMOS tube are connected as the complementary input node C of the second approximate C unit 1 ；
The gate of the eighth PMOS is the P-type input node of the second approximate C cellP 1 ；
The gate of the fifth NMOS is the N-type input node N of the second approximate C cell 1 ；
The grid of the sixth NMOS is the N-type input node N of the second approximate C unit 2 ；
The drain of the eighth PMOS is connected with the drain of the fifth NMOS as the complementary output node O of the second approximate C cell 1 ；
The drain electrode of the seventh PMOS is connected with the source electrode of the eighth PMOS, the source electrode of the fifth NMOS is connected with the drain electrode of the sixth NMOS, the source electrode of the sixth NMOS is connected with the drain electrode of the seventh NMOS, the source electrodes of the seventh PMOS and the substrates of the seventh PMOS and the eighth PMOS are externally connected with a power supply VDD, and the source electrodes of the seventh NMOS and the substrates of the fifth NMOS, the sixth NMOS and the seventh NMOS are all connected with the ground GND;
the fourth and sixth approximate C-cells are identical in structure to the second approximate C-cell.
Preferably, the second error-avoidance C unit includes a ninth PMOS, a tenth PMOS, an eighth NMOS, a ninth NMOS, a tenth NMOS, and an eleventh NMOS, wherein the gate of the ninth PMOS is connected with the gate of the eleventh NMOS as the complementary input node C of the second error-avoidance C unit 1 ；
The tenth PMOS gate is the P-type input node P of the second error-avoidance C unit 1 ；
The gate of the eighth NMOS is the N-type input node N of the second error-avoidance C unit 1 ；
The gate of the ninth NMOS is the N-type input node N of the second error-avoidance C unit 2 ；
The gate of the tenth NMOS is the N-type input node N of the second error-avoidance C unit 3 ；
The source of the eighth NMOS is connected with the drain of the ninth NMOS as the N-type output node O of the second error-avoidance C unit 1 ；
The drain electrode of the ninth PMOS is connected with the source electrode of the tenth PMOS, the drain electrode of the tenth PMOS is connected with the drain electrode of the eighth NMOS, the source electrode of the ninth NMOS is connected with the drain electrode of the tenth NMOS, the source electrode of the tenth NMOS is connected with the drain electrode of the eleventh NMOS, the source electrodes of the ninth PMOS and the substrates of the ninth PMOS and the tenth PMOS are externally connected with a power supply VDD, and the source electrode of the eleventh NMOS is connected with the substrates of the eighth NMOS, the ninth NMOS, the tenth NMOS and the eleventh NMOS to be connected with a ground GND;
the fourth error-avoidance C unit and the sixth error-avoidance C unit have the same structure as the second error-avoidance C unit.
The beneficial effects of the invention are as follows:
1) The latch design has high reliability, and can be completely self-recovered from level inversion of any three internal nodes;
2) Due to the special data output end design of the error avoidance C unit, the structure can reduce the possibility of level inversion on half nodes;
3) The area cost is low, the structure uses approximate C units, and the transistor number of the approximate C units is smaller than that of the traditional C units;
4) The invention uses the fast path and clock control technique, the latch has only one transmission gate from the signal input end to the signal output end, and can turn off half of internal transistors under the condition of no need, thus saving the power consumption and the delay cost.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention. In the drawings:
FIG. 1 is a schematic diagram of a three-point flip-flop self-restore latch based on heterogeneous C cells according to the present invention;
FIG. 2 is a schematic circuit diagram of a 6-group transmission gate according to the present invention;
FIG. 3 is a schematic circuit diagram of the first, third and fifth C-cell of FIG. 1 according to the present invention;
FIG. 4 is a schematic circuit diagram of the first, third and fifth units according to the present invention;
FIG. 5 is a schematic circuit diagram of the second, fourth and sixth C-cell of FIG. 1 according to the present invention;
FIG. 6 is a schematic circuit diagram of the second, fourth and sixth error-avoidance units of FIG. 1 according to the present invention;
FIG. 7 is a diagram of waveforms for implementing three-point flip self-recovery in accordance with the present invention.
In the figure: 101-first pass gate, 102-second pass gate, 103-third pass gate, 104-fourth pass gate, 105-fifth pass gate, 106-sixth pass gate, 107-first error-avoidance C unit, 108-first approximate C unit, 109-third error-avoidance C unit, 110-third approximate C unit, 111-fifth error-avoidance C unit, 112-fifth approximate C unit, 113-second approximate C unit, 114-second error-avoidance C unit, 115-fourth approximate C unit, 116-fourth error-avoidance C unit, 117-sixth approximate C unit, 118-sixth error-avoidance C unit, 201-first PMOS, 202-first NMOS, 207-second NMOS, 301-second PMOS, 302-third PMOS, 303-third NMOS, 401-fourth PMOS, 402-fifth PMOS, 403-sixth PMOS, 404-fourth PMOS, 501-seventh NMOS, 502-eighth PMOS, 503-fifth NMOS, 504-seventh NMOS, 505-seventh PMOS, 602-ninth PMOS, 601-ninth NMOS, 601-ninth PMOS, and ninth NMOS.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments.
Referring to fig. 1, a three-point flip self-recovery latch based on heterogeneous C units includes a signal input module, a transmission module, a matrix storage module, an internal node module, and a signal output module;
the transmission module comprises a first transmission gate 101, a second transmission gate 102, a third transmission gate 103, a fourth transmission gate 104, a fifth transmission gate 105 and a sixth transmission gate 106;
the matrix storage module includes a first error-avoidance C unit 107, a first approximate C unit 108, a second error-avoidance C unit 114, a second approximate C unit 113, a third error-avoidance C unit 109, a third approximate C unit 110, a fourth error-avoidance C unit 116, a fourth approximate C unit 115, a fifth error-avoidance C unit 111, a fifth approximate C unit 112, a sixth error-avoidance C unit 118, and a sixth approximate C unit 117;
the signal input module comprises a data input node D, a first clock input node CK and a second clock input node NCK;
the internal node module comprises an internal node I1, an internal node I2, an internal node I3, an internal node I4, an internal node I5, an internal node I6, an internal node I7, an internal node I8, an internal node I9, an internal node I10, an internal node I11 and an internal node I12;
The signal output module comprises a data output node Q;
the data input node D is connected to signal input nodes of the first transmission gate 101, the second transmission gate 102, the third transmission gate 103, the fourth transmission gate 104, the fifth transmission gate 105, and the sixth transmission gate 106;
the first clock input node CK is respectively connected with the N-type clock signal input nodes of the first transmission gate 101, the second transmission gate 102, the third transmission gate 103, the fourth transmission gate 104, the fifth transmission gate 105 and the sixth transmission gate 106; the P-type signal input nodes P1 of the second approximate C unit 113, the fourth approximate C unit 115, and the sixth approximate C unit 117; the second error-avoidance C unit 114, the fourth error-avoidance C unit 116, and the sixth error-avoidance C unit 118 are connected to the P-type signal input node P1;
the second clock input node NCK is respectively connected with the P-type clock signal input nodes of the first transmission gate 101, the third transmission gate 103 and the fifth transmission gate 105; n-type signal input nodes N of the second approximate C unit 113, the fourth approximate C unit 115 and the sixth approximate C unit 117 1 The method comprises the steps of carrying out a first treatment on the surface of the N-type signal input nodes N of the second error-avoidance C unit 114, the fourth error-avoidance C unit 116 and the sixth error-avoidance C unit 118 2 Connecting;
the internal node I1 is respectively connected with the P-type signal output node O of the first error-avoidance C unit 107 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of second approximation C cell 113 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of second error avoidance C unit 114 1 Connecting;
the internal node I2 is respectively connected with the complementary signal output node O of the second approximate C unit 113 1 The method comprises the steps of carrying out a first treatment on the surface of the P-type signal input node P of third error-avoidance C unit 109 1 The method comprises the steps of carrying out a first treatment on the surface of the P-type signal input node P of third approximate C cell 110 1 The method comprises the steps of carrying out a first treatment on the surface of the N-type signal input node N of second error-avoidance C unit 114 1 The method comprises the steps of carrying out a first treatment on the surface of the The signal output node of the third transmission gate 103 is connected;
the internal node I3 is respectively connected with the complementary signal output node O of the first approximate C unit 108 1 The method comprises the steps of carrying out a first treatment on the surface of the N-type signal input node N of second error-avoidance C unit 114 3 The method comprises the steps of carrying out a first treatment on the surface of the N-type signal input node N of fourth C-like cell 115 2 The method comprises the steps of carrying out a first treatment on the surface of the P-type signal input node P of third error-avoidance C unit 109 2 Connecting;
the internal node I4 is respectively connected with the N-type signal output node O of the second error-avoidance C unit 114 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of third approximation C cell 110 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of fifth error avoidance C unit 111 1 The method comprises the steps of carrying out a first treatment on the surface of the The signal output node of the fourth transmission gate 104 is connected;
the internal node I5 is respectively connected with the P-type signal output node O of the third error-avoidance C unit 109 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of fourth similar-C cell 115 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of 116 of fourth error avoidance C unit 1 Connecting;
the internal node I6 is respectively coupled to the complementary signal output node O of the fourth similar C-cell 115 1 The method comprises the steps of carrying out a first treatment on the surface of the P-type signal input node P of fifth error-avoidance C unit 111 1 The method comprises the steps of carrying out a first treatment on the surface of the P-type signal input node P of fifth approximate C cell 112 1 The method comprises the steps of carrying out a first treatment on the surface of the N-type signal input node N of fourth error-avoidance C unit 116 1 The method comprises the steps of carrying out a first treatment on the surface of the The signal output node of the fifth transmission gate 105 is connected;
the internal node I7 is respectively connected with the complementary signal output node O of the third approximate C unit 110 1 The method comprises the steps of carrying out a first treatment on the surface of the N-type signal input node N of fourth error-avoidance C unit 116 3 The method comprises the steps of carrying out a first treatment on the surface of the N-type signal input node N of sixth approximate C unit 117 2 The method comprises the steps of carrying out a first treatment on the surface of the P-type signal input node P of fifth error-avoidance C unit 111 2 Connecting;
internal nodes I8 respectivelyN-type signal output node O with fourth error avoidance C unit 116 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of fifth approximation C cell 112 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of first error avoidance C unit 107 1 The method comprises the steps of carrying out a first treatment on the surface of the The signal output node of the sixth transmission gate 106 is connected;
the internal node I9 is respectively connected with the P-type signal output node O of the fifth error-avoidance C unit 111 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of sixth approximate C cell 117 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of 118 of sixth error avoidance C unit 1 Connecting;
the internal node I10 is respectively connected with the complementary signal output node O of the sixth approximate C unit 117 1 The method comprises the steps of carrying out a first treatment on the surface of the P-type signal input node P of first error avoidance C unit 107 1 The method comprises the steps of carrying out a first treatment on the surface of the P-type signal input node P of first approximate C-cell 108 1 The method comprises the steps of carrying out a first treatment on the surface of the N-type signal input node N of sixth error avoidance C unit 118 1 The method comprises the steps of carrying out a first treatment on the surface of the The signal output node of the first transmission gate 101 is connected;
the internal node I11 is respectively connected with the complementary signal output node O of the fifth approximate C unit 112 1 The method comprises the steps of carrying out a first treatment on the surface of the N-type signal input node N of sixth error avoidance C unit 118 3 The method comprises the steps of carrying out a first treatment on the surface of the N-type signal input node N of second approximate C cell 113 2 The method comprises the steps of carrying out a first treatment on the surface of the P-type signal input node P of first error avoidance C unit 107 2 Connecting;
the internal node I12 and the N-type signal output node O of the sixth error-avoidance C unit 118 respectively 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of first approximation C cell 108 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of third error-avoidance C unit 109 1 The method comprises the steps of carrying out a first treatment on the surface of the The signal output node of the second transmission gate 102 is connected;
the data output node Q is connected to the internal node I6.
Referring to fig. 2, the first transmission gate 101 includes a first PMOS201 and a first NMOS202, and sources of the first PMOS201 and the first NMOS202 are connected together as a signal input node of the first transmission gate 101;
drains of the first PMOS201 and the first NMOS202 are connected together as a signal output node of the first transmission gate 101;
the first PMOS201 gate is connected with the second clock input node NCK by the P-type clock signal input node of the first transmission gate 101;
The first NMOS202 gate is connected to the first clock input node CK as the N-type clock input node of the first transmission gate 101;
the third transfer gate 103 and the fifth transfer gate 105 have the same structure as the first transfer gate 101.
The second transmission gate 102 includes a second NMOS207, and a source of the second NMOS207 serves as a signal input node of the second transmission gate 102; the drain of the second NMOS207 serves as a signal output node of the second transmission gate 102; the gate of the second NMOS207 is connected to the first clock input node CK as an N-type clock signal input node of the second transmission gate 102;
the fourth transmission gate 104 and the sixth transmission gate 106 have the same structure as the second transmission gate 102.
Referring to fig. 3, the first approximate C cell 108 includes a second PMOS301, a third PMOS302, and a third NMOS303, the gate connections of the second PMOS301 and the third PMOS302 being the complementary input node C of the first approximate C cell 108 1 ；
The gate of the third PMOS302 is the P-type input node P of the first approximate C-cell 108 1 ；
The drain of the third PMOS302 and the drain of the third NMOS303 serve as the complementary output nodes O of the first approximately C cell 108 1 ；
The drain electrode of the second PMOS301 is connected with the source electrode of the third PMOS302, the source electrodes of the second PMOS301 and the substrates of the second PMOS301 and the third PMOS302 are externally connected with a power supply VDD, and the source electrode of the third NMOS303 and the substrate of the third NMOS303 are grounded GND;
The third and fifth approximate C cells 110, 112 are identical in structure to the first approximate C cell 108.
Referring to fig. 4, the first error-avoidance C unit 107 includes a fourth PMOS401, a fifth PMOS402, a sixth PMOS403, and a fourth NMOS404, where a gate of the fourth PMOS401 and a gate of the fourth NMOS404 are connected as a complementary input node C of the first error-avoidance C unit 107 1 ；
The gate of the fifth PMOS402 is the P-type input node P of the first error-avoidance C unit 107 1 ；
The gate of the sixth PMOS403 is the P-type input node P of the first error-avoidance C unit 107 2 ；
The drain of the fifth PMOS402 is connected to the source of the sixth PMOS403 as the P-type output node O of the first error-avoidance C-unit 107 1 ；
The drain electrode of the fourth PMOS401 is connected with the source electrode of the fifth PMOS402, the drain electrode of the sixth PMOS403 is connected with the drain electrode of the fourth NMOS404, the source electrode of the fourth PMOS401 and the substrates of the fourth PMOS401, the fifth PMOS402 and the sixth PMOS403 are externally connected with a power supply VDD, and the source electrode of the fourth NMOS404 and the substrate of the fourth NMOS404 are grounded GND;
the third error-avoidance C unit 109 and the fifth error-avoidance C unit 111 have the same structure as the first error-avoidance C unit 107.
Referring to fig. 5, the second approximate C cell 113 includes a seventh PMOS501, an eighth PMOS502, a fifth NMOS503, a sixth NMOS504, a seventh NMOS505, the gate of the seventh PMOS501 and the gate of the seventh NMOS transistor 505 being connected as the complementary input node C of the second approximate C cell 113 1 ；
The gate of the eighth PMOS502 is the P-type input node P of the second approximate C-cell 113 1 ；
The gate of the fifth NMOS503 is the N-type input node N of the second approximately C cell 113 1 ；
The gate of the sixth NMOS504 is the N-type input node N of the second approximately C-cell 113 2 ；
The drain of the eighth PMOS502 is connected to the drain of the fifth NMOS503 as the complementary output node O of the second near C cell 113 1 ；
The drain electrode of the seventh PMOS501 is connected with the source electrode of the eighth PMOS502, the source electrode of the fifth NMOS503 is connected with the drain electrode of the sixth NMOS504, the source electrode of the sixth NMOS504 is connected with the drain electrode of the seventh NMOS505, the source electrode of the seventh PMOS501 is externally connected with a power supply VDD with the substrates of the seventh PMOS501 and the eighth PMOS502, and the source electrode of the seventh NMOS tube 505 is connected with the ground GND with the substrates of the fifth NMOS503, the sixth NMOS504 and the seventh NMOS 505;
the fourth and sixth approximate C units 115 and 117 have the same structure as the second approximate C unit 113.
Referring to fig. 6, the second error-avoidance C unit 114 includes a ninth PMOS601, a tenth PMOS602, an eighth NMOS603, a ninth NMOS604, a tenth NMOS605, eleventh NMOS606, and the gate of ninth PMOS601 is connected to the gate of eleventh NMOS606 as complementary input node C of second error-avoidance C cell 114 1 ；
The gate of the tenth PMOS602 is the P-type input node P of the second error-avoidance C unit 114 1 ；
The gate of the eighth NMOS603 is the N-type input node N of the second error-avoidance C unit 114 1 ；
The gate of the ninth NMOS604 is the N-type input node N of the second error-avoidance C-cell 114 2 ；
The gate of the tenth NMOS605 is the N-input node N of the second error-avoidance C unit 114 3 ；
The source of the eighth NMOS603 is connected to the drain of the ninth NMOS604 as the N-type output node O of the second error-avoidance C-cell 114 1 ；
The drain electrode of the ninth PMOS601 is connected with the source electrode of the tenth PMOS602, the drain electrode of the tenth PMOS602 is connected with the drain electrode of the eighth NMOS603, the source electrode of the ninth NMOS604 is connected with the drain electrode of the tenth NMOS605, the source electrode of the tenth NMOS605 is connected with the drain electrode of the eleventh NMOS606, the source electrode of the ninth PMOS601 is externally connected with a power supply VDD with the substrates of the ninth PMOS601 and the tenth PMOS602, and the source electrode of the eleventh NMOS606 is connected with the ground GND with the substrates of the eighth NMOS603, the ninth NMOS604, the tenth NMOS605 and the eleventh NMOS 606;
the fourth error-avoidance C unit 116, the sixth error-avoidance C unit 118 and the second error-avoidance C unit 114 have the same structure.
The working principle and fault tolerance principle of the present invention are further described below.
Truth tables for the first approximation C cell 108, the third approximation C cell 110, and the fifth approximation C cell 112 are shown in table 1 below:
TABLE 1
Complementary signal input node C 1 P-type signal input node P 1 Complementary signal output node O 1
0 0 1
0 1 Z
1 0 0
1 1 0
Truth tables of the first error-avoidance C unit 107, the third error-avoidance C unit 109, and the fifth error-avoidance C unit 111 are shown in table 2 below:
TABLE 2
When the first clock signal ck= "0", the second clock signal nck= "1", the truth tables of the second approximate C unit 113, the fourth approximate C unit 115, and the sixth approximate C unit 117 are shown in the following table 3:
TABLE 3 Table 3
Complementary signal input node C 1 N-type signal input node N 2 Complementary signal output node O 1
0 0 1
0 1 1
1 0 Z
1 1 0
When the first clock signal ck= "0", the second clock signal nck= "1", the truth tables of the second error-avoidance C unit 114, the fourth error-avoidance C unit 116, and the sixth error-avoidance C unit 118 are shown in table 4 below:
TABLE 4 Table 4
Next, the working principle of the present invention when it is not affected by the single event effect is analyzed in detail
When the first clock signal ck= "1" and the second clock signal nck= "0", the latch operates in the transparent period, the first transmission gate 101, the second transmission gate 102, the third transmission gate 103, the fourth transmission gate 104, the fifth transmission gate 105 and the sixth transmission gate 106 are turned on, the input signal writing nodes I2, I4, I6, I8, I10 and I12 are directly driven to the correct output value by the signal output terminal Q of the latch through the fifth transmission gate 105; the second error-avoidance C unit 114, the second approximate C unit 113, the fourth error-avoidance C unit 116, the fourth approximate C unit 115, the sixth error-avoidance C unit 118, the sixth approximate C unit 117 are closed, and the feedback loop is cut off; i2, I4, I6, I8, I10, I12 drive I1, I3, I5, I7, I9, I11 to the correct logic value through first error-avoidance C-unit 107, first approximation C-unit 108, third error-avoidance C-unit 1109, third approximation C-unit 110, fifth error-avoidance C-unit 111, fifth approximation C-unit 112. All internal nodes complete writing, waiting for the arrival of a hold period.
When the first clock signal ck= "0" and the second clock signal nck= "1", the latch operates in the hold period, the first transmission gate 101, the second transmission gate 102, the third transmission gate 103, the fourth transmission gate 104, the fifth transmission gate 105, and the sixth transmission gate 106 are closed, preventing new data from being written into the latch; the second error-avoidance C-cell 114, the second approximate C-cell 113, the fourth error-avoidance C-cell 116, the fourth approximate C-cell 115, the sixth error-avoidance C-cell 118, the sixth approximate C-cell 117 are opened, all twelve cells form a feedback loop, and the correct logic value is saved; the signal output node Q of the latch is driven to the correct value by the fourth similar C-cell 115. Waiting for the arrival of the next clock cycle.
Next, the three-point turnover self-recovery principle of the invention when the operation of the invention is influenced by the single event effect during the hold period is analyzed in detail
As can be seen from table 1, for the first, third and fifth approximate C units 108, 110 and 112, their output nodes are flipped when their two signal input nodes are flipped at the same time. Furthermore, when their output nodes correctly output a logical value "1", only their complementary signal is input to node C 1 A "0" to "1" flip occurs and their output nodes will flip.
As can be seen from table 3, for the second approximate C cell 113, the fourth approximate C cell 115, and the sixth approximate C cell 117. When their two signal input nodes are flipped at the same time, their output nodes will flip. Furthermore, when their output nodes correctly output a logical value "0", so long as their complementary signal is input to node C 1 A "1" to "0" flip occurs and their output nodes will flip.
As can be seen from table 2, for the first error-avoidance C unit 107, the third error-avoidance C unit 109, and the fifth error-avoidance C unit 111. When their output nodes correctly output a logical value of "0", as long as their complementary signal is input to node C 1 And P-type signal input node P 1 A "1" to "0" flip occurs and their output nodes will flip. In addition, when their output nodes correctly output a logical value of "1", their complementary signal is input to node C 1 The flip from 0 to 1 occurs, and the P-type signal is input to the node P 2 A "1" to "0" flip occurs and their output nodes will also flip.
As can be seen from table 4, for the second error-avoidance C unit 114, the fourth error-avoidance C unit 116, and the sixth error-avoidance C unit 118. When their output nodes correctly output a logical value of "0", as long as their complementary signal is input to node C 1 The flip from 1 to 0 occurs, and the N-type signal is input to node N 1 The output nodes where "0" to "1" flip occur will flip. In addition, when their output nodes correctly output a logical value of "1", the complementary signal input node C 1 And N-type signal input node N 3 A "0" to "1" flip occurs and their output nodes will also flip.
According to the circuit structure shown in fig. 4, the signal output node (P-type signal output node O 1 ) Is connected to the drain of the fifth PMOS402 and the source of the sixth PMOS 403. It can be seen that their signal output nodes are driven by PMOS only, and two PMOS transistors can completely isolate the signal output nodes from the n+ region, thus allowing only the output nodes to collect positive charges. So that their signal output nodes can only be generated when impacted by high-energy particlesAnd the device is overturned, so that the situation of occurrence of a soft error is avoided.
The third error-avoidance C unit 109, the fifth error-avoidance C unit 111, and the first error-avoidance C unit 107 have the same structure, so their signal output nodes (P-type signal output node O 1 ) Only positive flip can be generated when impacted by high-energy particles
According to the circuit structures shown in fig. 1 and 6, the signal output node (N-type signal output node O 1 ) A source connected to the eighth NMOS603 and a drain of the ninth NMOS604, and a signal output node (drain of NMOS) of the fourth transmission gate 104. It can be seen that their signal output nodes are driven by NMOS only, and that two NMOS transistors can completely isolate the signal output nodes from the p+ region, allowing only the output nodes to collect negative charge. So that their signal output nodes can only be turned negative when impacted by energetic particles, thereby avoiding a soft error occurrence.
The fourth error-avoidance C unit 116, the sixth error-avoidance C unit 118, and the second error-avoidance C unit 114 have the same structure, so their signal output nodes (N-type signal output node O 1 ) Only negative flip can be generated when impacted by high energy particles
Because of the above-described characteristics of the four C units used in the present invention, the manner in which the units are interconnected is well-defined in FIG. 1. The I1, I5, I9, I4, I8 and I12 nodes can avoid a soft error flip possibility, and the avoided situation can not appear on the I1, I5, I9, I4, I8 and I12 nodes due to soft error propagation.
When the logic value stored by the latch is "0", the nodes I1, I5, I9, I4, I8 and I12 will not have soft errors due to the influence of single particles. The three initial flip nodes caused by the single event will only appear in the nodes I3, I7, I2, I6, I10, I11, and according to the truth tables shown in tables 1, 2, 3, and 4, the soft error will not propagate, and the soft error on the nodes I3, I7, I2, I6, I10, and I11 will be restored to the correct logic value after the single event effect is finished.
When the logic value stored in the latch is 1, three single particles resultThe roll-over node will have soft errors in all twelve nodes, and it will be understood from the truth tables shown in tables 1, 2, 3, and 4 that soft errors will propagate from three initial roll-over nodes to other nodes, and thus for C 1 3 2 Class discussion of the 220 initial node groups, class as table 5:
TABLE 5
Case of the case Ⅰ Ⅱ Ⅲ Ⅳ
Classification I(2n):3,I(2n-1):0 I(2n):0,I(2n-1):3 I(2n):2,I(2n-1):1 I(2n):1,I(2n-1):2
Quantity of 20 20 90 90
The three initial rollover nodes are divided into four cases according to the distribution of the three initial rollover nodes in twelve nodes, wherein 'I (2 n): m, I (2 n-1): n' represents that m initial rollover nodes appear in six nodes of I (2 n), and n initial rollover nodes appear in six nodes of I (2 n-1), wherein n=1 to 6. Because the circuit structure has symmetry, the soft error transmission and self-recovery principles of the cases I and II are identical, and the soft error transmission and self-recovery principles of the cases III and IV are identical. So that case I and case III can be selected for further analysis.
For case I, looking at the circuit structure and truth table, it can be found that if two of the three initial flipped nodes of the six nodes I (2 n) are consecutive in location in the circuit topology (e.g., I2 and I4), then a soft error is generated in one of the six nodes I (2 n-1) (e.g., I7). Case I can thus be further divided into three categories based on the relative positions of the three initial roll-over nodes in the six nodes I (2 n), as in table 6:
TABLE 6
Similarly, case III is further divided into two categories based on the relative positions of the two initial roll-over nodes in the six nodes of I (2 n), as shown in Table 7:
TABLE 7
Case of the case D E
Classification Both initial flip nodes are discontinuous Two initial roll-over nodes are continuous
Results Soft errors do not propagate Soft error occurrence propagation
Quantity of 54 36
For case III: E, since two initial flipped nodes of the six nodes of I (2 n) are consecutive, which results in a soft error at one node IX of the six nodes of I (2 n-1), but in case III there is already one initial flipped node IY of the six nodes of I (2 n-1), so if IX is consecutive with IY they result in a further propagation of the soft error, case III: E can be further divided into three cases, as in Table 8:
TABLE 8
Case of the case a b c
Classification IX and IY are the same node IX and IY discontinuity IX and IY are continuous
Results Soft error propagation to a node Soft error propagation to a node Soft error propagation to two nodes
Quantity of 6 18 12
In tables 5, 6, 7, 8, there are collectively covered [ (2+12+6) +20] + { [54+ (6+18+12) ]+90} = 220 node group possibilities.
Next, the soft error self-recovery principle of worst case I: C in case I will be described in detail, assuming that the initial roll-over node group is { I10, I12, I2}. Depending on the circuit configuration and truth table, they will cause the output nodes I3, I5 of the first C-cell 108, the third error-avoidance C-cell 109 to flip, and I3, I5 will cause the output node I6 of the fourth C-cell 115 to flip, ending with soft error propagation. After the single event effect is over, the second approximate C cell 113, the sixth approximate C cell 117, and the sixth error-avoidance C cell 118, which still maintain the driving capability, will restore the nodes I2, I10, I12; the first approximation C unit 108 then recovers node I3; then, the third error-avoidance C unit 109 restores the correct driving capability, restoring the node I5; finally, I3 and I5 recover I6 through fourth approximate C cell 115. So far all soft errors are recovered.
Similarly, the soft error self-recovery principle for the worst case III: E: c in case III is described in detail, assuming that the initial node group is { I2, I4, I9}. Depending on the circuit configuration and truth table, a logic value flip on the I2, I4 nodes will cause the output node I7 of the third approximation C cell 110 to flip, while I7, I9 will cause the output node I10 of the sixth approximation C cell 117 to flip, ending with soft error propagation. After the single event effect is over, the second approximate C-cell 113, still maintaining the driving capability, the second error-avoidance C-cell 114 will restore nodes I2, I4; the third approximation C unit 110 then restores node I7; then, the fifth error-avoidance C unit 111 restores the correct driving capability, restoring the node I9; finally, I7 and I9 recover I10 via a sixth approximation C unit 117. So far all soft errors are recovered.
Since the worst case scenario in scenario I and scenario III is the three-node flipped self-healing, the invention is also the three-node flipped self-healing in other scenarios in scenario I and scenario III. Further, the present invention is also three-node flipped self-recovering in case II and case IV, depending on the symmetry of the circuit.
To verify the above analysis, the three-point reverse self-recovery capability of the present invention was simulated at room temperature using a 32nmPTM process model in hsice with a supply voltage of 0.9V. The simulation verification result is shown in fig. 7, the lightning symbol represents that the node is an initial flip node, and the soft error injection description is shown in table 9:
TABLE 9
According to theoretical analysis and simulation verification, the high-reliability latch can realize complete self-recovery of any three-node flip, and obviously can also realize self-recovery of any single-node flip and double-node flip.
In summary, the invention provides a radiation-resistant reinforcement latch based on heterogeneous C units:
1) The latch design has high reliability, and can be completely self-recovered from level inversion of any three internal nodes;
2) Due to the special data output node design of the error avoidance C unit, the structure can reduce the possibility of level inversion on half nodes;
3) The area cost is lower, the structure uses approximate C units, the number of transistors of the approximate C units is smaller than that of transistors of the traditional C units, and the adopted heterogeneous annular cross interlocking structure is a feedback loop for forming cross interlocking by four different subunits, so that the soft error self-recovery capability of any three internal nodes is realized.
4) The invention uses the fast path and clock control technique, the latch has only one transmission gate from the signal input end to the signal output end, and half of the circuit sub-units can be closed under the condition of no need, thus saving the power consumption and the delay cost. Therefore, the invention can be used for replacing the latch in the advanced integrated circuit working under the severe radiation environment, and can meet the requirement of a key system on high reliability.
The foregoing is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art, who is within the scope of the present invention, should make equivalent substitutions or modifications according to the technical scheme of the present invention and the inventive concept thereof, and should be covered by the scope of the present invention.

Claims (7)

1. A three-point flip self-recovery latch based on heterogeneous C units is characterized in that: the system comprises a signal input module, a transmission module, a matrix storage module, an internal node module and a signal output module;
the transmission module comprises a first transmission gate, a second transmission gate, a third transmission gate, a fourth transmission gate, a fifth transmission gate and a sixth transmission gate;
The matrix storage module comprises a first error avoidance C unit, a first approximate C unit, a second error avoidance C unit, a second approximate C unit, a third error avoidance C unit, a third approximate C unit, a fourth error avoidance C unit, a fourth approximate C unit, a fifth error avoidance C unit, a fifth approximate C unit, a sixth error avoidance C unit and a sixth approximate C unit;
the signal input module comprises a data input node D, a first clock input node CK and a second clock input node NCK;
the internal node module comprises an internal node I1, an internal node I2, an internal node I3, an internal node I4, an internal node I5, an internal node I6, an internal node I7, an internal node I8, an internal node I9, an internal node I10, an internal node I11 and an internal node I12;
the signal output module comprises a data output node Q;
the data input node D is connected with signal input nodes of the first transmission gate, the second transmission gate, the third transmission gate, the fourth transmission gate, the fifth transmission gate and the sixth transmission gate;
the first clock input node CK is respectively connected with the N-type clock signal input nodes of the first transmission gate, the second transmission gate, the third transmission gate, the fourth transmission gate, the fifth transmission gate and the sixth transmission gate; the second approximate C unit, the fourth approximate C unit and the sixth approximate C unit have P-type signal input nodes P 1 The method comprises the steps of carrying out a first treatment on the surface of the The P-type signal input nodes P of the second error-avoidance C unit, the fourth error-avoidance C unit and the sixth error-avoidance C unit 1 Connecting;
the second clock input node NCK is respectively connected with the P-type clock signal input nodes of the first transmission gate, the third transmission gate and the fifth transmission gate; the second approximate C unit, the fourth approximate C unit and the sixth approximate C unit are connected with the N-type signal input node N 1 The method comprises the steps of carrying out a first treatment on the surface of the N-type signal input nodes N of the second error-avoidance C unit, the fourth error-avoidance C unit and the sixth error-avoidance C unit 2 Connecting;
the internal node I1 is respectively connected with the P-type signal output node O of the first error avoidance C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of said second approximate C cell 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of the second error avoidance C unit 1 Connecting;
the internal node I2 is respectively connected with the complementary signal output node O of the second approximate C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the P-type signal input node P of the third error avoidance C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the P-type signal input node P of the third approximate C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the N-type signal input node N of the second error avoidance C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the The signal output node of the third transmission gate is connected;
the internal node I3 is respectively connected with the complementary signal output node O of the first approximate C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the N-type signal input node N of the second error avoidance C unit 3 The method comprises the steps of carrying out a first treatment on the surface of the The fourth approximate C unitN signal input node N of (2) 2 The method comprises the steps of carrying out a first treatment on the surface of the P-type signal input node P of the third error avoidance C unit 2 Connecting;
the internal node I4 is respectively connected with the N-type signal output node O of the second error avoidance C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of the third approximate C cell 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of the fifth error avoidance C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the The signal output node of the fourth transmission gate is connected;
the internal node I5 is respectively connected with the P-type signal output node O of the third error avoidance C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of the fourth C-like cell 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of the fourth error avoidance C unit 1 Connecting;
the internal node I6 is respectively connected with the complementary signal output node O of the fourth approximate C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the P-type signal input node P of the fifth error avoidance C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the P-type signal input node P of the fifth approximate C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the N-type signal input node N of the fourth error avoidance C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the The signal output node of the fifth transmission gate is connected;
the internal node I7 is respectively connected with the complementary signal output node O of the third approximate C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the N-type signal input node N of the fourth error avoidance C unit 3 The method comprises the steps of carrying out a first treatment on the surface of the N-type signal input node N of the sixth approximate C unit 2 The method comprises the steps of carrying out a first treatment on the surface of the P-type signal input node P of the fifth error avoidance C unit 2 Connecting;
the internal node I8 is respectively connected with the N-type signal output node O of the fourth error avoidance C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of the fifth approximate C cell 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of the first error avoidance C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the The signal output node of the sixth transmission gate is connected;
the internal node I9 is respectively connected with the P-type signal output node O of the fifth error avoidance C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of the sixth approximate C cell 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of the sixth error avoidance C unit 1 Connecting;
the saidThe internal node I10 is respectively connected with the complementary signal output node O of the sixth approximate C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the P-type signal input node P of the first error avoidance C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the P-type signal input node P of the first approximate C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the N-type signal input node N of the sixth error avoidance C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the The signal output node of the first transmission gate is connected;
the internal node I11 is respectively connected with the complementary signal output node O of the fifth approximate C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the N-type signal input node N of the sixth error avoidance C unit 3 The method comprises the steps of carrying out a first treatment on the surface of the N-type signal input node N of the second approximate C unit 2 The method comprises the steps of carrying out a first treatment on the surface of the P-type signal input node P of the first error avoidance C unit 2 Connecting;
the internal node I12 is respectively connected with the N-type signal output node O of the sixth error avoidance C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of the first approximate C cell 1 The method comprises the steps of carrying out a first treatment on the surface of the Complementary signal input node C of the third error avoidance C unit 1 The method comprises the steps of carrying out a first treatment on the surface of the The signal output node of the second transmission gate is connected;
the data output node Q is connected with the internal node I6.
2. A three-point flip-flop self-restore latch based on heterogeneous C cells according to claim 1, wherein: the first transmission gate comprises a first PMOS and a first NMOS, and the sources of the first PMOS and the first NMOS are connected together to serve as a signal input node of the first transmission gate;
the drains of the first PMOS and the first NMOS are connected together to serve as a signal output node of a first transmission gate;
the first PMOS gate is connected with the second clock input node NCK through a P-type clock signal input node of the first transmission gate;
the first NMOS gate is an N-type clock signal input node of a first transmission gate and is connected with the first clock input node CK;
the third transmission gate and the fifth transmission gate have the same structure as the first transmission gate.
3. A three-point flip-flop self-restore latch based on heterogeneous C cells according to claim 1, wherein: the second transmission gate comprises a second NMOS, and the source of the second NMOS is a signal input node of the second transmission gate; the drain electrode of the second NMOS is a signal output node of the second transmission gate; the second NMOS gate is connected with the first clock input node CK by an N-type clock signal input node of the second transmission gate;
the fourth transmission gate and the sixth transmission gate have the same structure as the second transmission gate.
4. A three-point flip-flop self-restore latch based on heterogeneous C cells according to claim 1, wherein: the first approximate C unit comprises a second PMOS, a third PMOS and a third NMOS, and the grid connection of the second PMOS and the third PMOS is used as a complementary input node C of the first approximate C unit 1 ；
The gate of the third PMOS is the P-type input node P of the first approximate C-cell 1 ；
The drain of the third PMOS and the drain of the third NMOS serve as the complementary output nodes O of the first approximate C cell 1 ；
The drain electrode of the second PMOS is connected with the source electrode of the third PMOS, the source electrodes of the second PMOS and the substrates of the second PMOS and the third PMOS are externally connected with a power supply VDD, and the source electrode of the third NMOS and the substrate of the third NMOS are grounded to GND;
The third approximate C unit and the fifth approximate C unit have the same structure as the first approximate C unit.
5. A three-point flip-flop self-restore latch based on heterogeneous C cells according to claim 1, wherein: the first error-avoidance C unit comprises a fourth PMOS, a fifth PMOS, a sixth PMOS and a fourth NMOS, wherein the grid electrode of the fourth PMOS is connected with the grid electrode of the fourth NMOS to be used as a complementary input node C of the first error-avoidance C unit 1 ；
The gate of the fifth PMOSP-type input node P of the first error-avoidance C unit 1 ；
The gate of the sixth PMOS is the P-type input node P of the first error-avoidance C unit 2 ；
The drain of the fifth PMOS is connected with the source of the sixth PMOS as the P-type output node O of the first error-avoidance C unit 1 ；
The drain electrode of the fourth PMOS is connected with the source electrode of the fifth PMOS, the drain electrode of the sixth PMOS is connected with the drain electrode of the fourth NMOS, the source electrode of the fourth PMOS and the substrates of the fourth PMOS, the fifth PMOS and the sixth PMOS are externally connected with a power supply VDD, and the source electrode of the fourth NMOS and the substrate of the fourth NMOS are grounded GND;
the third error-avoidance C unit and the fifth error-avoidance C unit have the same structure as the first error-avoidance C unit.
6. A three-point flip-flop self-restore latch based on heterogeneous C cells according to claim 1, wherein: the second approximate C unit comprises a seventh PMOS, an eighth PMOS, a fifth NMOS, a sixth NMOS and a seventh NMOS, wherein the grid electrode of the seventh PMOS and the grid electrode of the seventh NMOS tube are connected as a complementary input node C of the second approximate C unit 1 ；
The gate of the eighth PMOS is the P-type input node P of the second approximate C cell 1 ；
The gate of the fifth NMOS is the N-type input node N of the second approximate C cell 1 ；
The grid of the sixth NMOS is the N-type input node N of the second approximate C unit 2 ；
The drain of the eighth PMOS is connected with the drain of the fifth NMOS as the complementary output node O of the second approximate C cell 1 ；
The drain electrode of the seventh PMOS is connected with the source electrode of the eighth PMOS, the source electrode of the fifth NMOS is connected with the drain electrode of the sixth NMOS, the source electrode of the sixth NMOS is connected with the drain electrode of the seventh NMOS, the source electrodes of the seventh PMOS and the substrates of the seventh PMOS and the eighth PMOS are externally connected with a power supply VDD, and the source electrodes of the seventh NMOS and the substrates of the fifth NMOS, the sixth NMOS and the seventh NMOS are all connected with the ground GND;
The fourth and sixth approximate C-cells are identical in structure to the second approximate C-cell.
7. A three-point flip-flop self-restore latch based on heterogeneous C cells according to claim 1, wherein: the second error-avoidance C unit comprises a ninth PMOS, a tenth PMOS, an eighth NMOS, a ninth NMOS, a tenth NMOS and an eleventh NMOS, wherein the grid of the ninth PMOS is connected with the grid of the eleventh NMOS to be used as a complementary input node C of the second error-avoidance C unit 1 ；
The tenth PMOS gate is the P-type input node P of the second error-avoidance C unit 1 ；
The gate of the eighth NMOS is the N-type input node N of the second error-avoidance C unit 1 ；
The gate of the ninth NMOS is the N-type input node N of the second error-avoidance C unit 2 ；
The gate of the tenth NMOS is the N-type input node N of the second error-avoidance C unit 3 ；
The source of the eighth NMOS is connected with the drain of the ninth NMOS as the N-type output node O of the second error-avoidance C unit 1 ；
The drain electrode of the ninth PMOS is connected with the source electrode of the tenth PMOS, the drain electrode of the tenth PMOS is connected with the drain electrode of the eighth NMOS, the source electrode of the ninth NMOS is connected with the drain electrode of the tenth NMOS, the source electrode of the tenth NMOS is connected with the drain electrode of the eleventh NMOS, the source electrodes of the ninth PMOS and the substrates of the ninth PMOS and the tenth PMOS are externally connected with a power supply VDD, and the source electrode of the eleventh NMOS is connected with the substrates of the eighth NMOS, the ninth NMOS, the tenth NMOS and the eleventh NMOS to be connected with a ground GND;
The fourth error-avoidance C unit and the sixth error-avoidance C unit have the same structure as the second error-avoidance C unit.
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