CN109271282B - Single-particle multi-dislocation autonomous repair triple-redundancy assembly line and design method - Google Patents
Single-particle multi-dislocation autonomous repair triple-redundancy assembly line and design method Download PDFInfo
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Abstract
A design method of a single-particle multi-dislocation self-repairing triple-redundancy pipeline adopts three pipelines to process the same instruction stream in parallel; a voting arbitration logic circuit and an error correction control logic circuit are arranged behind each stage of the three pipelines; the voting arbitration logic circuit behind each stage of the three pipelines is used for judging the data output by the three pipelines at the stage and then outputting the judgment result to the error correction control logic circuit; and the error correction control logic circuit corrects possible data errors according to the judgment result of the voting arbitration logic circuit. The method improves the reliability of the pipeline and meets the requirement of delay performance between the pipeline stages.
Description
Technical Field
The invention relates to a design method of a single-particle multi-dislocation autonomous repair triple-redundancy flow line, and belongs to the field of microelectronic reinforcement design.
Background
Currently, integrated circuit technology has fully entered the nanometer era, and processors for aerospace have been developed by adopting nanometer-scale processes. Under the nanometer technology, the single event effect is more serious, and especially the problem that single event upset and single event transient cause single-bit errors and multi-bit errors of a processor is more prominent. The pipeline is used as an important component of a high-performance processor and is used for completing the execution of an instruction stream and writing an execution result into a data cache or a register file, and the pipeline internally comprises a large number of registers and combinational logic, is the most sensitive part of the processor and is most susceptible to the single event effect. If the pipeline is affected by the single event effect to generate single-bit errors and multi-bit errors, which cause errors in the execution result of the pipeline, the processor will work abnormally. In the prior art, the triple-modular redundancy register method can only solve the problem of single-event-effect-induced single-bit data upset errors, but cannot solve the problem of single-event-multiple-bit data upset errors; and the simple adoption of the pipeline backup method is ineffective for the situation that multiple bits occur in different pipeline stages of a plurality of pipelines.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the method carries out triple-modular redundancy fault tolerance on each stage of the flowing water, and simultaneously autonomously corrects the flowing water with the stage of error, thereby not only solving the problem that a single flowing water generates multi-bit errors, but also solving the problem that different flowing water stages of a plurality of flowing water lines generate multi-bit errors, not only improving the reliability of the flowing water, but also considering the delay performance requirements of the flowing water stages.
The purpose of the invention is realized by the following technical scheme:
a design method of a single-particle multi-dislocation self-repairing triple-redundancy pipeline adopts three pipelines to process the same instruction stream in parallel; a voting arbitration logic circuit and an error correction control logic circuit are arranged behind each stage of the three pipelines;
the voting arbitration logic circuit behind each stage of the three pipelines is used for judging the data output by the three pipelines at the stage and then outputting the judgment result to the error correction control logic circuit;
and the error correction control logic circuit corrects the possible error data according to the judgment result of the voting arbitration logic circuit.
According to the design method of the single-event multi-dislocation self-repairing triple-redundancy pipeline, when the data output by the three pipelines at a certain stage has errors, the voting arbitration logic circuit adopts a method of three-judgment two to determine the correct data output by the three pipelines at the stage, then judges the serial number of the pipeline with the errors, and outputs the correct data output by the three pipelines at the stage and the serial number of the pipeline with the errors to the error correction control logic circuit.
The single-event multi-bit error self-repairing triple redundancyThe method for designing the assembly line comprises the following steps that when the single-particle environment of the space causes the single-particle upset threshold value of the assembly line to exceed 37 MeV-cm2At/mg, the voting arbitration logic circuit determines the correct data output by the three pipelines at the stage by adopting the following method:
the method comprises the steps of testing any one stage output of three assembly lines based on a ground simulation experiment device, obtaining reliability indexes of the three assembly lines at any one stage respectively under a single-particle environment, adopting output data of the assembly line with the highest reliability index at the stage as correct data of the three assembly lines at the stage, judging the serial number of the assembly line with errors, and outputting the correct data of the three assembly lines at the stage and the serial number of the assembly line with errors to an error correction control logic circuit.
According to the design method of the single-event multi-dislocation self-repairing triple-redundancy pipeline, the error correction control logic circuit corrects the data output by the pipeline with errors at the stage according to the correct data output by the three pipelines at the stage and the serial number of the pipeline with errors.
According to the design method of the single-particle multi-dislocation autonomous repair triple-redundancy production line, the three production lines have the same structure.
A single-event multi-dislocation self-repairing triple-redundancy pipeline comprises three pipelines for processing the same instruction stream in parallel, a voting arbitration logic circuit and an error correction control logic circuit; a voting arbitration logic circuit and an error correction control logic circuit are arranged behind each stage of the three pipelines;
the voting arbitration logic circuit behind each stage of the three pipelines is used for judging the data output by the three pipelines at the stage and then outputting the judgment result to the error correction control logic circuit;
and the error correction control logic circuit corrects possible data errors according to the judgment result of the voting arbitration logic circuit.
When the data output by the three pipelines at a certain stage has errors, the voting arbitration logic circuit adopts a three-to-two method to determine the correct data output by the three pipelines at the stage, then judges the serial number of the pipeline with errors, and outputs the correct data output by the three pipelines at the stage and the serial number of the pipeline with errors to the error correction control logic circuit.
When the single-particle environment of the single-particle multi-dislocation self-repairing triple-redundancy assembly line causes the single-particle upset threshold of the assembly line to exceed 37 MeV-cm2At/mg, the voting arbitration logic circuit determines the correct data output by the three pipelines at the stage by adopting the following method:
the method comprises the steps of testing any one stage output of three assembly lines based on a ground simulation experiment device, obtaining reliability indexes of the three assembly lines at any one stage respectively under a single-particle environment, adopting output data of the assembly line with the highest reliability index at the stage as correct data of the three assembly lines at the stage, judging the serial number of the assembly line with errors, and outputting the correct data of the three assembly lines at the stage and the serial number of the assembly line with errors to an error correction control logic circuit.
According to the single-event multi-dislocation self-repairing triple redundant assembly line, the error correction control logic circuit corrects the data output by the pipeline with errors at the stage according to the correct data output by the three assembly lines at the stage and the serial number of the assembly line with errors.
The three redundant assembly lines are independently repaired by the single-particle multi-dislocation, and the structures of the three assembly lines are the same.
Compared with the prior art, the invention has the following beneficial effects:
(1) the invention provides a design method of a single-particle multi-dislocation self-repairing triple-redundancy pipeline, which solves the problem that a single pipeline generates multi-bit errors and also solves the problem that different pipeline stages of a plurality of pipelines generate multi-bit errors;
(2) the invention adopts an error correction mechanism at each stage of the flow, thereby avoiding the accumulation of single event errors and improving the reliability of the flow line;
(3) the invention adopts triple modular redundancy fault tolerance at each stage of the flowing water, only the logic gate delay of the voter is increased, and the logic gate delay under the nano process is in picosecond magnitude and is far smaller than the nanosecond magnitude delay between the flowing water stages, so the invention improves the reliability of the flowing water and also gives consideration to the flowing water delay performance requirement;
(4) according to the method, voting arbitration is carried out on the basis of the reliability indexes of the assembly lines at any one stage, which are obtained by ground simulation experiments, under the condition of severe space environment, on one hand, although the structures of the three assembly lines are the same, the method still overcomes the problem of product reliability introduced by the production process of the assembly lines, on the other hand, the reliability of each stage of the three assembly lines under the application environment is more practically distinguished by means of the protection factors such as equipment shells, installation positions and the like of the assembly lines in the practical application process, and on the basis of the voting arbitration results, the reliability of the triple-redundancy assembly lines can be improved under the extremely severe condition.
Drawings
FIG. 1 is a block diagram of a single-event multi-dislocation autonomous repair triple-redundancy pipeline according to an embodiment of the present invention;
FIG. 2 is a logic diagram of the comparator/arbitration logic according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
A design method of a single-particle multi-dislocation self-repairing triple-redundancy pipeline adopts three pipelines with the same structure to process the same instruction stream in parallel; a voting arbitration logic circuit and an error correction control logic circuit are arranged behind each stage of the three pipelines.
The voting arbitration logic circuit behind each stage of the three pipelines is used for judging the data output by the three pipelines at the stage and then outputting the judgment result to the error correction control logic circuit. When the data output by the three pipelines at a certain stage has errors, the voting arbitration logic circuit adopts a three-to-two method to determine the correct data output by the three pipelines at the stage, then judges the serial number of the pipeline with errors, and outputs the correct data output by the three pipelines at the stage and the serial number of the pipeline with errors to the error correction control logic circuit.
And the error correction control logic circuit corrects the possible error data according to the judgment result of the voting arbitration logic circuit. And the error correction control logic circuit corrects the data output by the pipeline with errors at the stage according to the correct data output by the three pipelines at the stage and the serial number of the pipeline with errors.
For extremely severe space environment, namely when the single particle environment in space causes the single particle upset threshold value of the assembly line to exceed 37MeV cm2At/mg, the voting arbitration logic circuit can also determine the correct data output by the three pipelines at the stage by adopting the following method:
the method comprises the steps of testing the output of any one of three assembly lines based on a ground simulation experiment device, obtaining reliability indexes of the three assembly lines at any one level respectively under a single-particle environment, and adopting the output data of the assembly line with the highest reliability index at the level as the correct data output by the three assembly lines at the level. And then judging the serial number of the pipeline with the error, and outputting correct data output by the three pipelines at the stage and the serial number of the pipeline with the error to an error correction control logic circuit.
A single-event multi-dislocation self-repairing triple-redundancy pipeline comprises three pipelines which process the same instruction stream in parallel and have the same structure, a voting arbitration logic circuit and an error correction control logic circuit; and a voting arbitration logic circuit and an error correction control logic circuit are arranged behind each stage of the three pipelines.
The voting arbitration logic circuit behind each stage of the three pipelines is used for judging the data output by the three pipelines at the stage and then outputting the judgment result to the error correction control logic circuit; when the data output by the three pipelines at a certain stage has errors, the voting arbitration logic circuit adopts a three-to-two method to determine the correct data output by the three pipelines at the stage, then judges the serial number of the pipeline with errors, and outputs the correct data output by the three pipelines at the stage and the serial number of the pipeline with errors to the error correction control logic circuit.
And the error correction control logic circuit corrects possible data errors according to the judgment result of the voting arbitration logic circuit. And the error correction control logic circuit corrects the data output by the pipeline with errors at the stage according to the correct data output by the three pipelines at the stage and the serial number of the pipeline with errors.
Under extremely severe space environment, namely when the single-particle environment of the space causes the single-particle upset threshold of the assembly line to exceed 37MeV cm2At/mg, the voting arbitration logic circuit can also determine the correct data output by the three pipelines at the stage by adopting the following method:
the method comprises the steps of testing the output of any one of three assembly lines based on a ground simulation experiment device, obtaining reliability indexes of the three assembly lines at any one level respectively under a single-particle environment, and adopting the output data of the assembly line with the highest reliability index at the level as the correct data output by the three assembly lines at the level. And then judging the serial number of the pipeline with the error, and outputting correct data output by the three pipelines at the stage and the serial number of the pipeline with the error to an error correction control logic circuit.
Example (b):
the embodiment of the invention is shown in figure 1 and comprises a pipeline 1, a pipeline 2, a pipeline 3, a voting arbitration logic circuit and an error correction control logic circuit, wherein the periphery of the pipeline comprises an instruction cache, a data cache and a register file. The instruction cache, the data cache and the register file are shared by three pipelines, wherein the instruction cache is used for storing instructions executed by the pipelines and sending the instructions to the first-stage pipelines of the pipeline 1, the pipeline 2 and the pipeline 3; the data cache is used for storing data output by the pipeline and providing operation operands for the pipeline; the register file is used for storing data output by the pipeline and providing operation operands for the pipeline.
The pipelines 1, 2 and 3 have the same structure and are redundant backup with each other, each pipeline comprises N stages of pipeline units, and N is more than or equal to 3 and less than or equal to 13. The result of each stage of the pipeline is output to the voter and the arbitration logic, the result of the voter is output to the next stage of the pipeline or the data buffer and the register file, and the result of the arbitration logic is output to the error correction control logic circuit.
The voter votes the result from each of the three pipelines by two out of three, and outputs the correct result.
The arbitration logic works as shown in fig. 2: if the results of the pipeline 1, the pipeline 2 and the pipeline 3 are consistent, outputting error-free information to an error correction control logic circuit; if the results of the pipeline 1 and the pipeline 2 are consistent, the results of the pipeline 1 and the pipeline 3 are inconsistent, and the results of the pipeline 2 and the pipeline 3 are inconsistent, the pipeline 3 is indicated to have an error, and pipeline 3 error information is output to the error correction control logic circuit; if the results of the pipeline 1 and the pipeline 3 are consistent, the results of the pipeline 1 and the pipeline 2 are inconsistent, and the results of the pipeline 3 and the pipeline 2 are inconsistent, the pipeline 2 is indicated to have an error, and pipeline 2 error information is output to an error correction control logic circuit; if the results of the pipeline 2 and the pipeline 3 are consistent, the results of the pipeline 2 and the pipeline 1 are inconsistent, and the results of the pipeline 3 and the pipeline 1 are inconsistent, the pipeline 1 is indicated to have an error, and pipeline 1 error information is output to the error correction control logic circuit.
And after receiving the error pipeline information, the error correction control logic circuit corrects the pipeline state of the error of the stage according to an error correction algorithm, the correction operation occupies one clock cycle, and the pipeline operation of the stage is carried out again in the next clock cycle. Error correction algorithm: when pipeline 1 is a faulty pipeline, pipeline 3 replaces pipeline 1 of this stage; when pipeline 2 is a wrong pipeline, pipeline 1 is used to replace pipeline 2 of the stage; when pipeline 3 is a faulty pipeline, pipeline 1 replaces pipeline 3 of this stage.
Those skilled in the art will appreciate that those matters not described in detail in the present specification are well known in the art.
Claims (4)
1. A design method for a single-particle multi-dislocation autonomous repair triple-redundancy pipeline is characterized by comprising the following steps: three pipelines are adopted to process the same instruction stream in parallel; a voting arbitration logic circuit and an error correction control logic circuit are arranged behind each stage of the three pipelines;
the voting arbitration logic circuit behind each stage of the three pipelines is used for judging the data output by the three pipelines at the stage and then outputting the judgment result to the error correction control logic circuit;
the error correction control logic circuit corrects possible error data according to the judgment result of the voting arbitration logic circuit;
when the data output by the three pipelines at a certain stage has errors, the voting arbitration logic circuit adopts a three-to-two method to determine the correct data output by the three pipelines at the stage, then judges the serial number of the pipeline with errors, and outputs the correct data output by the three pipelines at the stage and the serial number of the pipeline with errors to the error correction control logic circuit;
when the single-particle environment of the space causes the single-particle upset threshold value of the assembly line to exceed 37 MeV-cm2At/mg, the voting arbitration logic circuit determines the correct data output by the three pipelines at the stage by adopting the following method:
testing any one stage output of the three assembly lines based on a ground simulation experiment device to obtain reliability indexes of the three assembly lines at any one stage respectively under a single-particle environment, and adopting output data of the assembly line with the highest reliability index at the stage as correct data output by the three assembly lines at the stage for any same one stage of the three assembly lines;
the error correction control logic circuit corrects the data output by the pipeline with errors at the stage according to the correct data output by the three pipelines at the stage and the serial number of the pipeline with errors, and corrects the state of the pipeline with errors according to an error correction algorithm; the correction operation takes one clock cycle and the stage pipelining operation is resumed in the next clock cycle.
2. The method for designing the single-event multi-dislocation autonomous repair triple-redundancy pipeline according to claim 1, wherein the method comprises the following steps: the three pipelines have the same structure.
3. A single-particle multi-dislocation autonomous repair triple-redundancy pipeline is characterized in that: the system comprises three pipelines for processing the same instruction stream in parallel, a voting arbitration logic circuit and an error correction control logic circuit; a voting arbitration logic circuit and an error correction control logic circuit are arranged behind each stage of the three pipelines;
the voting arbitration logic circuit behind each stage of the three pipelines is used for judging the data output by the three pipelines at the stage and then outputting the judgment result to the error correction control logic circuit;
the error correction control logic circuit corrects possible data errors according to the judgment result of the voting arbitration logic circuit;
when the data output by the three pipelines at a certain stage has errors, the voting arbitration logic circuit adopts a three-to-two method to determine the correct data output by the three pipelines at the stage, then judges the serial number of the pipeline with errors, and outputs the correct data output by the three pipelines at the stage and the serial number of the pipeline with errors to the error correction control logic circuit;
when the single-particle environment of the space causes the single-particle upset threshold value of the assembly line to exceed 37 MeV-cm2At/mg, the voting arbitration logic circuit determines the correct data output by the three pipelines at the stage by adopting the following method:
testing any one stage output of the three assembly lines based on a ground simulation experiment device to obtain reliability indexes of the three assembly lines at any one stage respectively under a single-particle environment, and adopting output data of the assembly line with the highest reliability index at the stage as correct data output by the three assembly lines at the stage for any same one stage of the three assembly lines;
the error correction control logic circuit corrects the data output by the pipeline with errors at the stage according to the correct data output by the three pipelines at the stage and the serial number of the pipeline with errors, and corrects the state of the pipeline with errors according to an error correction algorithm; the correction operation takes one clock cycle and the stage pipelining operation is resumed in the next clock cycle.
4. The single-event multi-dislocation autonomous repair triple redundancy pipeline according to claim 3, wherein: the three pipelines have the same structure.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105045672A (en) * | 2015-07-24 | 2015-11-11 | 哈尔滨工业大学 | Multilevel fault tolerance reinforcement satellite information processing system based on SRAM FPGA |
| CN105279049A (en) * | 2015-06-16 | 2016-01-27 | 康宇星科技(北京)有限公司 | Method for designing triple-modular redundancy type fault-tolerant computer IP core with fault spontaneous restoration function |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101551764B (en) * | 2009-02-27 | 2010-11-10 | 北京时代民芯科技有限公司 | An anti-SEE system and method based on synchronizing redundant threads and coding technique |
| CN102135928B (en) * | 2011-03-30 | 2013-07-24 | 武汉大学 | Isomerous triple modular redundancy fault-tolerant method based on LUT (Look-up Table) evolvable hardware |
| CN102355349A (en) * | 2011-06-28 | 2012-02-15 | 中国人民解放军国防科学技术大学 | Fault-tolerant based IDEA (International Data Encryption Algorithm) full-flowing-water hardware encryption method |
| CN102955427B (en) * | 2012-11-14 | 2014-12-03 | 中国船舶重工集团公司第七一九研究所 | Interconnecting error correction type triple-modular redundancy control system and arbitration method |
| CN104731666B (en) * | 2013-12-23 | 2017-12-08 | 深圳市国微电子有限公司 | It is a kind of primary particle inversion resistant from error correction integrated circuit and its error correction method |
| CN103731130B (en) * | 2013-12-27 | 2017-01-04 | 华为技术有限公司 | General fault-tolerant error correction circuit and the decoder of application thereof and triplication redundancy circuit |
| CN104932954B (en) * | 2015-07-01 | 2017-10-24 | 西北工业大学 | Microsatellite FPGA critical data guard methods |
| CN105320575B (en) * | 2015-10-27 | 2018-03-23 | 首都师范大学 | A kind of self checking of duplication redundancy streamline and recovery device and method |
| CN106656184B (en) * | 2016-12-26 | 2020-05-19 | 中国科学院微电子研究所 | Folding interpolation type analog-digital converter with folding rate of 3 and error correction method thereof |
| CN108055031B (en) * | 2017-12-14 | 2021-04-13 | 北京时代民芯科技有限公司 | Self-recovery triple modular redundancy structure for resisting single-particle soft error accumulation |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105279049A (en) * | 2015-06-16 | 2016-01-27 | 康宇星科技(北京)有限公司 | Method for designing triple-modular redundancy type fault-tolerant computer IP core with fault spontaneous restoration function |
| CN105045672A (en) * | 2015-07-24 | 2015-11-11 | 哈尔滨工业大学 | Multilevel fault tolerance reinforcement satellite information processing system based on SRAM FPGA |
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