CN104866390B

CN104866390B - Asynchronous static random access memory triplication redundancy controller

Info

Publication number: CN104866390B
Application number: CN201510178271.0A
Authority: CN
Inventors: 赵建领; 林涛
Original assignee: Institute of High Energy Physics of CAS
Current assignee: Institute of High Energy Physics of CAS
Priority date: 2015-04-15
Filing date: 2015-04-15
Publication date: 2018-07-20
Anticipated expiration: 2035-04-15
Also published as: CN104866390A

Abstract

The present invention provides a kind of asynchronous static random access memory triplication redundancy controller, including：Address signal processing unit is separately connected microprocessor and the address signal pin of SRAM, and for receiving and processing the first address signal, the second address signal is exported to SRAM；Write signal processing unit is separately connected microprocessor and the write signal pin of SRAM, for receiving and processing the first write signal, exports the second write signal to SRAM, and export write operation address gating signal；Read signal processing unit is separately connected microprocessor and the read signal pin of SRAM, for receiving and processing the first read signal, exports the second read signal to SRAM, and export read operation address gating signal；Triplication redundancy error correction unit is separately connected microprocessor and the data signal pin of SRAM, and for carrying out triplication redundancy comparison, output error status signal and comparison result data, error correction is carried out to the Backup Data of SRAM storages.The present invention have many advantages, such as it is simple in structure, compatible it is strong, applied widely, reliability is high.

Description

Asynchronous static random access memory triplication redundancy controller

Technical field

The present invention relates to memory Anti-radioactive Fault-tolerant technical field more particularly to a kind of three moulds of asynchronous static random access memory Redundant manipulator.

Background technology

Asynchronous Static RAM (Static Random Access Memory, hereinafter referred to as Asynchronous SRAM) due to It is high with integrated level, read or write speed is fast, low-power consumption and with complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, hereinafter referred to as CMOS) technique it is completely compatible the features such as, be widely used in each class of electronic devices The middle storage for carrying out data.It is same wide in space application field, each in-orbit spacecraft, satellite load etc. electronics equipment The general storage that data are carried out using Asynchronous SRAM.Due to having various particles, such as proton, electronics, α in space environment Particle, heavy ion, gamma-rays etc..A variety of single particle effects (SEE) will occur in these particle bombardments to Asynchronous SRAM, wrap Include the soft errors such as damage and single-particle inversion (SEU) firmly such as displacement damage, total dose effect.Asynchronous SRAM is in long-term big agent It measures under radiation environment, especially especially sensitive to Single event upset effecf, Single event upset effecf will lead to storage content It is mutated between ' 0 ', ' 1 ', causes the corrupt data of storage.Once corrupt data will lead to system dysfunction, jeopardize spacecraft Reliability, function and service life.

Characteristic size with the gradually micromation of CMOS integrated circuit technologies, device constantly reduces, and single-particle occurs and turns over The critical charge threshold value turned is lower and lower.On the other hand, system is higher and higher to the capacity requirement of SRAM memory, this integrated The probability that the raising of degree further results in SRAM memory generation single-particle inversion is increasing.

In order to resist single particle effect, especially Single event upset effecf, often come pair from device level and application layer at present Asynchronous SRAM is reinforced.Device level is to carry out radiation resistance reinforcing to device design and processes itself, such as Chinese invention is special A kind of SRAM for radiation hardened design is disclosed in sharp radioresistance sram cell (number of patent application 201410223064.8) Unit, in addition it can use the better SOI of Radiation hardness (Silicon On Insulator, abbreviation SOI) technique next life Produce SRAM memory.But such methods are all only to improve radiation-resistant ability, can not fundamentally be prevented radiation-induced Single event upset effecf.Therefore, it is necessary to SRAM progress radiation hardenings from application angle.In system application, one As use triplication redundancy technology (Triple modular redundancy, TMR) or Error Checking and Correcting coding techniques (Error detection and correction, EDAC) is realized.Triplication redundancy technology is by the same data backup three Part, correct data is exported by two from three majority voting, if the error of a copy of it Backup Data can be corrected back；EDAC skills Art is encoded to data, increases check bit, then by the correctness of decoding algorithm verify data, according to answering for algorithm Miscellaneous degree can complete 1 or multi-bit correction.These methods generally require to occupy the run time of system software.For example, middle promulgated by the State Council Bright the patent a kind of controller and method (number of patent application 201310648233.8) of the anti-SEU incorrect integrations towards SRAM, in The primary particle inversion resistant memory error correction and detection of state's patent of invention space computer and automatic write back method (number of patent application 200510041617.9).Software for Design will be caused to complicate in this way, waste the processing time of a large amount of microprocessors, increased not Responsible factor.For EDAC technologies, the development of special EDAC chips is also carried out both at home and abroad, such as in S698M SoC chips (Huang Lin, old tiger, beam precious jade wait Chinese Integrated Circuits, 2008,112 (9) with realization for the design of EDAC modules:50-54.) Deng.But EDAC encoding and decoding are complicated, error correcting capability ratio TMR is weak, executes speed and is also limited.Therefore, the mode based on triplication redundancy It is best.But it can not increase system software burden currently without a kind of effective scheme, not change system microprocessor On the basis of device software configuration, the fault-tolerant processing of data is realized to the progress triplication redundancy control of existing asynchronous SRAM memory.

Fig. 1 is the application scenarios schematic diagram of above-mentioned static random access memory asynchronous in the prior art.Microprocessor (monolithic Machine, FPGA etc.) directly it is connect with SRAM, including address bus Addr, data/address bus Data, (low level has chip selection signal CS Effect), write enable signal WE (low level is effective) and reading enable signal OE (low level is effective).These signals are the marks of Asynchronous SRAM The read-write sequence of quasi- interface, the Asynchronous SRAM of different model is usually all unified, except that data/address bus Data and ground There may be differences for the bit wide of location bus Addr.

Fig. 2 and Fig. 3 is respectively that the sequential of write operation/read operation of above-mentioned static random access memory asynchronous in the prior art is shown It is intended to.In the case where chip selection signal CS is low, reading enable signal OE is height, by data between write enable signal WE low periods In the specified address Addr of Data write-ins；It is in the case that low write enable signal WE is high, to read enable signal in chip selection signal CS Between OE low periods, the data Data in specified address Addr will be exported.

Invention content

The brief overview about the present invention is given below, in order to provide the basic reason about certain aspects of the invention Solution.It should be appreciated that this general introduction is not the exhaustive general introduction about the present invention.It is not intended to determine the key of the present invention Or pith, nor is it intended to limit the scope of the present invention.Its purpose only provides certain concepts in simplified form, with This is as the preamble in greater detail discussed later.

The present invention, which provides one kind and being not take up system software run time and do not change microprocessor software structure, can be realized The backup of SRAM triplication redundancies, majority voting and the asynchronous static random access memory triplication redundancy controller for correcting function.

The present invention provides a kind of asynchronous static random access memory triplication redundancy controller, including：

Address signal processing unit is separately connected the address signal pin of microprocessor and static random access memory, is used for The first address signal of the microprocessor output is received and processed, comprising write operation to static random access memory output Second address signal of location, read operation address or error-correction operation address；

Write signal processing unit is separately connected the write signal pin of the microprocessor and the static random access memory, And it is connect with described address signal processing unit, the first write signal for receiving and processing the microprocessor output, to institute It states static random access memory and exports the second write signal, exported to described address signal processing unit for gating the write operation The gating signal of location；

Read signal processing unit is separately connected the read signal pin of the microprocessor and the static random access memory, And it is connect with described address signal processing unit, the first read signal for receiving and processing the microprocessor output, to institute It states static random access memory and exports the second read signal, exported to described address signal processing unit for gating the read operation The gating signal of location；

Triplication redundancy error correction unit is separately connected data signal pin, the error status signal pin of the microprocessor With the data signal pin of the static random access memory, and respectively with the read signal processing unit, the write signal processing Unit is connected with described address signal processing unit, triplication redundancy comparison is carried out for three parts of Backup Datas to input, to institute State microprocessor output error status signal and comparison result data, to the static random access memory storage Backup Data into Row error correction.

Asynchronous static random access memory triplication redundancy controller setting provided by the invention is in systematic microprocessor and asynchronous Bridge is used as between static random access memory, by microprocessor to the write/read operation automatic conversion of asynchronous static random access memory It for triplication redundancy and two from three majority voting time sequential routine, realizes that triplication redundancy is fault-tolerant and automatically processes, thus instead of being Triplication redundancy is handled in system software, alleviates the burden of system software, while without changing systematic microprocessor software configuration, dropping Reliability has been ensured while the low complexity of Design of System Software.In conclusion the asynchronous static random access memory of the present invention Triplication redundancy controller have many advantages, such as it is simple in structure, compatible it is strong, applied widely, reliability is high.

Description of the drawings

Below with reference to the accompanying drawings illustrate embodiments of the invention, the above of the present invention and its can be more readily understood that Its objects, features and advantages.Component in attached drawing is intended merely to show the principle of the present invention.In the accompanying drawings, identical or similar Technical characteristic or component will be indicated using same or similar reference numeral.

Fig. 1 is the application scenarios schematic diagram of asynchronous static random access memory in the prior art.

Fig. 2 is the write operation time diagram of asynchronous static random access memory in the prior art.

Fig. 3 is the read operation time diagram of asynchronous static random access memory in the prior art.

Fig. 4 is the application scenarios schematic diagram of the asynchronous static random access memory triplication redundancy controller of the present invention.

Fig. 5 is the pin configuration schematic diagram of the asynchronous static random access memory triplication redundancy controller of the present invention.

Fig. 6 is the internal structure schematic diagram of the asynchronous static random access memory triplication redundancy controller of the present invention.

Fig. 7 is the structural representation of the write signal time delay module of the asynchronous static random access memory triplication redundancy controller of the present invention Figure.

Fig. 8 is the sequential signal of the write signal time delay module of the asynchronous static random access memory triplication redundancy controller of the present invention Figure.

Fig. 9 is the structural schematic diagram for writing tfi module of the asynchronous static random access memory triplication redundancy controller of the present invention.

Figure 10 is the time diagram for writing tfi module of the asynchronous static random access memory triplication redundancy controller of the present invention.

Figure 11 is that the structure of the read signal time delay module of the asynchronous static random access memory triplication redundancy controller of the present invention is shown It is intended to.

Figure 12 is that the sequential of the read signal time delay module of the asynchronous static random access memory triplication redundancy controller of the present invention is shown It is intended to.

Figure 13 is the structural schematic diagram of the reading tfi module of the asynchronous static random access memory triplication redundancy controller of the present invention.

Figure 14 is the time diagram of the reading tfi module of the asynchronous static random access memory triplication redundancy controller of the present invention.

Figure 15 is the structural representation of the address calculation module of the asynchronous static random access memory triplication redundancy controller of the present invention Figure.

Figure 16 is the sequential signal of the address calculation module of the asynchronous static random access memory triplication redundancy controller of the present invention Figure.

Figure 17 is the structural schematic diagram of the write address module of the asynchronous static random access memory triplication redundancy controller of the present invention.

Figure 18 is the time diagram of the write address module of the asynchronous static random access memory triplication redundancy controller of the present invention.

Figure 19 is the structural schematic diagram of the reading address module of the asynchronous static random access memory triplication redundancy controller of the present invention.

Figure 20 is the time diagram of the reading address module of the asynchronous static random access memory triplication redundancy controller of the present invention.

Figure 21 is the asynchronous static random access memory triplication redundancy controller of the present invention to asynchronous static random access memory address The principle schematic that space divides.

Figure 22 is the structural representation of the error correction address module of the asynchronous static random access memory triplication redundancy controller of the present invention Figure.

Figure 23 is second backup of error correction address module of the asynchronous static random access memory triplication redundancy controller of the present invention Time diagram when corrupt data.

Figure 24 is the structural representation of the majority voting module of the asynchronous static random access memory triplication redundancy controller of the present invention Figure.

Figure 25 is the majority voting module error-free received data of the asynchronous static random access memory triplication redundancy controller of the present invention When time diagram.

Figure 26 is that there are one mistakes for the majority voting module of the asynchronous static random access memory triplication redundancy controller of the present invention Time diagram when data.

Figure 27 is that three data of majority voting module of the asynchronous static random access memory triplication redundancy controller of the present invention are each Time diagram when differing.

Figure 28 is the structural representation of the error correction tfi module of the asynchronous static random access memory triplication redundancy controller of the present invention Figure.

Figure 29 is the sequential signal of the error correction tfi module of the asynchronous static random access memory triplication redundancy controller of the present invention Figure.

Figure 30 is the write operation time diagram of the asynchronous static random access memory triplication redundancy controller of the present invention.

When read operation when Figure 31 is the error-free received data of the asynchronous static random access memory triplication redundancy controller of the present invention Sequence schematic diagram.

Figure 32 be the asynchronous static random access memory triplication redundancy controller of the present invention there are one reading behaviour when wrong data Make time diagram.

Figure 33 is reading when three data of the asynchronous static random access memory triplication redundancy controller of the present invention are different Time sequential routine schematic diagram.

Figure 34 is that the internal signal sequential of the write operation of the asynchronous static random access memory triplication redundancy controller of the present invention is shown It is intended to.

It is interior when Figure 35 is the read operation error-free received data of the asynchronous static random access memory triplication redundancy controller of the present invention Portion's signal sequence schematic diagram.

Figure 36 is that there are one when wrong data for the read operation of the asynchronous static random access memory triplication redundancy controller of the present invention Internal signal time diagram.

Figure 37 is that three data of read operation of the asynchronous static random access memory triplication redundancy controller of the present invention are different When internal signal time diagram.

Figure 38 is the simulation waveform of the write operation of the asynchronous static random access memory triplication redundancy controller of the present invention.

It is imitative when Figure 39 is the read operation error-free received data of the asynchronous static random access memory triplication redundancy controller of the present invention True oscillogram.

When Figure 40 is first corrupt data of read operation of the asynchronous static random access memory triplication redundancy controller of the present invention Simulation waveform.

When Figure 41 is second corrupt data of read operation of the asynchronous static random access memory triplication redundancy controller of the present invention Simulation waveform.

When Figure 42 is the read operation third corrupt data of the asynchronous static random access memory triplication redundancy controller of the present invention Simulation waveform.

Figure 43 is that three data of read operation of the asynchronous static random access memory triplication redundancy controller of the present invention are different When simulation waveform.

Reference sign：

10 asynchronous static random access memory triplication redundancy controllers

1011 first address signal pins

1012 second address signal pins

1021 first data signal pins

1022 second data signal pins

1031 first write signal pins

1032 second write signal pins

1041 first read signal pins

1042 second read signal pins

1051 first error status signal pins

1061 first chip selection signal pins

1062 second chip selection signal pins

121 address calculation modules

123 write address modules

125 read address module

127 error correction address modules

129 second and module

141 write signal time delay modules

143 write tfi module

145 first and module

161 read signal time delay modules

163 read tfi module

181 majority voting modules

183 error correction tfi modules

191 first input buffers

193 first tristate output buffers

195 second input buffers

197 second tristate output buffers

Specific implementation mode

Illustrate the embodiment of the present invention with reference to the accompanying drawings.It is retouched in the attached drawing of the present invention or a kind of embodiment The elements and features stated can be combined with elements and features shown in one or more other attached drawings or embodiment.It answers When note that for purposes of clarity, being omitted known to unrelated to the invention, those of ordinary skill in the art in attached drawing and explanation Component and processing expression and description.

As shown in figure 4, microprocessor is not directly written and read operation to asynchronous static random access memory, but pass through this hair Bright asynchronous static random access memory triplication redundancy controller reads and writes asynchronous static random access memory indirectly as bridge.The present invention Design keep read-write sequence between asynchronous static random access memory triplication redundancy controller and microprocessor and commonly asynchronous The read-write sequence of static random access memory is consistent.

For the write operation each time of the microprocessor, the asynchronous static random access memory triplication redundancy controller will It is converted to the write operation of three different addresses, and the data of write-in are identical and address is different, to play three parts of data backup Effect；Read operation each time for the microprocessor, the asynchronous static random access memory triplication redundancy controller by its The read operation for being converted to three different addresses, progress two from three is decided by vote to the microprocessor after having read three Backup Datas Correct result is exported, then write-back correct result carries out error correction in case of a corrupt data, in case of two corrupt datas And cause three Backup Datas are all different then to return to error status signal to the microprocessor.

As shown in figure 5, the asynchronous static random access memory triplication redundancy controller 10 of the present invention is equipped with and connects the microprocessor Device：

For inputting the first address signal AddrL [N:0] the first address signal pin 1011,

For inputting the first data-signal DataL [M:0] the first data signal pin 1021,

The first write signal pin 1031 for inputting the first write signal WEL,

The first read signal pin 1041 for inputting the first read signal OEL,

For the first error status signal pin 1051 of output error status signal ErrorStatus,

The first chip selection signal pin 1061 for inputting the first chip selection signal CSL；

And the connection static random access memory：

For exporting the second address signal AddrR [N:0] the second address signal pin 1012,

For exporting the second data-signal DataR [M:0] the second data signal pin 1022,

The second write signal pin 1032 for exporting the second write signal WER,

The second read signal pin 1042 for exporting the second read signal OER,

The second chip selection signal pin 1062 for exporting the second chip selection signal CSR.

Wherein, N is address bit wide, and M is data bit width.

As shown in fig. 6, in the present embodiment, asynchronous static random access memory triplication redundancy controller 10 of the invention includes：

Address signal processing unit is separately connected the address signal pin of microprocessor and static random access memory, is used for Receive and process the first address signal AddrL [N of the microprocessor output:0], export and wrap to the static random access memory Second address signal AddrR [N of address containing write operation, read operation address or error-correction operation address:0]；

Write signal processing unit is separately connected the write signal pin of the microprocessor and the static random access memory, And connect with described address signal processing unit, the first write signal WEL for receiving and processing the microprocessor output, to The static random access memory exports the second write signal WER, to the output of described address signal processing unit for gating described write The gating signal of operation address；

Read signal processing unit is separately connected the read signal pin of the microprocessor and the static random access memory, And connect with described address signal processing unit, the first read signal OEL for receiving and processing the microprocessor output, to The static random access memory exports the second read signal OER, is exported to described address signal processing unit for gating the reading The gating signal of operation address；

Triplication redundancy error correction unit is separately connected data signal pin, the error status signal pin of the microprocessor With the data signal pin of the static random access memory, and respectively with the read signal processing unit, the write signal processing Unit is connected with described address signal processing unit, triplication redundancy comparison is carried out for three parts of Backup Datas to input, to institute Microprocessor output error status signal ErrorStatus and comparison result data are stated, the static random access memory is stored Backup Data carry out error correction.

Preferably, the write signal processing unit includes：

Write signal time delay module 141, input terminal connect the first write signal pin 1031, and four output ends export first respectively Zero propagation write signal WEL0, the second delay write signal WEL1, the third delay write signal WEL3 of delay write signal WEL2 and the 4th, are used It is exported in the first write signal WEL multistages are delayed.The write signal pin of first write signal pin 1031 and the microprocessor connects It connects.

Tfi module 143 is write, four input terminals are separately connected four output ends of write signal time delay module 141, and four defeated Outlet exports third write signal WER1, the first gating signal WAddrS1, the second gating signal WAddrS2 and third gating respectively Signal WAddrS3, the gating signal of third write signal WER1 and strobe write operation address for calculating and exporting write operation WAddrS1-WAddrS3。

First writes tfi module 143 and the triplication redundancy error correction unit with module 145, input terminal connection, and output end connects The second write signal pin 1032 is connect, for exporting the second write signal WER, is specifically included in the of write operation sequential export write operation Three write signal WER1, and the 4th write signal WER2 in error-correction operation sequential export error-correction operation.The second write signal pin 1032 connect with the write signal pin of the static random access memory.

As shown in Figure 7, it is preferable that write signal time delay module 141 prolongs including the first delay submodule WELDelay1, second When submodule WELDelay2 and third delay submodule WELDelay3.First write signal WEL input write signals time delay module 141 After be divided into two-way, directly obtain and export the first zero propagation write signal WEL0 all the way, another way passes through the first delay submodule WELDelay1 is delayed to obtain and export the second delay write signal WEL1.Second delay write signal WEL1 passes through the second delay again Module WELDelay2 is delayed to obtain and export third delay write signal WEL2.Third delay write signal WEL2 is prolonged by third again When submodule WELDelay3 be delayed to obtain and export the 4th delay write signal WEL3.

Under normal conditions, the delay parameter of above three delay submodule is identical.The selection of delay parameter is needed according to institute The asynchronous static random access memory used, should be greater than or equal to the asynchronous static random access memory minimum write cycle time.

Fig. 8 is the sequential signal of the write signal time delay module of the asynchronous static random access memory triplication redundancy controller of the present invention Figure.As shown in figure 8, after the first write signal WEL input write signals time delay module 141, the first zero propagation write signal WEL0 zero propagations Synchronism output, the second delay write signal WEL1, the third delays of delay write signal WEL2 and the 4th write signal WEL3 are delayed defeated successively Go out.

As shown in Figure 9, it is preferable that write tfi module 143 include three respectively with write 143 4 input terminals of tfi module and connect 4 input nand gates connect and three input terminals connect respectively with the output end of three 4 input nand gates 3 input with Door.The output result of three 4 input nand gates is respectively the first gating signal WAddrS1, the second gating signal WAddrS2 With third gating signal WAddrS3.3 input and the output result of door are third write signal WER1.

Wherein, there are one reverse input end and three non-inverting inputs, reverse input end are defeated for the one 4 input nand gate band Enter the first zero propagation write signal WEL0；There are two reverse input end and two non-inverting inputs for 2nd 4 input nand gate band End, reverse input end input the delay write signals of the first zero propagation write signal WEL0 and second WEL1；3rd 4 input nand gate carries Three reverse input ends and a non-inverting input, reverse input end input the first zero propagation write signal WEL0, second Be delayed write signal WEL1 and third delay write signal WEL2.

Figure 10 is the time diagram for writing tfi module of the asynchronous static random access memory triplication redundancy controller of the present invention. First gating signal WAddrS1, the second gating signal WAddrS2, third gating signal WAddrS3 and third write signal WER1 Sequential is as shown in Figure 10.

When writing the work of tfi module 143, the first gating signal WAddrS1, the second gating signal WAddrS2 and third gating Signal WAddrS3 is used for three different addresses of gated data backup area, and low level is effective.First gating signal WAddrS1 is Write address module 123 exports the address of the first Backup Data when low level, and the second gating signal WAddrS2 writes ground when being low level Location module 123 exports the address of the second Backup Data, and write address module 123 is defeated when third gating signal WAddrS3 is low level The address for going out third Backup Data, third write signal WER1 is low level during selection exports three write addresses.

Preferably, the read signal processing unit includes：

Read signal time delay module 161, input terminal connect the first read signal pin 1041, and four output ends export first respectively Zero propagation read signal OEL0, the second delay read signal OEL1, the third delay read signal OEL3 of delay read signal OEL2 and the 4th, are used It is exported in the first read signal OEL multistages are delayed.The read signal pin of first read signal pin 1041 and the microprocessor connects It connects.

Tfi module 163 is read, four input terminals are separately connected four output ends of read signal time delay module 161, and four defeated Outlet exports the second read signal OER, the 4th gating signal RAddrS1, the gating letters of the 5th gating signal RAddrS2 and the 6th respectively Number RAddrS3, the gating signal of the second read signal OER and gating read operation address for calculating and exporting read operation RAddrS1, RAddrS2 and RAddrS3.The output end and the second read signal pin 1042 of the second read signal OER of the output connects It connects, the second read signal pin 1042 is connect with the read signal pin of the static random access memory.

As shown in figure 11, it is preferable that read signal time delay module 161 prolongs including the 4th delay submodule OELDelay1, the 5th When the delays of submodule OELDelay2 and the 6th submodule OELDelay3.First read signal OEL input read signals time delay module 161 After be divided into two-way, directly obtain and export the first zero propagation read signal OEL0 all the way, another way passes through the 4th delay submodule OELDelay1 is delayed to obtain and export the second delay read signal OEL1.Second delay read signal OEL1 passes through the 5th delay again Module OELDelay2 is delayed to obtain and export third delay read signal OEL2.Third delay read signal OEL2 prolongs by the 6th again When submodule OELDelay3 be delayed to obtain and export the 4th delay read signal OEL3.

Figure 12 is that the sequential of the read signal time delay module of the asynchronous static random access memory triplication redundancy controller of the present invention is shown It is intended to.As shown in figure 12, after the first read signal OEL input read signals time delay module 161, the first zero propagation read signal OEL0 zero prolongs When synchronism output, the second delay read signal OEL1, the third delays of delay read signal OEL2 and the 4th read signal OEL3 are delayed successively Output.

As shown in figure 13, it is preferable that read tfi module 163 include three respectively with read 163 4 input terminals of tfi module 3 inputs that 4 input nand gates and three input terminals of connection are connect with the output end of three 4 input nand gates respectively With door.The output result of three 4 input nand gates is respectively the 4th gating signal RAddrS1, the 5th gating signal RAddrS2 and the 6th gating signal RAddrS3,3 input and the output result of door are the second read signal OER.

Wherein, there are one reverse input end and three non-inverting inputs, reverse input end are defeated for the 4th 4 input nand gate band Enter the first zero propagation read signal OEL0.There are two reverse input end and two non-inverting inputs for 5th 4 input nand gate band, instead Input the delay read signals of the first zero propagation read signal OEL0 and second OEL1 respectively to input terminal.6th 4 input nand gate carries Three reverse input ends and a non-inverting input, reverse input end input the first zero propagation read signal OEL0, second respectively Be delayed read signal OEL1 and third delay read signal OEL2.

Figure 14 is the time diagram of the reading tfi module of the asynchronous static random access memory triplication redundancy controller of the present invention. 4th gating signal RAddrS1, the 5th gating signal RAddrS2, the 6th gating signal RAddrS3 and the second read signal OER Sequential is as shown in Figure 10.

When reading the work of tfi module 163, the 4th gating signal RAddrS1, the 5th gating signal RAddrS2 and the 6th gating Signal RAddrS3 is used for three different addresses of gated data backup area, and low level is effective.4th gating signal RAddrS1 is It reads the address that address module 125 exports the first Backup Data, to read ground when the 5th gating signal RAddrS2 is low level when low level Location module 125 exports the address of the second Backup Data, and it is defeated that address module 125 is read when the 6th gating signal RAddrS3 is low level The address for going out third Backup Data, the second read signal OER is low level during three reading addresses of selection output.

Preferably, described address signal processing unit includes：

Address calculation module 121, input terminal connect the first address signal pin 1011, and three output ends export first respectively Backup address signal Addr0, the second backup address signal Addr1 and third backup address signal Addr2, for calculating and exporting Three backup address Addr0, Addr1, Addr2 corresponding to first address signal AddrL.First address signal pin 1011 with The address signal pin of the microprocessor connects.

Write address module 123, six input terminals be separately connected write tfi module 143 export gating signal WAddrS1, Three output ends of WAddrS2, WAddrS3 and three output ends of address calculation module 121, output end export write operation address FA1, for receiving and processing the first gating signal WAddrS1, the second gating signal WAddrS2, third gating signal WAddrS3 and the first backup address signal Addr0 of write operation sequential, the second backup address signal Addr1, third backup ground Location signal Addr2, output write operation address FA1.

Read address module 125, six input terminals be separately connected read tfi module 163 export gating signal RAddrS1, Three output ends of RAddrS2, RAddrS3 and three output ends of address calculation module 121, output end export read operation address FA2, for receiving and processing the 4th gating signal RAddrS1, the 5th gating signal RAddrS2, the 6th gating signal RAddrS3 and the first backup address signal Addr0 of read operation sequential, the second backup address signal Addr1, third backup ground Location signal Addr2 exports the read operation address FA2.

Error correction address module 127, seven input terminals, which are separately connected, reads the defeated of second read signal OER of the output of tfi module 163 Three outputs of outlet, three output ends of triplication redundancy error correction unit output gating signal and address calculation module 121 End, output end exports error-correction operation address FA3, for receiving and processing the second read signal OER, the triplication redundancy error correction unit Error-correction operation address gating signal EAddrS1, EAddrS2, EAddrS3 of output and described the first of error-correction operation sequential is standby Part address signal Addr0, the second backup address signal Addr1, the third backup address signal Addr2, described in output Error-correction operation address FA3.

Second is separately connected the output end of write address module 123, reads address module 125 with module 129, three input terminals The output end of output end, error correction address module 127, output end connect the second address signal pin 1012, in write operation Sequence exports write operation address FA1, in read operation sequential export read operation address FA2, in error-correction operation sequential export error-correction operation Address FA3.Second address signal pin 1012 is connect with the address signal pin of the static random access memory.

As shown in figure 15, it is preferable that address calculation module 121 divide No. three counting circuit pair the first address signal AddrL into Row parallel computation is handled, and the first address signal AddrL is directly obtained by buffer and exported the first backup address signal respectively Addr0, the second backup address signal Addr1 is obtained and exported by first adder and offset addition, by the second addition Device and twice of offset addition obtain and export third backup address signal Addr2.

The offset is calculated by the address bit wide of the asynchronous static random access memory.

Preferably, the address bit wide of the asynchronous static random access memory is N, then the calculating of the offset Offset Mode is：

Figure 21 is the asynchronous static random access memory triplication redundancy controller of the present invention to asynchronous static random access memory address The principle schematic that space divides.As shown in figure 21, due to needing the same data inside asynchronous static random access memory Three parts of backup, therefore divided firstly the need of the memory space to asynchronous static random access memory.Asynchronous random static storage The address bit wide of device is N, then can store 2 in total^NA data.In order to back up the needs of three parts of data, address space is pressed According to being sequentially equally divided into three parts, it is followed successively by 0~(Offset-1), Offset~(2*Offset-1), 2*Offset~(3* Offset-1).Wherein,Wherein symbolIndicate downward rounding.For example, in the present embodiment, it is asynchronous with The address bit wide N of machine static memory is 16, thenThree backup address spaces at this time It is followed successively by 0~0x5554,0x5555~0xAAA9,0xAAAA~0xFFFE.After division, asynchronous static random access memory Effective memory space there was only a copy of it, remaining two parts of Backup Data as triplication redundancy uses, i.e., asynchronous random static Effective memory space of memory is reduced to one third, by original 0~2^NIt is reduced into 0~(Offset-1).The same data It will be respectively stored in Addr, Addr+Offset, Addr+2Offset, the wherein address range of Addr is 0~(Offset-1).

Due to 2^NIt cannot be divided exactly by 3, therefore can finally leave in asynchronous static random access memory 1 or 2 addresses not It is used, the address (being in the present embodiment 0xFFFF) finally left is in the asynchronous static random access memory triplication redundancy control Address in device processed as do-nothing operation uses.

As shown in figure 17, it is preferable that write address module 123 passes through three 2 inputs or door and the first gating signal respectively It is WAddrS1, the second gating signal WAddrS2, WAddrS3 couples of the first backup address signal Addr0 of third gating signal, second standby Part address signal Addr1, third backup address signal Addr2 carry out output control, and described in being merged with door by one 3 input Output WA1, WA2 and WA3 of three 2 inputs or door, export write operation address FA1, to realize continuous output write operation sequential The first backup address signal, the second backup address signal and third backup address signal.

Specifically, when the first gating signal WAddrS1 is low level, WA1 exports the first backup address signal Addr0, When the first gating signal WAddrS1 is high level, WA1 exports the last one vacant address 0xFFFF；When the second gating signal When WAddrS2 is low level, WA2 exports the second backup address signal Addr1, when the second gating signal WAddrS2 is high level When, WA2 exports the last one vacant address 0xFFFF；When third gating signal WAddrS3 is low level, WA3 exports third Backup address signal Addr2, when third gating signal WAddrS3 is high level, WA3 exports the last one vacant address 0xFFFF。

As shown in figure 18, when the first gating signal WAddrS1, the second gating signal WAddrS2, third gating signal When WAddrS3 is high level, FA1 outputs in write operation address are 0xFFFF.When the first gating signal WAddrS1 becomes low level When, write operation address FA1 exports the value of the first backup address signal Addr0.When the second gating signal WAddrS2 becomes low level When, write operation address FA1 exports the value of the second backup address signal Addr1.When third gating signal WAddrS3 becomes low level When, write operation address FA1 exports the value of third backup address signal Addr2.Final effect is that write operation address FA1 is continuously defeated Go out three backup address signals, to realize the backup write-in of three parts of data.

As shown in figure 19, it is preferable that read address module 125 respectively by three 2 inputs or door and the 4th gating signal It is RAddrS1, the 5th gating signal RAddrS2, RAddrS3 couples of the first backup address signal Addr0 of the 6th gating signal, second standby Part address signal Addr1, third backup address signal Addr2 carry out output control, and described in being merged with door by one 3 input Output RA1, RA2 and RA3 of three 2 inputs or door, thus the first backup address signal of the continuous output read operation sequential of realization, Second backup address signal and third backup address signal.

Specifically, when the 4th gating signal RAddrS1 is low level, RA1 exports the first backup address signal Addr0, When the 4th gating signal RAddrS1 is high level, RA1 exports the last one vacant address 0xFFFF；When the 5th gating signal When RAddrS2 is low level, RA2 exports the second backup address signal Addr1, when the 5th gating signal RAddrS2 is high level When, RA2 exports the last one vacant address 0xFFFF；When the 6th gating signal RAddrS3 is low level, RA3 exports third Backup address signal Addr2, when the 6th gating signal RAddrS3 is high level, RA3 exports the last one vacant address 0xFFFF。

As shown in figure 20, when the 4th gating signal RAddrS1, the 5th gating signal RAddrS2, the 6th gating signal When RAddrS3 is high level, FA2 outputs in read operation address are 0xFFFF.When the 4th gating signal RAddrS1 becomes low level When, read operation address FA2 exports the value of the first backup address signal Addr0.When the 5th gating signal RAddrS2 becomes low level When, read operation address FA2 exports the value of the second backup address signal Addr1.When the 6th gating signal RAddrS3 becomes low level When, read operation address FA2 exports the value of third backup address signal Addr2.Final effect is that read operation address FA2 is continuously defeated Go out three backup address signals, to realize that the backup of three parts of data is read.

As shown in figure 22, it is preferable that error correction address module 127 includes three 2 inputs or door, 3 input and door and one A includes the 10th input of a reverse input end or door, passes through described three 2 inputs or door and the 7th gating signal respectively It is EAddrS1, the 8th gating signal EAddrS2, EAddrS3 couples of the first backup address signal Addr0 of the 9th gating signal, second standby Part address signal Addr1, third backup address signal Addr2 carry out output control, respectively output EA1, EA2 and EA3, and described three The output end of a 2 input or door is separately connected the non-inverting input of the input terminal of 3 input and door, the 10th input or door Connect the output end of 3 input and door, the input terminal of the second read signal OER of reverse input end connection input, output end output Error-correction operation address FA3.

Specifically, when the 7th gating signal EAddrS1 is low level, EA1 exports the first backup address signal Addr0, When the 7th gating signal EAddrS1 is high level, EA1 exports the last one vacant address 0xFFFF；When the 8th gating signal When EAddrS2 is low level, EA2 exports the second backup address signal Addr1, when the 8th gating signal EAddrS2 is high level When, EA2 exports the last one vacant address 0xFFFF；When the 9th gating signal EAddrS3 is low level, EA3 exports third Backup address signal Addr2, when the 9th gating signal EAddrS3 is high level, EA3 exports the last one vacant address 0xFFFF。

EA1, EA2 and EA3 are input to 3 input and door, and 3 input and the output of door connect with the second read signal OER It is connected to 2 input or door, 2 input or door output error-correction operation address FA3.

Error correction address module 127 at work, when the 7th gating signal EAddrS1, the 8th gating signal EAddrS2, When nine gating signal EAddrS3 are high level, FA3 outputs in error-correction operation address are 0xFFFF.When the 7th gating signal EAddrS1 becomes low level and the second read signal OER when being high level, and error-correction operation address FA3 exports the first backup address letter The value of number Addr0.When the 8th gating signal EAddrS2 becomes low level and the second read signal OER is high level, error-correction operation Address FA3 exports the value of the second backup address signal Addr1.It is high electricity when WAddrS3 becomes low level and the second read signal OER Usually, error-correction operation address FA3 exports the value of third backup address signal Addr2.

Preferably, the triplication redundancy error correction unit includes：

Majority voting module 181, six input terminals, which are separately connected, reads the defeated of second read signal OER of the output of tfi module 161 Outlet, four output ends of read signal time delay module 163, the second data signal pin 1022, six output ends export respectively One comparison result signal C12, the second comparison result signal C23, third comparison result signal C31, majority voting result data FinalDataOut, majority voting result gating signal FinalReadOutControl and error status signal ErrorStatus, for carrying out triplication redundancy comparison to the three parts of Backup Datas inputted by the second data signal pin 1022 And comparison result is exported, to the microprocessor output error status signal ErrorStatus and comparison result data.First ratio It is that three parts of Backup Datas compare two-by-two compared with consequential signal C12, the second comparison result signal C23, third comparison result signal C31 Compared with consequential signal.Second data signal pin 1022 is connect with the data signal pin of the static random access memory.Output Two of majority voting result data FinalDataOut and majority voting result gating signal FinalReadOutControl are defeated Outlet is connect with the first data signal pin 1021, and the first data signal pin 1021 and the data-signal of the microprocessor draw Foot connects.The output end of output error status signal ErrorStatus is connect with the first error status signal pin 1051, and first Error status signal pin 1051 is connect with the second error status signal pin of the microprocessor.

Error correction tfi module 183, four input terminals, which are separately connected, reads the defeated of second read signal OER of the output of tfi module 163 Outlet, majority voting module 181 export three output ends of comparison result signal C12, C23, C31, and four output ends connect respectively Connect first with the input terminal of module 145, error correction address module 127 for input gating signal EAddrS1, EAddrS2, Three input terminals of EAddrS3, for receiving and processing the second read signal OER, the first comparison result signal C12, second comparing Consequential signal C23, third comparison result signal C31 export the 4th write signal WER2 of error-correction operation to first with module 145, The 7th gating signal EAddrS1, the 8th gating signal for gating error-correction operation address are exported to error correction address module 127 EAddrS2 and the 9th gating signal EAddrS3.

As shown in figure 24, it is preferable that majority voting module 181 latches three parts of backup numbers respectively by three latch According to, and three parts of Backup Datas are compared two-by-two by three comparators, obtain the first comparison result signal C12, Two comparison result signal C23, third comparison result signal C31, then respectively obtained by logic circuit operation and export most tables Certainly result data FinalDataOut, majority voting result gating signal FinalReadOutControl and error status signal ErrorStatus。

Specifically, inside majority voting module 181, the static random access memory passes through the second data signal pin The data-signal DataRead of 1022 inputs is connected respectively to the data input pin of three LD8CE latch, and the first zero propagation is read Signal OEL0 is connected respectively to the clear terminal (CLR) of three LD8CE latch, and the Enable Pin (GE) of three LD8CE latch connects High level indicates enabled；The input terminal G of second delay read signal OEL1 the first latch of connection LD1, the second delay read signal The failing edge of OEL1 latches DataRead data, exports the first latch data signal RData1, i.e. first Backup Data；The The failing edge of the input terminal G of three delay read signal OEL2 the second latch of connection LD2, third delay read signal OEL2 will DataRead data latch, and export the second latch data signal RData2, i.e. second Backup Data；4th delay read signal The input terminal G of OEL3 connection third latch LD3, the failing edge of the 4th delay read signal OEL3 latch DataRead data, Export third latch data signal RData3, i.e. third Backup Data.

First latch data signal of input terminal A input the first latch LD1 outputs of first comparator COMP12 RData1, the second latch data signal RData2 of input terminal B input the second latch LD2 outputs；Second comparator COMP23 Input terminal A input the second latch LD2 outputs the second latch data signal RData2, input terminal B inputs third latch The third latch data signal RData3 of LD3 outputs；The input terminal A input third latch LD3 of third comparator COMP31 is defeated The third latch data signal RData3 gone out, the first latch data signal of input terminal B input the first latch LD1 outputs RData1.First comparator COMP12, the second comparator COMP23 and third comparator COMP31 are 8 ratios of same type Compared with device, for being compared to two input datas, if comparison result is identical, 1 is exported, otherwise exports 0.

First comparator COMP12, the second comparator COMP23, third comparator COMP31 output end export respectively One comparison result signal C12, the second comparison result signal C23, third comparison result signal C31.

Meanwhile first latch data signal RData1 and the first comparison result signal C12 be respectively connected to 2 inputs and door Two input terminals of FData1, when the first latch data signal RData1 is equal to the second latch data signal RData2, FData1 exports the value of the first latch data signal RData1, and otherwise FData1 exports 0x00；

Second latch data signal RData2 and the second comparison result signal C23 are respectively connected to 2 inputs and door FData2 Two input terminals, when the second latch data signal RData2 be equal to third latch data signal RData3 when, FData2 output The value of second latch data signal RData2, otherwise FData2 export 0x00；

Third latch data signal RData3 and third comparison result signal C31 is respectively connected to 2 inputs and door FData3 Two input terminals, when third latch data signal RData3 be equal to the first latch data signal RData1 when, FData3 output The value of third latch data signal RData3, otherwise FData3 export 0x00.

Three 2 inputs and the output of door FData1, FData2 and FData3 are input to one 3 input or door, 3 input Or the output of door is majority voting result data FinalDataOut.

First comparator COMP12, the second comparator COMP23, third comparator COMP31 output end be respectively connected to 3 Three input terminals of input or door FStatus, when the first comparison result signal C12, the second comparison result signal C23, third ratio Compared with the value of at least one in consequential signal C31 three be 1 when, then it represents that at least there are two Backup Data it is identical, then 3 input or The output of door FStatus is 1, indicates correct result output；When the first comparison result signal C12, the second comparison result signal C23, third comparison result signal C31 three it is all 0 when, then 3 inputs or the output of door FStatus is 0, is indicated incorrect As a result it exports.

First zero propagation read signal OEL0, the second read signal OER and 3 inputs or the output of door FStatus input respectively The 3 input nand gate NAND3B1 for carrying 1 reverse input end and 2 non-inverting inputs to one, wherein the first zero propagation is read Signal OEL0 is connected to reverse input end, and the 3 input nand gate NAND3B1 exports majority voting result gating signal FinalReadOutControl。

First zero propagation read signal OEL0, the second read signal OER and 3 inputs or the output of door FStatus input respectively The 3 input nand gate NAND3B2 for carrying 2 reverse input ends and 1 non-inverting input to one, wherein the first zero propagation is read The inputs of signal OEL0 and 3 or the output of door FStatus are respectively connected to 2 reverse input ends, 3 input nand gate NAND3B2 output error status signals ErrorStatus.

The execution sequential of majority voting module 181 can be divided into three kinds of situations：Error-free received data, there are one Backup Datas Error and three Backup Datas are different.

Figure 25, Figure 26, Figure 27 are respectively the majority voting of the asynchronous static random access memory triplication redundancy controller of the present invention When module error-free received data, there are one when wrong data (by taking second Backup Data malfunctions as an example), three data it is different When time diagram.

As shown in figure 28, it is preferable that error correction tfi module 183 inputs the first comparison result letter respectively including three input terminals 3 input nand gates of number C12, the second comparison result signal C23, third comparison result signal C31, input terminal are separately connected described 3 inputs of three 3 input nand gate output ends and door and input terminal be separately connected the second read signal OER of input input terminal and 2 inputs or door of 3 input with the output end of door.

2 input or one reverse input end of door band and a non-inverting input, the second read signal OER are connected to this Reverse input end, output end export the 4th write signal WER2.

Respectively there are two reverse input end and a non-inverting inputs for band for three 3 input nand gates, wherein the 1st The non-inverting input of input nand gate inputs the second comparison result C23, and output end exports the 7th gating signal EAddrS1；The The non-inverting input of 23 input nand gates inputs third comparison result C31, and output end exports the 8th gating signal EAddrS2； The non-inverting input of 3rd 3 input nand gate inputs the first comparison result C12, and output end exports the 9th gating signal EAddrS3。

Figure 29 is the sequential signal of the error correction tfi module of the asynchronous static random access memory triplication redundancy controller of the present invention Figure (by taking the error of the second Backup Data as an example).

When the 4th write signal WER2 is low level, and the 7th gating signal EAddrS1 is low level, the first Backup Data goes out Mistake, error correction address module 127 will export the address of the first Backup Data；When the 4th write signal WER2 is low level, the 8th gating When signal EAddrS2 is low level, the second Backup Data error, error correction address module 127 will export the ground of the second Backup Data Location；When the 4th write signal WER2 is low level, and the 9th gating signal EAddrS3 is low level, the error of third Backup Data is entangled Wrong address module 127 will export the address of third Backup Data.

Preferably, the first input is equipped between the first data signal pin 1021 and the second data signal pin 1022 to buffer Device 191 and the first tristate output buffer 193 controlled with module 145 by first.Second data signal pin 1022 and majority It is equipped with the second input buffer 195 between the input terminal of voting module 181.The output majority voting result data Two output ends of FinalDataOut and majority voting result gating signal FinalReadOutControl and the first data letter It is equipped between number pin 1021 by the second ternary output of majority voting result gating signal FinalReadOutControl controls Buffer 197.

When second write signal WER is effective, the first tristate output buffer 193 exports institute to the second data signal pin 1022 State the data that microprocessor is inputted by the first data signal pin 1021 and the first input buffer 191.

When majority voting result gating signal FinalReadOutControl is effective, the second tristate output buffer 197 to First data signal pin 1021 exports majority voting result data FinalDataOut.

Preferably, the asynchronous static random access memory triplication redundancy controller further includes being selected with the piece of the microprocessor It first chip selection signal pin 1061 of signal pins connection and connect with the chip selection signal pin of the static random access memory Second chip selection signal pin 1062, the first chip selection signal pin 1061 are connect with the second chip selection signal pin 1062.

As shown in figure 30, when executing write operation using the asynchronous static random access memory triplication redundancy controller of the present invention, institute That states microprocessor writes that sequential is constant, and the asynchronous static random access memory triplication redundancy controller is by the one of the microprocessor Secondary write operation is converted into the write operation of three addresses, only need to change backup address successively.

When executing read operation using the asynchronous static random access memory triplication redundancy controller of the present invention, it is divided into inerrancy number According to, there are one Backup Data error and the different three kinds of situations of three Backup Datas.

As shown in figure 31, in the case of error-free received data, the reading sequential of the microprocessor is constant, described asynchronous random Read operation of the microprocessor is converted into the read operation of three backup address by static memory triplication redundancy controller, Then read three data are subjected to triplication redundancy processing, correct data is exported to the microprocessor.

As shown in figure 32, there are one wrong data, the reading sequential of the microprocessor is constant, described asynchronous Read operation of the microprocessor is converted into the reading of three backup address by static random access memory triplication redundancy controller Then read three data are carried out triplication redundancy processing by operation, correct data is exported to the microprocessor, and to asynchronous Static random access memory write-back correct data.

As shown in figure 33, in the case where three data are different, the reading sequential of the microprocessor is constant, described different Read operation of the microprocessor is converted into three backup address by step static random access memory triplication redundancy controller Then read three data are carried out triplication redundancy processing by read operation, since three data are different, can not export correct As a result, the asynchronous static random access memory triplication redundancy controller is returned by error status signal pin ErrorStatus One high level indicates error condition.

As shown in figure 34, inside the asynchronous static random access memory triplication redundancy controller, the write operation includes Following steps：

(1) external microprocessor starts write operation：The microprocessor inputs low electricity by the first write signal pin 1031 It puts down effective first write signal WEL and starts write operation, while the first data-signal is inputted by the first data signal pin 1021 DataL inputs the first address signal AddrL by the first address signal pin 1011, and reads to believe with read operation relevant first Number OEL is then high level.First address signal AddrL is calculated by address calculation module 121, it is standby to obtain three data The address in part area：AddrL, AddrL+Offset and AddrL+2Offset.At this point, three mould of asynchronous static random access memory The write address of redundant manipulator output is AddrL, that is, starts to write the first Backup Data.

(2) write signal delay 1 reaches：The address of the asynchronous static random access memory triplication redundancy controller output described at this time It will be switched to AddrL+Offset, that is, start to write the second Backup Data.

(3) write signal delay 2 reaches：The address of the asynchronous static random access memory triplication redundancy controller output described at this time It will be switched to AddrL+2Offset, that is, start to write third Backup Data.

(4) write signal delay 3 reaches：The address of the asynchronous static random access memory triplication redundancy controller output described at this time It will be switched to do-nothing operation address 0xFFFF, while the third write signal WER1 exported becomes high level, and indicate to stop write operation.

(5) write signal terminates：First write signal WEL becomes high level, and the write operation of external microprocessor terminates.

As shown in figure 35, inside the asynchronous static random access memory triplication redundancy controller, read operation inerrancy number According to when, the read operation includes the following steps：

(1) external microprocessor starts read operation：The microprocessor inputs low electricity by the first read signal pin 1041 It puts down effective first read signal OEL and starts read operation, while the first address signal is inputted by the first address signal pin 1011 AddrL, and be then high level with the relevant first write signal WEL of write operation.First address is believed by address calculation module 121 Number AddrL is calculated, and the address of three data backup areas is obtained：AddrL, AddrL+Offset and AddrL+2Offset.This When, the reading address of the asynchronous static random access memory triplication redundancy controller output is AddrL, that is, starts to read the first backup number According to.

(2) read signal delay 1 reaches：It is standby that the asynchronous static random access memory triplication redundancy controller described at this time latches first Part data, and the address of output will be switched to AddrL+Offset, that is, start to read the second Backup Data.

(3) read signal delay 2 reaches：It is standby that the asynchronous static random access memory triplication redundancy controller described at this time latches second Part data, and the address of output will be switched to AddrL+2Offset, that is, it opens

(4) read signal delay 3 reaches：It is standby that the asynchronous static random access memory triplication redundancy controller described at this time latches third Part data, and the address of output will be switched to do-nothing operation address 0xFFFF, while the second read signal OER exported becomes high electricity It is flat, it indicates to stop read operation.Since three Backup Datas read are identical, majority voting module 181 will export just at this time True result.

(5) read signal terminates：First read signal OEL of input becomes high level, and the read operation of external microprocessor terminates.

As shown in figure 36, inside the asynchronous static random access memory triplication redundancy controller, there are one wrong for read operation Accidentally when data, the read operation includes the following steps：

(3) read signal delay 2 reaches：It is standby that the asynchronous static random access memory triplication redundancy controller described at this time latches second Part data, and the address of output will be switched to AddrL+2Offset, that is, start to read third Backup Data.

(4) read signal delay 3 reaches：It is standby that the asynchronous static random access memory triplication redundancy controller described at this time latches third Part data, while the second read signal OER exported becomes high level, indicates to stop read operation.This sentences the second Backup Data and goes out For mistake, since the first Backup Data read is identical as third Backup Data, the error of the second Backup Data, majority voting at this time Module 181 will export correct result, and export the second backup again by error correction tfi module 183 and error correction address module 127 Address and correct result complete error-correction operation.

As shown in figure 37, inside the asynchronous static random access memory triplication redundancy controller, three data of read operation When different, the read operation includes the following steps：

(4) read signal delay 3 reaches：It is standby that the asynchronous static random access memory triplication redundancy controller described at this time latches third Part data, while the second read signal OER exported becomes high level, indicates to stop read operation.Due to the first backup number read Different according to, the second Backup Data and third Backup Data, majority voting module 181 will be unable to output correct result, also without Method realizes error-correction operation by error correction tfi module 183 and error correction address module 127, and the address exported at this time will be switched to empty behaviour Make address 0xFFFF, and high level signal is exported by error status signal pin ErrorStatus and indicates that corrupt data, nothing have Imitate data output.

In order to verify the feasibility of the present invention program, the present inventor is in Xilinx Spartan3 Series FPGAs Carry out Proof-Of Principle.First, in Xilinx ISE Integrated Development Environment, each mould of this programme is inputted using schematic diagram mode Block and overall structure.Then corresponding emulation testing input file is write, above-mentioned various types of operations are emulated successively.

It is compared by internal signal sequence diagram Figure 34-Figure 37 with aforementioned the present invention program process analysis, emulation knot The sequential of fruit and the sequential of principle analysis are completely the same, to demonstrate the correctness of the present invention program.

In addition, after above-mentioned principle of simulation is verified, a dedicated test circuit has also been devised to the present invention in inventor Technical solution carried out actual hardware testing.Test circuit is random into line asynchronous using XilinxSpartan3 Series FPGAs The design of static memory triplication redundancy controller selects the asynchronous static random access memory of dual-port, AT89LS52 microcontrollers to borrow Asynchronous static random access memory triplication redundancy controller is helped to carry out conventional read-write behaviour to the asynchronous static random access memory of dual-port Make, test system carries out single-particle inversion simulated injection sum number by PSoC chips to the asynchronous static random access memory of dual-port According to inspection readback.It is verified by hardware testing, shows the asynchronous static random access memory triplication redundancy designed by the present invention program Controller is feasible and reliable.

In conclusion asynchronous static random access memory triplication redundancy controller provided by the invention is arranged in system microprocessor Bridge is used as between device and asynchronous static random access memory, by microprocessor to the write/read operation of asynchronous static random access memory It is automatically converted to triplication redundancy and two from three majority voting time sequential routine, realizes that triplication redundancy is fault-tolerant and automatically processes, to take For triplication redundancy is handled in system software, the burden of system software is alleviated, while soft without changing systematic microprocessor Part structure, the complexity for reducing Design of System Software while, have ensured reliability.In conclusion the present invention is asynchronous random quiet State memory triplication redundancy controller have many advantages, such as it is simple in structure, compatible it is strong, applied widely, reliability is high.

Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although Present invention has been described in detail with reference to the aforementioned embodiments, it will be understood by those of ordinary skill in the art that：It still may be used With technical scheme described in the above embodiments is modified or equivalent replacement of some of the technical features； And these modifications or replacements, various embodiments of the present invention technical solution that it does not separate the essence of the corresponding technical solution spirit and Range.

Claims

1. a kind of asynchronous static random access memory triplication redundancy controller, which is characterized in that including：

Address signal processing unit is separately connected the address signal pin of microprocessor and static random access memory, for receiving And handle the first address signal of microprocessor output, to static random access memory output comprising write operation address, Second address signal of read operation address or error-correction operation address；

Write signal processing unit, is separately connected the write signal pin of the microprocessor and the static random access memory, and with Described address signal processing unit connects, the first write signal for receiving and processing microprocessor output, to it is described with Machine static memory exports the second write signal, is exported to described address signal processing unit for gating the write operation address Gating signal；

Read signal processing unit, is separately connected the read signal pin of the microprocessor and the static random access memory, and with Described address signal processing unit connects, the first read signal for receiving and processing microprocessor output, to it is described with Machine static memory exports the second read signal, is exported to described address signal processing unit for gating the read operation address Gating signal；

Triplication redundancy error correction unit is separately connected data signal pin, error status signal pin and the institute of the microprocessor State the data signal pin of static random access memory, and respectively with the read signal processing unit, the write signal processing unit It is connected with described address signal processing unit, for carrying out triplication redundancy comparison to three parts of Backup Datas of input, to described micro- Processor output error status signal and comparison result data entangle the Backup Data of static random access memory storage It is wrong；

The write signal processing unit includes：

Write signal time delay module, input terminal connect the first write signal pin, and four output ends export the first zero propagation and write letter respectively Number, second delay write signal, third delay write signal and the 4th delay write signal, for will the first write signal multistage delay Output；The first write signal pin is connect with the write signal pin of the microprocessor；

Tfi module is write, four input terminals are separately connected four output ends of the write signal time delay module, four output ends point Not Shu Chu third write signal, the first gating signal, the second gating signal and third gating signal, for calculating and exporting write operation Third write signal and strobe write operation address gating signal；

First and module, tfi module and the triplication redundancy error correction unit, output end connection second are write described in input terminal connection Write signal pin is specifically included in the third write signal of write operation sequential export write operation for exporting second write signal, With the 4th write signal in error-correction operation sequential export error-correction operation；The second write signal pin is stored with the random static The write signal pin of device connects.

2. asynchronous static random access memory triplication redundancy controller according to claim 1, which is characterized in that described to write letter Number time delay module includes that the first delay submodule, the second delay submodule and third are delayed submodule；First write signal is straight It connects to obtain and export the first zero propagation write signal, is delayed to obtain and export described second by the first delay submodule Be delayed write signal, passes sequentially through the first delay submodule and the second delay submodule is delayed to obtain and export described the Three delay write signals pass sequentially through the first delay submodule, the second delay submodule and third delay submodule Block is delayed to obtain and export the 4th delay write signal.

3. asynchronous static random access memory triplication redundancy controller according to claim 1, which is characterized in that described when writing Sequence module includes three and writes 4 input nand gates and three input terminals that four input terminals of tfi module are connect with described respectively 3 inputs being connect respectively with the output end of three 4 input nand gates and door；The output result of three 4 input nand gates is respectively First gating signal, second gating signal and the third gating signal, 3 input and the output result of door are The third write signal；

Wherein, there are one reverse input end and three non-inverting inputs, reverse input end to input institute for the one 4 input nand gate band State the first zero propagation write signal；There are two reverse input end and two non-inverting inputs for 2nd 4 input nand gate band, reversed defeated Enter end and inputs the first zero propagation write signal and the second delay write signal；There are three reversed for 3rd 4 input nand gate band Input terminal and a non-inverting input, reverse input end inputs the first zero propagation write signal, second delay is write letter Number and the third be delayed write signal.

4. asynchronous static random access memory triplication redundancy controller according to claim 1, which is characterized in that the reading letter Number processing unit includes：

Read signal time delay module, input terminal connect the first read signal pin, and four output ends export the first zero propagation and read letter respectively Number, second delay read signal, third delay read signal and the 4th delay read signal, for will the first read signal multistage delay Output；The first read signal pin is connect with the read signal pin of the microprocessor；

Tfi module is read, four input terminals are separately connected four output ends of the read signal time delay module, four output ends point Second read signal, the 4th gating signal, the 5th gating signal and the 6th gating signal are not exported, for calculating and exporting reading The gating signal of the second read signal and gating read operation address of operation；The output end of the second read signal of the output and second is read Signal pins connect, and the second read signal pin is connect with the read signal pin of the static random access memory.

5. asynchronous static random access memory triplication redundancy controller according to claim 4, which is characterized in that the reading letter Number time delay module includes the 4th delay submodule, the 5th delay submodule and the 6th delay submodule；First read signal is straight It connects to obtain and export the first zero propagation read signal, is delayed to obtain and export described second by the 4th delay submodule Be delayed read signal, passes sequentially through the 4th delay submodule and the 5th delay submodule is delayed to obtain and export described the Three delay read signals pass sequentially through the 4th delay submodule, the 5th delay submodule and the 6th delay submodule Block is delayed to obtain and export the 4th delay read signal.

6. asynchronous static random access memory triplication redundancy controller according to claim 4, which is characterized in that when the reading Sequence module includes three 4 input nand gates being connect respectively with described reading four input terminals of tfi module and three input terminals 3 inputs being connect respectively with the output end of three 4 input nand gates and door；The output result of three 4 input nand gates is respectively 4th gating signal, the 5th gating signal and the 6th gating signal, 3 input and the output result of door are Second read signal；

Wherein, there are one reverse input end and three non-inverting inputs, reverse input end to input institute for the 4th 4 input nand gate band State the first zero propagation read signal；There are two reverse input end and two non-inverting inputs for 5th 4 input nand gate band, reversed defeated Enter end and inputs the first zero propagation read signal and the second delay read signal respectively；There are three 6th 4 input nand gate bands Reverse input end and a non-inverting input, reverse input end input the first zero propagation read signal, described second respectively The read signal that is delayed and third delay read signal.

7. asynchronous static random access memory triplication redundancy controller according to claim 4, which is characterized in that described address Signal processing unit includes：

Address calculation module, input terminal connect the first address signal pin, and three output ends export the first backup address letter respectively Number, the second backup address signal and third backup address signal, for calculating and exporting corresponding to first address signal Three backup address；The first address signal pin is connect with the address signal pin of the microprocessor；

Write address module, six input terminals are separately connected three output ends for writing tfi module output gating signal and described Three output ends of address calculation module, output end export write operation address, for receive and process first gating signal, Second gating signal, the first backup address signal of the third gating signal and write operation sequential, described second Backup address signal, the third backup address signal, export the write operation address；

Read address module, six input terminals are separately connected reading tfi module output three output ends of gating signal and described Three output ends of address calculation module, output end export read operation address, for receive and process the 4th gating signal, 5th gating signal, the first backup address signal of the 6th gating signal and read operation sequential, described second Backup address signal, the third backup address signal, export the read operation address；

Error correction address module, seven input terminals are separately connected the output end, described that the reading tfi module exports the second read signal Triplication redundancy error correction unit exports three output ends of three output ends and described address computing module of gating signal, output end Error-correction operation address is exported, the error correction for receiving and processing second read signal, triplication redundancy error correction unit output The first backup address signal of operation address gating signal and error-correction operation sequential, the second backup address signal, institute Third backup address signal is stated, the error-correction operation address is exported；

Second and module, three input terminals are separately connected the output end of the write address module, the output for reading address module It holds, the output end of the error correction address module, output end connects the second address signal pin, in write operation sequential export institute Write operation address is stated, the read operation address described in read operation sequential export, the error-correction operation described in error-correction operation sequential export Location；The second address signal pin is connect with the address signal pin of the static random access memory.

8. asynchronous static random access memory triplication redundancy controller according to claim 7, which is characterized in that described address Computing module point No. three counting circuits carry out parallel computation processing, the first address signal difference to first address signal It directly obtained by buffer and exports the first backup address signal, obtained simultaneously by first adder and offset addition The second backup address signal is exported, is obtained by second adder and twice of offset addition and exports the third Backup address signal；The offset is calculated by the address bit wide of the asynchronous static random access memory.

9. asynchronous static random access memory triplication redundancy controller according to claim 8, which is characterized in that described asynchronous The address bit wide of static random access memory is N, then the calculation of the offset Offset is：

10. asynchronous static random access memory triplication redundancy controller according to claim 7, which is characterized in that described to write Address module is gated by three 2 inputs or door and first gating signal, second gating signal, the third respectively Signal exports the first backup address signal, the second backup address signal, the third backup address signal Control, and merge three 2 inputs or the output of door with door by one 3 input, when to realize continuous output write operation The first backup address signal, the second backup address signal and the third backup address signal of sequence.

11. asynchronous static random access memory triplication redundancy controller according to claim 7, which is characterized in that the reading Address module passes through three 2 inputs or door and the 4th gating signal, the 5th gating signal, the 6th gating respectively Signal exports the first backup address signal, the second backup address signal, the third backup address signal Control, and merge three 2 inputs or the output of door with door by one 3 input, when to realize continuous output read operation The first backup address signal, the second backup address signal and the third backup address signal of sequence.

12. asynchronous static random access memory triplication redundancy controller according to claim 7, which is characterized in that described to entangle Wrong address module includes three 2 inputs or door, 3 inputs and the 10th input of door and one comprising a reverse input end Or door, respectively by described three 2 inputs or door and the 7th gating signal, the 8th gating signal, the 9th gating signal to described First backup address signal, the second backup address signal, the third backup address signal carry out output control, and described three The output end of a 2 input or door is separately connected 3 input and the input terminal of door, the 10th input or door it is non-return defeated Enter the output end of end connection 3 input and door, the input terminal of reverse input end connection the second read signal of input, output end output The error-correction operation address.

13. asynchronous static random access memory triplication redundancy controller according to claim 7, which is characterized in that described three Mould redundant correcting unit includes：

Majority voting module, six input terminals are separately connected the output end, described that the reading tfi module exports the second read signal Four output ends of read signal time delay module, the second data signal pin, six output ends export the first comparison result letter respectively Number, the second comparison result signal, third comparison result signal, majority voting result data, majority voting result gating signal and Error status signal, for carrying out triplication redundancy comparison to the three parts of Backup Datas inputted by second data signal pin And comparison result is exported, to the microprocessor output error status signal and comparison result data；First comparison result Signal, the second comparison result signal, third comparison result signal are three parts of Backup Datas result of the comparison signal two-by-two；Institute The second data signal pin is stated to connect with the data signal pin of the static random access memory；Export the majority voting result Two output ends of data and the majority voting result gating signal are connect with the first data signal pin, first data Signal pins are connect with the data signal pin of the microprocessor；Export the output end and the first mistake of the error status signal Accidentally the connection of status signal pin, the second error status signal of the first error status signal pin and the microprocessor draw Foot connects；

Error correction tfi module, four input terminals are separately connected the output end, described that the reading tfi module exports the second read signal Majority voting module exports three output ends of comparison result signal, and it is defeated with module that four output ends are separately connected described first Enter three input terminals of end, the error correction address module for inputting gating signal, letter is read for receiving and processing described second Number, the first comparison result signal, the second comparison result signal, the third comparison result signal, to described first The 4th write signal that error-correction operation is exported with module, to error correction address module output for gating error-correction operation address the Seven gating signals, the 8th gating signal and the 9th gating signal.

14. asynchronous static random access memory triplication redundancy controller according to claim 13, which is characterized in that described more Number voting module latches three parts of Backup Datas respectively by three latch, and standby to described three parts by three comparators Part data are compared two-by-two, obtain the first comparison result signal, the second comparison result signal, third comparison result letter Number, then the majority voting result data, majority voting result gating are respectively obtained and exported by logic circuit operation Signal and the error status signal.

15. asynchronous static random access memory triplication redundancy controller according to claim 13, which is characterized in that described to entangle Wrong tfi module inputs the first comparison result signal, the second comparison result signal, third ratio respectively including three input terminals Compared with 3 input nand gates of consequential signal, input terminal is separately connected 3 inputs and the door of three 3 input nand gate output ends, and input End is separately connected 2 inputs or door of the input terminal and 3 input of the second read signal of input with the output end of door；

2 input or gate output terminal export the 4th write signal；

Respectively there are two reverse input end and a non-inverting inputs for band for three 3 input nand gates, wherein the one 3 input with it is non- The non-inverting input of door inputs second comparison result, and output end exports the 7th gating signal, the 2nd 3 input with it is non- The non-inverting input of door inputs the third comparison result, and output end exports the 8th gating signal, the 3rd 3 input with it is non- The non-inverting input of door inputs first comparison result, and output end exports the 9th gating signal.

16. asynchronous static random access memory triplication redundancy controller according to claim 13, which is characterized in that described The first input buffer is equipped between one data signal pin and second data signal pin and by described first and module First tristate output buffer of control；It is set between second data signal pin and the input terminal of the majority voting module There is the second input buffer；Export the majority voting result data and the majority voting result gating signal two The second tri-state controlled by the majority voting result gating signal is equipped between output end and first data signal pin Output buffer；

When second write signal is effective, described in first tristate output buffer is exported to second data signal pin The data that microprocessor is inputted by first data signal pin and first input buffer；

When the majority voting result gating signal is effective, second tristate output buffer draws to first data-signal Foot exports the majority voting result data.

17. according to the asynchronous static random access memory triplication redundancy controller of claim 1-16 any one of them, feature exists In further including the first chip selection signal pin being connect with the chip selection signal pin of the microprocessor and deposited with the random static Second chip selection signal pin of the chip selection signal pin connection of reservoir, the first chip selection signal pin are believed with described second choosing The connection of number pin.