CN103500125A - Anti-radiation data processing system and method based on FPGA - Google Patents
Anti-radiation data processing system and method based on FPGA Download PDFInfo
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Abstract
The invention discloses an anti-radiation data processing system and method based on an FPGA. The data processing system comprises a data processing card applicable to severe environments such as radiation environments and comprising the double-port RAM commercial SPAM structure FPGA. The data processing card comprises two pieces of anti-radiation antifuse Aeroflex UT6235FPGAs, two pieces of incomplete anti-radiation Xilinx Virtex-5FX130T FPGAs and relevant storages, interfaces and other peripheral chips. Each piece of Xilinx Virtex-5FX130T FPGA comprises three parts, namely a control and processing part, a first path data processing module used for processing input data and storing a data processing result into a first part of a double-port RAM and a second path data processing module identical with the first path data processing module and identically processing the same input data. A data processing result is stored into a second part of the double-port RAM. A control and processing module compares the processing results of the two path processing modules. If the results are identical, the processing results are stored into a designated storage and if the results are not identical, processing is repeated.
Description
Technical field:
The present invention relates to a kind of data based on FPGA and process board, particularly a kind of radiation-resistant high-performance data disposal system and method based on FPGA.
Background technology:
Along with the development of novel high resolving power and active remote sensing instrument, in application such as spaceborne or airborne remote sensing, need the high-performance data disposal system to obtain data to instrument and carry out processing in real time or closely in real time to reduce storage or down-transmitting data amount.
In application like that, working environment is comparatively severe, has radiation such as high energy particle, cosmic rays, Solar Soft X-Ray, and this can cause that electron device lost efficacy and damage.Therefore need to strengthen the capability of resistance to radiation of electron device to alleviate or to prevent the generation of this event of class.Radiation refers to the damage that the mechanism such as ionization that cause as particles such as the electromagnetic wave such as X ray, Ka code ray and neutron, electronics, alpha particles produce disposal system.
Other electron device radiotolerance of three kinds of levels is arranged at present; The first is that electron device does not have safeguard measure, when electron device is used in rugged surroundings experience various possible can recovery type and damage type mistake; The second refers to conventional radioresistance tolerance limit, be the radiation that exists in environment during lower than this level, the impact of the not raying of work of device, comprise that damage type mistake does not occur the device that makes to be operated in rugged surroundings by design, but can recovery type mistake, as bit flipping still likely occurs; The third refers to the device radioresistance, and while comprising for severe working environment, device does not occur can recovery type and damage type mistake.
Bit flipping is that a kind of state of occurring in memory device or register changes, and for example becomes 0 or become 1 from 0 from 1, and it is a kind of of single-particle inversion.It can not produce fatal impact to device, but needs to proofread and correct to prevent wrong transmission in calculating etc. is processed.Circuit upset is grave error more, usually need outage and restart, or device is reset.
The processing power of radioresistance device is lower than existing commercial non-complete radioresistance processing apparatus.Non-complete radioresistance device refers to possess certain radioresistance tolerance limit, and when environmental radiation is lower than this threshold value, device can work.The processing power of radioresistance device, such as, may be than low one to two order of magnitude of existing commercial non-complete radioresistance device.
In spaceborne or other rugged surroundings, use commercialization or non-aerospace level device, for ever-increasing handling property requirement in meeting space mission, very important meaning is arranged, because the processing power of existing space flight level processor part is too low.
Therefore in existing or new data handling system, use existing commercial devices to possess very large advantage, it does not need to redesign new processing apparatus, can use existing standard interface and agreement, facilitates system extension.Based on the SRAM structure FPGA, such as Xilinx Virtex-5Q, possessing very high data-handling capacity and dirigibility, is the desirable high-performance data processing platform of a class, key that to be it apply in the rugged surroundings such as spaceborne that capability of resistance to radiation how to realize such device strengthens.
Summary of the invention:
For above deficiency, the present invention has provided a kind of radioresistance high-performance data based on FPGA and has processed board and capability of resistance to radiation Enhancement Method, adopt embedded PowerPC processor and fpga logic gate array to build the software-hardware synergism framework, the technical matters of the high-performance that solution builds based on commercial SRAM structure FPGA, low-power consumption, compact radioresistance data handling system.
Technical solution of the present invention is:
The high-performance built based on commercial SRAM structure FPGA, the compact radioresistance data handling system of low-power consumption, realize that by structural design and software approach its capability of resistance to radiation strengthens, so that the reliability that approaches radioresistance rank processing apparatus to be provided.Its feature part is:
1. data are processed board and are comprised two anti-fuse-type FPGA of radioresistance, two 32K PROM and 32K SRAM outer extension memory; Two reconfigurable non-complete radioresistance FPGA and corresponding configuration Flash; Memory device comprises that two 512MB have the SDRAM that the Flash storer of error detecting and error correcting function, two 512MB have error detecting and error correcting function; Peripheral Interface comprises PCIE, RS-422, Ethernet interface, SATA, Multi-Gbps Transceivers, I2C, CAN and GPIO;
The anti-fuse-type FPGA of described two radioresistances adopts Aeroflex UT6325FPGA.
Described two reconfigurable non-complete radioresistance FPGA adopt Xilinx Virtex-5Q FX130T FPGA, and corresponding configuration Flash is 32MB Xilinx configuration Flash;
2. the notebook data disposal system is responsible for inner embedded PowerPC processor and the fpga logic gate array structure software-hardware synergism data processing framework of adopting of Xilinx FPGA that data are processed.For algorithm structure fix, operand is large, the processing of front end data at a high speed, uses the fpga logic gate array to complete; For the algorithm flow complexity, the processing of the Back end data of operand less, used embedded PowerPC processor to complete, to improve the data-handling capacity of native system.
3. data handling system capability of resistance to radiation of the present invention strengthens by two steps realizations: the first step provides capability of resistance to radiation to strengthen by flow chart of data processing design.At first be the system logic design optimization, then the complete radioresistance FPGA of right and wrong comprises three difference in functionality modules: control and processing module compare for control, command decode and the data processed result that inputs or outputs Data Control, data processing and storage; First via data processing module, process the input data, sets up first group of output deal with data, and data processed result is deposited in to first part of dual port RAM; The data processing module that the second tunnel is identical with the first via, process same input data, sets up second group of output deal with data, and data processed result is deposited in to the second part of dual port RAM; Then control and processing module compare the output deal with data of the first via and the second circuit-switched data processing module.If these two groups of data consistents, process the output deal with data of output data as this sheet FPGA using first group or second group.Also comprise second and the identical non-complete radioresistance FPGA of first, same input data are processed, for setting up the 3rd group and the 4th group of output deal with data, deposit respectively first and the second part of second dual port RAM in, the control of second FPGA and processing module be the 3rd group and the 4th group of output deal with data relatively, if these two groups of data consistents, process the output deal with data of output data as second FPGA using the 3rd group or the 4th group.Then compare the output data of first and second non-complete radioresistance FPGA, to detect the mistake produced in data or data handling procedure, this output data comparison is completed by anti-fuse-type radioresistance type FPGA.When making a mistake, again data are processed.Further method also comprises the output data from first and second non-complete radioresistance FPGA, under pass the homogeneous data disposal system on ，Yu ground, ground back the output data compare.In addition, use anti-fuse-type radioresistance FPGA monitor non-complete radioresistance FPGA data handling procedure and check mistake, can remove most or all upset mistakes.Second step, used software approach to be detected the mistake that may exist in the data processing procedure and proofread and correct to realize that capability of resistance to radiation strengthens.Disturb in the non-complete radioresistance processor data processing procedures of methods detection such as signs the mistakes such as bit flipping because of introducings such as radiation by output result detections, tri-state redundancy, house dog, data, and this type of mistake is suitably proofreaied and correct.When gross error occurs, carry out the relevant logic of restarting.
The present invention has the following advantages:
1. commercial devices has the processing power far above aerospace level radioresistance device.What the present invention proposed builds for there being the data handling system of the rugged surroundings such as radiation based on commercial devices, realize that by design and software approach capability of resistance to radiation strengthens, can obtain very high data-handling capacity, and without the special-purpose radioresistance type processing apparatus of redesign, can effectively reduce costs, thereby guarantee to use existing business level processing apparatus, memory device and other electronic devices and components in space mission.
2. possess based on the SRAM structure FPGA ability of reshuffling, can realize difference in functionality by reshuffling, and without the change hardware design.
3. the data handling system based on FPGA possesses very high data-handling capacity and application flexibility.
4. the data handling system that comprises the Xilinx FPGA structure of PowerPC possesses the software-hardware synergism framework, can conveniently adopt fpga logic gate array or embedded PowerPC to realize difference in functionality.
The accompanying drawing explanation:
Accompanying drawing 1 data are processed the board block diagram.
Accompanying drawing 2Xilinx FPGA internal module block diagram.
The TMR module frame chart that accompanying drawing 3Xilinx FPGA comprises.
Accompanying drawing 4TMR module workflow diagram.
Embodiment:
In such as application such as spaceflight apparatus data processing, so high unlike security system to the requirement of reliability, therefore can abandon partial reliability and improve to exchange processing power for.Use commercial non-complete radioresistance processing apparatus, even some non-damage mistakes occur, such as bit flipping, can be proofreaied and correct by correlation technique, have superiority.The technology related in the present invention realizes the enhancing of commercial non-complete radioresistance processing apparatus capability of resistance to radiation by design and software mode.
A lot of methods can realize detection and the correction of this type of mistake, but their application is limited by calculated amount.Realize that based on treatment scheme design and software approach capability of resistance to radiation strengthens the data that can guarantee the data handling system processing and can not have very serious mistake, and can obtain the key message of raw data.
The disposal system built based on prior art can be integrated on an instrument or platform worked in rugged surroundings such as having radiation, in order to show and to verify that capability of resistance to radiation enhancing, error recovery and commercial devices based on design and software approach are applied to other related correlation techniques of space mission.
The present invention proposes a kind of disposal system, the dirigibility, the checking that can be used for improving system strengthen the effect of capability of resistance to radiation based on design and software approach, and with the communication interface of the outside platform that is operated in rugged surroundings.
The disposal system built based on prior art as shown in Figure 1.This processing board comprises two reconfigurable FPGA, for example Xilinx Virtex-5FX130T FPGAs.Xilinx FPGAs is not aerospace level device, and it is to possess certain radiotolerance rather than fully radiation-resistant, and when environmental radiation surpasses radiotolerance, this device can't be worked.Every Xilinx FPGAs comprises two IBM PowerPC processors and the soft core of 32-bits RISC, as shown in Figure 2.Xilinx FPGAs adopts mode back-to-back to install, so that all or part of Share interlinkage device is so that the space minimum that installation takies is calculated usefulness to improve.Utilize prior art, rationally divide into groups by the shared mouth that inputs or outputs of inciting somebody to action the device that mode is installed back-to-back, use the assembly that mode is installed back-to-back can carry out same instructions or this part is configured.To the capability of resistance to radiation based on software approach, enhancing is of great use for this, because these need to be two parts independently, for example, two Xilinx FPGAs, carry out identical code, instruction or task, and the collision flag position that will export deal with data compares to detect mistake and repeats computing.One back-to-back integrated circuit board configuration allow very high component density, therefore with traditional integrated circuit board, compare, can reduce required physical space.
What should be noted that is a bit that Xilinx FPGAs and other disposal system assembly there is no need to use fully installation back-to-back, and shares all connectors.In fact, shared signal, in some cases, can reduce signal speed.Under specific circumstances, the signal of SDRAM and Flash storer does not share, because the shared design on board level of this type of signal is very complicated.
Each Xilinx FPGA has relevant storer and interface, comprises two 512MB SDRAM that possess error detecting and error correcting function.The control of Xilinx FPGAs and processing module are used 512MB SDRAM storer.
This processing board also comprises the Aeroflex UT6325FPGA of two anti-fuse-type one-off programming of radioresistance.Two Aeroflex radioresistance processors are for the treatment of system task management and sequential control.The Aeroflex processor connects by bus, uses installation method back-to-back, so that all or part of common connector calculates usefulness to reduce required space and the scale of installing to optimize.An Aeroflex processor can be used as master control FPGA, and another Aeroflex processor can be used as from FPGA, and above two Aeroflex FPGA combination can be used for monitoring non-complete radioresistance FPGA.It may be noted that a bit, determine the number of the anti-fuse-type FPGAs of required radioresistance according to system Processing tasks and single non-complete radioresistance FPGA processing power.In disposal system of the present invention, one of them Aeroflex FPGA comprises 8 radioresistance microcontrollers.8 8-digit microcontroller major functions comprise that the PowerPC processor detects, utilizes the configuration file configuration xilinx FPGA of storage and restarts the PowerPC processor.Aeroflex FPGA also can be used as and sees the doorway circuit, regularly receives the house dog packet from the PowerPC processor, if do not receive at the appointed time the house dog packet, restarts the PowerPC processor of house dog data-bag lost.Consistent with application-specific, Aeroflex FPGA also is responsible for checking the output data of comparison Xilinx FPGA.The deposit data of all Xilinx FPGAs is in corresponding 512MB Flash storer, so the data that have 4 road FPGA simultaneously to export in 512MB Flash.
Disposal system also comprises two 512MB Flash storeies that possess error detecting and error correcting function, for the configuration file of depositing Xilinx and Aeroflex FPGA, the data that Xilinx FPGAs produces and uses, for example, telemetry and application file.
Processor board as shown in Figure 1 also comprises a radiation-resistant 32K PROM and 32K SRAM.PROM deposits control and the Processing tasks file of 8 8-digit microcontrollers.During work, the Aeroflex processor obtains from PROM to be controlled and Processing tasks, and carries out this task in 32K SRAM.Then the Aeroflex processor checks 512MB Flash storer, looks into to see if there is more new task and need to carry out.
Disposable plates board based on prior art small-sized, for example be less than 4'' * 4'' * 7''.The power consumption of processing board is 7-25W, and storage capacity is: 1GB has the SDRAM of EDC error detection and correction ability, and 1GB has the Flash of EDC error detection and correction ability, 32K SRAM and 32K PROM.
The disposal system built based on prior art can be connected with instrument or platform easily, by programming, carries out particular task.And but the disposal system based on Xilinx FPGA is field-programmable and overprogram, thereby there is very high application flexibility.
According to prior art, can obtain field-programmable or configurable radioresistance disposal system by the anti-fuse-type FPGA of the radioresistance that replaces some type.In addition, can use different capability of resistance to radiation Enhancement Method to realize detection and the correction to single-particle inversions such as bit flipping, bad picture dot mistake, to avoid introducing mistake by radiation.
The capability of resistance to radiation the present invention relates to strengthens and can complete by two steps: the first step provides capability of resistance to radiation to strengthen by flow chart of data processing design; Second step, used software approach to be detected the mistake that may exist in the data processing procedure and proofread and correct to realize that capability of resistance to radiation strengthens.Below above two steps are described in detail.
(1) capability of resistance to radiation based on method for designing strengthens
The Xilinx FPGA structured flowchart of data handling system of the present invention, as shown in Figure 2, every XilinxFPGA can be divided into three modules by function: control and processing module; First via data processing module; The data processing module that the second tunnel is identical with the first via; For same input data are carried out to the two-way processing, provide first group and second group of output deal with data.Second and the identical Xilinx FPGA of first, to same input data, provide Third Road He tetra-tunnels output deal with data.Bing Duige road output deal with data compares, to find contingent mistake.The dual port RAM that Xilinx FPGA comprises allows the control of Xilinx FPGA and the health status of the real-time Check processing module of processing module, because processing module writes the data of dual port RAM and can compare with control and the processing unit of Xilinx FPGA, because dual port RAM allows disparate modules it to be carried out to read-write operation simultaneously.
In block diagram as shown in Figure 2, in monolithic Xilinx FPGA, the PowerPC processor that is designated Main CDH PPC_0 is carried out control and processing capacity.Another PowerPC processor that is denoted as Spare PPC_1 forms first via data processing module, processes the input data, and the deal with data of output is delivered to and controlled and processing module.The 3rd processor, the soft core risc processor that is denoted as the 32-bits of MicroBlaze forms the second circuit-switched data processing module, carries out the data identical with Spare PPC_1 and processes, and its result is also sent into and is controlled and processing module.The two paths of data processing module, all comprise the RAM that a PowerPC processor, xilinx FPGA provide, for example block RAM, a digital dock manager (DCM), corresponding logic gate array.The digital dock manager of two paths of data processing module is monitored by GPIO by control and processing module, working properly to guarantee data processing module.If necessary, but GPIO combine digital timer manager restart.
The output deal with data of every circuit-switched data processing module can be delivered to and be controlled and processing module by each the self-corresponding CMD_TLM BRAMs shown in accompanying drawing 2, and CMD_TLM BRAMs also can be used for the order of control and processing module is delivered to data processing module.Each processor, comprise that soft core risc processor has the local bus of oneself (PLB) for data stream transmitting.
Control & Processing module comprises a PowerPC processor, a digital dock manager (DCM), is connected to the root BRAM for program file and data storage of the 512MB SDRAM that processes board, one provides the URAT be connected with outside platform by Aeroflex FPGA, and a USRT.When controlling and after processing module restarts the PowerPC processor, the configuration file read in the root BRAM of control and processing module completes initialization, then by USRT, with Aeroflex FPGA, starts to communicate by letter.Control and processing module can, for example, send a command to SDRAM and send output deal with data from all data processing modules to SDRAM.
(2) capability of resistance to radiation based on software mode strengthens
In different application, can utilize one or more detection modes, land station for example, detected the output deal with data of Xilinx FPGA.It is necessary carrying out such detection, because realize that based on design and software mode dirigibility and reliability that capability of resistance to radiation strengthens need to be monitored.Replace or extra detection means also comprises in land station, having same processing board to be processed identical data, the data after comparison process; Perhaps radioresistance Aeroflex FPGA in-orbit carries out same treatment, with Xilinx FPGA output data, compares.In application-specific, Aeroflex FPGA can be at data storing or pass down before detection and reduce error in data.
As shown in Figure 2, each Xilinx FPGA comprises a TMR(tri-state redundancy) watch-dog.The TMR technology alleviates a kind of common technology of single-particle inversion while being the FPGA severe environment applications, can in different FPGA, configure the TMR module.In attached system shown in Figure 1, each Xilinx FPGA all comprises the TMR module, and oneself the configuration file of reading back is disturbed to prevent configuration file.
A kind of Xilinx FPGA TMR monitor module as shown in Figure 3.TMR watch-dog logic can read the data of three tunnels through same treatment, for example, module 1, module 2 and module 3, each means a configuration file, and is voted based on this three circuit-switched data.In application-specific, TMR monitor module real time execution, constantly checked data, to find the mistake that may exist.
TMR monitor module workflow diagram as shown in Figure 4.After powering on, Aeroflex FPGA microcontroller utilizes configuration file to be configured Xilinx FPGA.Once Xilinx FPGA has configured, the TMR monitor module is started working.The TMR monitor module configures mouthful (ICAP) at first internally, see accompanying drawing 3, read in first configuration frame, frame error-correcting code (FRAME ECC) register completes the execution of this frame, if mistake do not detected, the TMR monitor module checks whether this frame is last configuration file frame.If this frame is not last frame, reads the next frame configuration file, and carry out and once read frame error recovery Code memory.If this frame is last frame, returns and read configuration file, and carry out this circulation continuously.
If find mistake in frame error-correcting code register read process, if detect single bit flipping mistake, report and proofread and correct this mistake, this flow process can be determined whether last frame carry out respective handling of this frame.If detect dibit upset mistake, report this mistake, flow process is determined whether last frame carry out respective handling of this frame.Based on prior art, single bit flipping mistake can be corrected, and the bit flipping mistake of two can not be proofreaied and correct.Bit flipping mistake more than two can not be detected and proofread and correct.The bit flipping detected can be used the Local Gravity And configuring technical to be proofreaied and correct.
Correlation technique of the present invention can effectively be removed 95% the radiation relevant error produced when non-complete radioresistance FPGA is applied to rugged surroundings, particularly simple grain subnumber upset mistake.Yet, the situation that comprises flush bonding processor for FPGA, PowerPC processor for example, radiation-induced bit flipping still can have influence on flush bonding processor and relevant storer, causes such as single-particle inversions such as bit flippings.The capability of resistance to radiation of software approach strengthens mainly for the protection of flush bonding processor.The capability of resistance to radiation of software approach strengthens, comprise, for example usage data disturbs the method indicated to detect the incorrect result that data processing module produces, for example, incorrect as a result the time when occurring in flush bonding processor, can realize the correction to error result by the method for again data being processed.
Data disturb to indicate and to comprise that one is caught function, verification and function, error detector and correction, and other can judge the whether consistent method of result of two processors fast.Verification and comprise that the fixed qty data set calculated in binary data blocks is to detect the mistake that may occur in data transmission or storing process.By Real-Time Monitoring verification and function, realize the detection to wrong deal with data.The detection of mistake and correction are a kind of technology of guaranteeing reliability while using unreliable communication port transmission data.
For the execution error inspection, a private memory of disposal system is in order to stored program instruction, and when processor is carried out this program, the capability of resistance to radiation that obtains software approach strengthens.Program code is provided while perhaps, reshuffling device.In the present invention, this program code also is stored in another storer of disposal system.
The present invention confirms that the method that the data interference indicates requires two processors to carry out the Check processing task, and result is checked.For binary circuit, the result of at least three processors is compared better.With use to check three tunnel results, and remove the method difference of different that of result, the present invention adopt the verification that checks the two-way result and, if verification and inconsistent re-starts data and processes.
In the present invention, use software approach to strengthen the disposal system capability of resistance to radiation, when the gross error caused by radiation etc. occurring, Aeroflex FPGA's restarts logic one or more error recoveries path can be provided.The Restart Signal that can offer Xilinx FPGA comprises: software restarting order, PowerPC reset command, logic reset command, program reset command.
Can, according to when application mission requirements, use one or more data to process boards and realize Correlation method for data processing.
Claims (2)
1. the radiation-resistant data handling system based on FPGA is characterized in that:
The data of described system are processed board and are comprised two anti-fuse-type FPGA of radioresistance, two 32K PROM and 32K SRAM outer extension memory; Two reconfigurable non-complete radioresistance FPGA and corresponding configuration Flash; Memory device comprises that two 512MB have the SDRAM that the Flash storer of error detecting and error correcting function, two 512MB have error detecting and error correcting function; Peripheral Interface comprises PCIE, RS-422, Ethernet interface, SATA, Multi-Gbps Transceivers, I2C, CAN and GPIO;
The anti-fuse-type FPGA of described two radioresistances adopts Aeroflex UT6325FPGA.
Described two reconfigurable non-complete radioresistance FPGA adopt Xilinx Virtex-5Q FX130T FPGA, and corresponding configuration Flash is 32MB Xilinx configuration Flash.
2. the capability of resistance to radiation Enhancement Method based on the described system of claim 1 is characterized in that:
The data handling system capability of resistance to radiation strengthens by two steps to be realized: the first step, by flow chart of data processing design, provide capability of resistance to radiation to strengthen, at first be the system logic design optimization, then the complete radioresistance FPGA of right and wrong comprises three difference in functionality modules: control and processing module compare for control, command decode and the data processed result that inputs or outputs Data Control, data processing and storage; First via data processing module, process the input data, sets up first group of output deal with data, and data processed result is deposited in to first part of dual port RAM; The data processing module that the second tunnel is identical with the first via, process same input data, sets up second group of output deal with data, and data processed result is deposited in to the second part of dual port RAM; Then control and processing module compare the output deal with data of the first via and the second circuit-switched data processing module, if these two groups of data consistents are processed the output deal with data of output data as this sheet FPGA using first group or second group.Also comprise second and the identical non-complete radioresistance FPGA of first; same input data are processed; for setting up the 3rd group and the 4th group output deal with data, deposit respectively first and the second part of second dual port RAM in, the & of second FPGA; Processing module is the 3rd group and the 4th group of output deal with data relatively, if these two groups of data consistents, using the 3rd group or the 4th group, process the output deal with data of output data as second FPGA, then compare the output data of first and second non-complete radioresistance FPGA, to detect the mistake produced in data or data handling procedure, this output data comparison is completed by anti-fuse-type radioresistance type FPGA; When making a mistake, again data are processed.Further method also comprises the output data from first and second non-complete radioresistance FPGA, under pass the homogeneous data disposal system on ，Yu ground, ground back the output data compare; In addition, use anti-fuse-type radioresistance FPGA monitor non-complete radioresistance FPGA data handling procedure and check mistake, can remove most or all bit flipping mistakes; Second step, use software approach to be detected the mistake that may exist in the data processing procedure and proofread and correct to realize that capability of resistance to radiation strengthens, disturb in the non-complete radioresistance processor data processing procedures of methods detection such as signs the mistakes such as bit flipping because of introducings such as radiation by output result detections, tri-state redundancy, house dog, data, and this type of mistake is suitably proofreaied and correct, when gross error occurs, carry out the relevant logic of restarting.
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| US11120168B2 (en) | 2018-06-21 | 2021-09-14 | Safran Electronics & Defense | Method for protecting an FPGA against natural radiations |
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| CN114895622A (en) * | 2022-05-11 | 2022-08-12 | 中铁隧道局集团有限公司 | Underground low-temperature low-humidity special-reservoir cave depot environment control system |
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