CN110932748B - Large-scale antenna array digital wave control signal interface design method - Google Patents
Large-scale antenna array digital wave control signal interface design method Download PDFInfo
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- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
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- H—ELECTRICITY
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- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q21/00—Antenna arrays or systems
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- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/0408—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas using two or more beams, i.e. beam diversity
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Abstract
The invention discloses a large-scale antenna array digital wave control signal interface scheme. The invention adopts an improved SPI four-wire interface scheme, integrates a digital logic module with an SPI slave interface at the front end of radio frequency, and adopts a communication protocol of adding an ID label, thereby realizing the independent control of a single SPI host controller on all antenna units or the control of all antenna units under the condition of extremely large antenna scale (such as 1024 antennas). The interface scheme improves the traditional SPI control scheme, reduces the number of required interfaces to only 4 lines, thereby using low-cost FPGA or MCU as a host controller and not wasting extra interfaces. Another advantage of the present invention is that board-level antenna array routing is simple, reducing the number of required PCB routing layers to two and providing a feasible routing scheme.
Description
Technical Field
The invention relates to a design scheme of a large-scale antenna array digital wave control signal interface, which belongs to the technical field of electronic circuit design and is particularly suitable for large-scale antenna array design.
Background
In the hardware basis of satellite communication and radar technology, a large-scale antenna array is an indispensable key module. In order to transmit and receive electromagnetic waves in different directions, the transceiver needs to continuously adjust the gain and phase of each antenna in the antenna array. After the era of 5G and millimeter wave, the communication throughput and reliability requirements are greatly improved, the number of used antennas is remarkably increased, the array is more dense, and the difficulty of realizing accurate, real-time and efficient digital wave control signal interfaces is more increased.
The traditional antenna array control adopts a Serial Peripheral Interface (SPI) to carry out one-to-one and full-duplex communication between a controller and a radio frequency front-end chip. As shown in fig. 1 (a), the conventional control scheme has the advantages of simple implementation and low logic complexity of the on-chip digital module when the number of antenna arrays is small. When the chip select signal SS corresponding to the kth SPI slave is pulled low, it is selected and the master can communicate with it. However, for an N × N antenna array, when the number of antennas is N2When the number of the board-level control signal lines is increased, the number of the board-level control signal lines is in a trend of three times that of the antennas (3N)2+1) is greatly increased, resulting in increased board-level wiring difficulty and high interface overhead for the SPI host controllerAnd the efficiency is low. Taking an antenna array of 32 × 32(N is 32) for millimeter wave communication as an example, this solution requires 3073 interfaces to the SPI host, which means that the same number of control signal lines are arranged on the PCB, which is obviously difficult to implement. The reason is as follows: on one hand, the number of interfaces of a common single FPGA chip is limited, and 3073 is difficult to achieve; on the other hand, the arrangement of such many signal lines is also difficult to be completed by a common double-layer PCB, which may require four or even more layers, increasing the area of the PCB and the cost.
Disclosure of Invention
This design is through improvement and the optimization to traditional SPI agreement, proposes to adopt the communication scheme that four-wire scheme realized SPI host controller and large-scale antenna array. Each radio frequency front end chip in the antenna array is added with a different digital ID label. The scheme can realize a low-cost, one-to-many and full-duplex digital wave control signal interface. Because only four signal lines are used, the antenna array design can be realized by adopting a common low-cost double-sided PCB under the condition that a low-cost MCU or a single-chip small-capacity FPGA serves as a host. Meanwhile, the design provides a feasible design scheme of the SPI slave computer circuit.
In order to achieve the purpose, the invention adopts the following technical scheme:
a large-scale antenna array digital wave control signal interface design scheme, integrate a digital logic module with SPI slave interface in each phased array chip in the antenna array, adopted and joined the communication protocol of ID label, realize that the single SPI host controller controls all aerial units in the antenna array alone or controls all aerial units, wherein, each radio frequency front end in the antenna array has a different digital ID label;
the digital logic module comprises a core control logic module based on a Moore finite state machine, a reset control module, an error mechanism module, a general register, a phased array amplitude and phase register and an SPI slave machine; the SPI slave machine transmits a sending frame of the SPI master machine to the core control logic module, wherein the sending frame comprises a digital ID, an amplitude code and a phase code; the core control logic module controls reading and writing of the general register, and if and only if the ID in the sending frame is the same as the digital ID of the radio frequency front end corresponding to the digital logic module, the core control logic module distributes the amplitude and phase codes to the phased array amplitude and phase control register through the general register, and the phased array amplitude and phase control register is directly connected to the radio frequency front end; when the frame sending is started by the error mechanism module, when a frame error is found through frame length check and CRC detection, the communication between the general register and the communication between the phased array amplitude and phase register and the SPI slave interface are automatically closed, the frame error is recorded in the general register, when the SPI master inquires about the error, feedback is given through the MISO port of the SPI slave, and after the SPI master sends a reset frame, sequential synchronous reset is carried out under the control of the reset control module.
Furthermore, the four interfaces SCLK, MOSI, MISO and SS of the SPI slave are respectively and correspondingly connected with the four interfaces SCLK, MOSI, MISO and SS of the SPI master, wherein SCLK is a system synchronization clock of the SPI master and the SPI slave, SS is a low-level effective chip selection synchronization signal, MOSI is a master output/slave input interface, and MISO is a slave output/master input interface.
Furthermore, at any moment, the MISO of only one SPI slave is in an output state, and the MISOs of the rest SPI slaves are in a high-impedance state.
Further, the communication protocol for adding the ID tag is: the writing and outputting of the SPI interface take a frame as a unit; the SPI host outputs MOSI at the descending edge of SCLK, and samples MISO at the descending edge of SCLK; when the SS changes from high to low, the phased array chip is selected, serial input signals of the MOSI start to be stored in a buffer in the phased array chip until all the serial input signals are stored, and when the SS changes from low to high, data processing is started, corresponding registers are read and written, and MISO output is prepared; when SS is high, SCLK rising edge resets the state machine of the phase control array chip, SPI is in standby state; when the MODE register in the phased array chip is 1, the SPI works in the state of identifying the digital ID, can read and write, and can read and write only if the digital ID is correct, and once the digital ID is incorrect, the SPI slave computer immediately enters a standby state; the MODE register is in a no ID state when being 0, and is only writable and unreadable.
Technical effects
Compared with the prior art, the technical scheme of the invention has the following advantages:
the invention adopts an improved SPI four-wire interface scheme, integrates a digital logic module with an SPI slave interface at the front end of radio frequency, and adopts a communication protocol of adding an ID label, thereby realizing the independent control of a single SPI host controller on all antenna units or the control on all antenna units under the condition of extremely large antenna scale (such as 1024 antennas); the interface scheme improves the traditional SPI control scheme, reduces the number of required interfaces to only 4 lines, thereby using low-cost FPGA or MCU as a host controller without wasting extra interfaces; another advantage of the present invention is that board-level antenna array routing is simple, reducing the number of PCB routing layers required to two layers.
Drawings
FIG. 1 is a schematic block diagram of a conventional SPI control method and an improved four-wire control method, wherein (a) is the conventional SPI control method and (b) is the improved four-wire control method;
FIG. 2 is a schematic layout diagram of a dual layer PCB based antenna array;
FIG. 3 is a phased array chip internal control logic architecture;
FIG. 4 is a SPI chip write timing sequence;
FIG. 5 is a SPI chip read timing.
Detailed Description
The technical scheme of the invention is further explained by combining the drawings and the specific embodiments:
first, a digital control scheme of the entire system is described.
As shown in fig. 1 (b), this scheme can reduce the number of digital control signal lines to 4, namely, SCLK, MOSI, MISO, and SS in the general SPI protocol. Wherein, SCLK is system clock, MOSI is output of host and input of slave, MISO is input of host and output of slave, and SS is chip selection and synchronous signal. This approach is applicable to the specific system architecture and wiring method shown in fig. 2. Because only four digital signal lines are provided, the SPI host controller can select a small-capacity FPGA or a low-cost MCU.
The dual-layer PCB routing method illustrated in fig. 2 is an achievable routing method, in which the rf front end and the antenna array are arranged on the front side of the PCB; SCLK, MOSI, MISO and SS are divided into two groups of MOSI and SS, MISO and SCLK, each group respectively walking on the front or back of PCB (i.e. MOSI and SS walking on the front of PCB, MISO and SCLK walking on the back of PCB, or MOSI and SS walking on the back of PCB, MISO and SCLK walking on the front of PCB). VDD is a power supply, and the front side of the PCB is ensured to be VDD by paving copper on the front side of the PCB and connecting the back side of the PCB with each partition area on the front side; and the ground VSS is connected with the front side by spreading copper on the back side of the PCB by the same method. Compared with the traditional scheme which can be realized only by adopting a multi-pin FPGA and a multi-layer PCB, the cost and the design complexity are obviously reduced.
The digital logic module structure inside the corresponding phased array chip is described below, taking an SPI communication protocol with a frame length of 24 bits as an example.
First, as shown in fig. 1 (b), each rf front-end chip in the antenna array has a different digital ID tag numbered from 1 to N2. The digital ID tag herein may be implemented using an off-chip signal input, or an on-chip fuse (Efuse). Taking a 32 × 32 antenna array as an example, it is assumed that both transmitted and received amplitude phase signals are 6 bits, and a frame length specified by the SPI communication protocol is 24 bits.
The architecture of the digital logic module in the phased array chip is shown in fig. 3, and comprises a core control logic module based on a Moore finite state machine, a reset control module, an error mechanism module, a general register, a phased array amplitude and phase register and an SPI slave. The digital logic module has 7 inputs and outputs in addition to the 3.3V and 1.1V power and ground ports.
The function of each sub-module in the digital logic module is described as follows:
the SPI slave machine transmits a sending frame of the SPI master machine to the core control logic module, wherein the sending frame comprises an ID, an amplitude code and a phase code;
the core control logic distributes the amplitude and phase codes to the internal buffers and controls the reading and writing of general purpose registers. If and only if the ID in the sending frame is the same as the digital ID of the radio frequency front end corresponding to the digital logic module, the reading and writing functions of the general register normally work;
the amplitude and phase codes are stored in a phased array amplitude and phase register and are directly connected to a radio frequency front end;
the general purpose register controls the state of the whole phased array chip;
and an error mechanism module, wherein when the error mechanism module is detected to open the transmission frame, the error mechanism is opened. When a frame error is found through frame length check and CRC detection, the module automatically closes communication between an internal register of the digital logic module and the SPI (serial peripheral interface) interface (namely error content is not sent to a radio frequency front end), records the error in a general register, and gives feedback through an MISO (single input single output) port when an SPI host inquires the error. Because the multiple output interfaces are directly connected on the MISO, the MISO is a three-state bus, only the MISO of one SPI slave is in an output state at any moment, and the MISOs of the other SPI slaves are in a high-impedance state. After the SPI host computer sends the frame that resets, whole phased array chip can be in order synchronous reset under the control of module that resets.
Specific communication protocols are described below.
The improved SPI four-wire interface protocol mainly depends on four interfaces of SCLK, MOSI, MISO and SS, and can complete the read-write operation of wave control signal. Wherein SCLK is the system synchronous clock of SPI master and slave, SS is the effective chip selection synchronous signal of low level. MOSI is the interface of the host output (chip input), MISO is the interface of the chip output (host input).
The writing and outputting are both in units of frames, and the length of each frame is fixed to be 24 bits.
SDI samples MOSI at SCLK rising edge, SCLK rising edge outputs MISO, so SPI host needs to output MOSI at SCLK falling edge, sampling MISO at SCLK falling edge. When SS changes from high to low, the phased array chip is selected, serial input signals of MOSI start to be stored in a 24-bit buffer in the phased array chip until all 24-bit signals are stored, and when SS changes from low to high, data start to be carried outReads and writes the corresponding register, and prepares the output of the MISO. When SS is high, SCLK rising edge resets the state machine of the phase control array, and SPI is in standby state. When the MODE register in the phased array chip is 1, the SPI works in an ID recognition state, the SPI can read and write, the ID is correct, and once the ID of the first 4 bits is incorrect, the SPI immediately enters a standby state. When MODE is 0, it is in non-ID state, and can only be written, and can not be read, at this time it can implement all N2Simultaneous control of the individual chips.
The write timing is shown in fig. 4. After the SS falling edge, the MOSI writes a 24-bit write command frame whose function is realized at the SS rising edge. When writing continuously, the MISO presents a high impedance state.
The read timing exists only when there is an ID MODE, i.e., when the MODE register is written to 1. As shown in fig. 5. After SS falling edge, MOSI writes 24bit read command frame, at SS rising edge, output content put into MISO buffer in advance, output at next frame. Meanwhile, the next frame will also take effect, if the next frame is not required to take effect, an invalid frame with the correct ID number can be written. The MISO state at the time of the read command frame is not of interest at this time because the current MISO state is only relevant to the previous frame.
In an actual application scenario, the transmission frames are in the following order. First, an ID frame is sent, which has an inherent frame header followed by the ID number to be written next, assuming that the ID is k. And then all frames sent by the SPI host only communicate with the phased array chip with the digital ID of k. After the communication with the phased array chip with the ID k is completed, a new ID frame is transmitted, and the individual communication with the chip with the next ID can be performed.
The invention adopts an improved SPI four-wire interface scheme, integrates a digital logic module with an SPI slave interface on a phased array chip, and adopts a communication protocol of adding an ID label, thereby realizing the independent control of a single SPI host controller on all antenna units or the control on all antenna units under the condition of extremely large antenna scale (such as 1024 antennas). The interface scheme improves the traditional SPI control scheme, reduces the number of required interfaces to only 4 lines, thereby using low-cost FPGA or MCU as a host controller and not wasting extra interfaces.
The above description is only an embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can understand that the modifications or substitutions within the technical scope of the present invention are included in the scope of the present invention, and therefore, the scope of the present invention should be subject to the protection scope of the claims.
Claims (3)
1. A large-scale antenna array digital wave control signal interface design method is characterized in that each phased array chip in an antenna array integrates a digital logic module with an SPI slave interface, a communication protocol with an ID label is adopted, the number of interfaces of an SPI host is reduced to four, and the single SPI host can independently control all antenna units in the antenna array or control all antenna units, wherein each radio frequency front end in the antenna array is provided with a different digital ID label, and the interfaces of the SPI host are SCLK, MOSI, MISO and SS;
the SCLK, MOSI, MISO and SS interfaces of each SPI slave are respectively and correspondingly connected with SCLK, MOSI, MISO and SS interfaces of the SPI master, wherein SCLK is a system synchronous clock of the SPI master and the SPI slave, SS is a low-level effective chip selection synchronous signal, MOSI is an interface of master output/slave input, and MISO is an interface of slave output/master input;
the digital logic module comprises a core control logic module based on a Moore finite state machine, a reset control module, an error mechanism module, a general register, a phased array amplitude and phase register and an SPI slave machine; the SPI slave machine transmits a sending frame of the SPI master machine to the core control logic module, wherein the sending frame comprises a digital ID, an amplitude code and a phase code; the core control logic module controls reading and writing of the general register, and if and only if the ID in the sending frame is the same as the digital ID of the radio frequency front end corresponding to the digital logic module, the core control logic module distributes the amplitude and phase codes to the phased array amplitude and phase control register through the general register, and the phased array amplitude and phase control register is directly connected to the radio frequency front end; when the frame sending is started by the error mechanism module, when a frame error is found through frame length check and CRC detection, the communication between the general register and the phase array amplitude and phase register and the SPI slave interface is automatically closed, the frame error is recorded in the general register, when the SPI host inquires about the error, feedback is given through the MISO port of the SPI slave, and after the SPI host sends a reset frame, sequential synchronous reset is carried out under the control of the reset control module;
the design method adopts a double-layer PCB wiring mode, and specifically comprises the following steps: the radio frequency front end and the antenna array are arranged on the front side of the PCB; four interfaces SCLK, MOSI, MISO and SS of the SPI slave machine are divided into two groups, MOSI and SS, MISO and SCLK, each group respectively runs on the front side or the back side of the PCB, namely MOSI and SS run on the front side of the PCB and MISO and SCLK run on the back side of the PCB, or MOSI and SS run on the back side of the PCB and MISO and SCLK run on the front side of the PCB; VDD is a power supply, and the front side of the PCB is ensured to be VDD by paving copper on the front side of the PCB and connecting the back side of the PCB with each partition area on the front side; VSS is ground, and the front side is connected with each division area on the back side by spreading copper on the back side of the PCB, so that the back side of the PCB is guaranteed to be VSS.
2. The design method of digital wave control signal interface of large scale antenna array of claim 1, characterized in that only MISO of one SPI slave is in output state at any moment, and MISO of other SPI slave is in high impedance state.
3. The method as claimed in claim 1, wherein the communication protocol for adding ID tag is: the writing and outputting of the SPI interface take a frame as a unit; the SPI host outputs MOSI at the descending edge of SCLK, and samples MISO at the descending edge of SCLK; when the SS changes from high to low, the phased array chip is selected, serial input signals of the MOSI start to be stored in a buffer in the phased array chip until all the serial input signals are stored, and when the SS changes from low to high, data processing is started, corresponding registers are read and written, and MISO output is prepared; when SS is high, SCLK rising edge resets the state machine of the phase control array chip, SPI is in standby state; when the MODE register in the phased array chip is 1, the SPI works in the state of identifying the digital ID, can read and write, and can read and write only if the digital ID is correct, and once the digital ID is incorrect, the SPI slave computer immediately enters a standby state; the MODE register is in a no ID state when being 0, and is only writable and unreadable.
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| CN201911219696.6A CN110932748B (en) | 2019-12-03 | 2019-12-03 | Large-scale antenna array digital wave control signal interface design method |
| PCT/CN2020/095236 WO2021109525A1 (en) | 2019-12-03 | 2020-06-09 | Method for digital wave control signal interface of large-scale antenna array |
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