CN110061765B - 5G onboard double 2X 2MIMO wireless control system - Google Patents
5G onboard double 2X 2MIMO wireless control system Download PDFInfo
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Abstract
The invention discloses a 5G onboard double 2X 2MIMO wireless control system, which comprises a hardware platform, a bottom layer driving module and an upper layer application module; the hardware platform is at least provided with two idle SPI buses and a plurality of GPIO ports, and the power supply equipment is connected with the GPIO ports and supplies power to the hardware platform; two AD9371 chips, an AD9528 chip and an FPGA chip are carried on the hardware platform, wherein the two AD9371 chips and the AD9528 chip share a first SPI bus and are respectively controlled through different CS chip selection signals. The onboard platform of the invention integrates 2 AD9371 chips, thereby supporting double 2X 2 (namely 4X 4) MIMO, only 16 onboard platforms are needed to form 64 antenna arrays, not only the cost is reduced, but also the installation space is greatly reduced, and the layout is more compact and reasonable.
Description
Technical Field
The invention relates to the field of communication equipment, in particular to a wireless control system for 5G communication.
Background
The 5G network is a fifth and latest generation mobile communication network, and its peak transmission speed theoretically reaches several tens of G (unit: bps, i.e., bits per second), which is hundreds of times faster than the 4G network currently in use.
Since the transmission of signals on the ultra-high frequency band has the disadvantages of large loss and short transmission distance, the technical problem has been a bottleneck restricting the development of networks in the industry, and the high-speed long-distance transmission of signals on the ultra-high frequency band is not possible until the problem is overcome by the adaptive array transmission technology of 64 antenna units by using samsung electronics in 2014. In 2016, Nokia in cooperation with Bell corporation completed the 5G signal testing work in Canada. In 2017, release 5G NR was formally released at the international telecommunication standards organization 3GPP RAN meeting en masse 78, the first commercially deployed 5G standard worldwide. By the end of 2018, the ministry of national industry and informatization divided 5G test frequency resources for china telecommunications, china mobile and china federation respectively, and marked that 5G networks formally enter the deployment and commercial stages in China.
In this large background, as a foundation of the 5G network, an antenna array product with MIMO and a control system thereof become an indispensable important component for constructing the 5G network. The current MIMO antenna array basically adopts a 2 × 2MIMO antenna array (2 × 2, i.e. 2 receive +2 transmit, 1 receive 1 transmit is an antenna pair, which is a minimum unit for a radio frequency system to work normally), and its wireless control system software is also developed based on this antenna array. Such as the HJX-AD9371-SDR software radio platform.
At present, similar HJX-AD9371-SDR software radio platforms basically have the following defects and shortcomings:
(1) most of the current platforms are only Evaluation versions (AD9371 Evaluation Boards), which are provided for clients to test and develop secondarily, and are away from the real business;
(2) the platform only supports 2 × 2MIMO (an AD9371 chip is adopted, and a 2-transceiver and 2-transceiver RF transceiver is provided), if 64 antenna arrays (namely 64 × 64 MIMO) are to be formed, 32 onboard platforms are required, which is not only high in cost, but also occupies a large installation space, so that the layout is difficult;
(3) the control software of the platform is developed based on an Atmel ARM9 embedded platform, the coupling degree between a bottom layer drive and upper layer application is high in design, the embedded development concept is not completely followed, and upper layer application developers need to pay close attention to the structural design of bottom layer hardware, so that the transportability is poor;
(4) due to safety considerations, the platform applies a hardware watchdog device, which causes the platform to be inconvenient to maintain and operate, and although platform software provides a console interaction function for a user, the platform has poor operability, low reliability and slight carelessness in operation, or the upper-layer application is suspended for some reason and cannot perform a watchdog feeding operation in time, and the watchdog causes the system to be restarted.
Disclosure of Invention
The purpose of the invention is as follows: the invention aims to provide a 5G onboard dual 2X 2MIMO wireless control system aiming at the defects of the prior art, support a 4X 4 MIMO antenna array, meet the layout requirement of a given installation space, reduce the cost and realize commercialization.
The technical scheme is as follows: the invention relates to a 5G onboard double 2X 2MIMO wireless control system, which comprises a hardware platform, a bottom driving module and an upper application module;
the hardware platform is at least provided with two idle SPI buses and a plurality of GPIO ports, and the power supply equipment is connected with the GPIO ports and supplies power to the hardware platform; two AD9371 chips, an AD9528 chip and an FPGA chip are carried on the hardware platform, wherein the two AD9371 chips and the AD9528 chip share a first SPI bus and are respectively controlled by different CS chip selection signals, the AD9528 chip is used for providing working clock signals for the AD9371 chip, and the FPGA chip interacts with a second SPI bus to provide functions related to AD9371 configuration and front-end channel parameters;
the bottom layer driving module comprises a first SPI bus equipment management module, a second SPI bus equipment management module and a GPIO control module, the first SPI bus equipment management module is communicated with a first SPI bus, the upper layer application module controls the configuration of two AD9371 chips, and the two AD9371 chips are configured in different copies and the same configuration parameter mode; the second SPI bus equipment management module is communicated with the second SPI bus, drives resources provided by an onboard system to realize reading and writing of each chip equipment of the SPI bus and control of a GPIO port, and provides an IOCTL interface for upper-layer application;
the upper application module communicates with the first SPI bus equipment management module through an IOCTL interface provided by the bottom driving module, and controls the first SPI bus to read and write the AD9371 chip.
The invention further preferably adopts the technical scheme that the hardware platform is an ARM9 embedded platform or an ARM Cortex-A8 embedded platform.
Preferably, the hardware platform further has at least one ETHERNET port resource and a serial port or USB port resource; the hardware platform is connected to a switch or a local area network through an ETHERNET network port resource.
Preferably, the bottom layer driving module controls the GPIO terminal pin and abstracts the GPIO terminal pin so that the GPIO terminal pin is invisible to the upper layer application module.
Preferably, the upper application module comprises a local operation and maintenance module, a configuration management module and a remote monitoring module.
Preferably, the upper layer application module configures the AD9371 chip one by one according to the ADI standard configuration flow and the general API interface provided by the upper layer application module.
The invention also provides a 5G antenna array which comprises 16 wireless control systems, wherein each wireless control system adopts the same software and hardware environment, and is uniformly powered and configured.
Has the advantages that: (1) the invention is designed directly aiming at commercial use and requirement, and has stronger purpose; the onboard platform of the invention integrates 2 AD9371 chips, thereby supporting double 2X 2 (namely 4X 4) MIMO, only 16 onboard platforms are needed to form 64 antenna arrays, not only reducing the cost, but also greatly reducing the installation space, and having more compact and reasonable layout;
(2) the control software follows the design concept of an embedded system, the functions of a bottom layer drive and an upper layer application are separated in the design, and the upper layer application does not need to pay attention to how the lower layer drive is interacted with hardware, so that the coupling degree between the bottom layer drive and the hardware is greatly reduced, and the software can be conveniently transplanted to a new embedded platform;
(3) the onboard platform does not need watchdog equipment, and the software system provides safety support, so that the onboard platform is more beneficial to maintenance;
(4) the control system software of the invention provides a uniform Socket interface for the outside, and can realize remote monitoring and management through a network according to a corresponding interface protocol.
Drawings
Fig. 1 is a schematic structural diagram of a wireless control system according to the present invention.
Fig. 2 is a flow chart of the local operation and maintenance module in the upper application function module according to the present invention.
FIG. 3 is a flow chart of a configuration management module in the upper layer application function module according to the present invention.
Fig. 4 is a flow chart of the remote monitoring module in the upper application function module according to the present invention.
Detailed Description
The technical solution of the present invention is described in detail below with reference to the accompanying drawings, but the scope of the present invention is not limited to the embodiments.
Example (b): a 5G onboard dual 2 × 2MIMO wireless control system, as shown in fig. 1, includes a hardware platform, a bottom layer driving module and an upper layer application module.
The hardware platform is an ARM9 embedded platform, an ARM Cortex-A8 embedded platform or other platforms, but the selected platform can provide at least 2 idle onboard SPI buses, an ETHERNET network port resource, a serial port or USB port resource and a plurality of GPIO port resources. The power supply equipment is connected with the GPIO port and supplies power to the hardware platform; two AD9371 chips, an AD9528 chip and an FPGA chip are carried on the hardware platform. A single on-board system adopts a double 2 x 2MIMO structure, namely 2 AD9371 chips are adopted, and the 2 AD9371 RF transceivers are respectively configured to a normal working state through ARM system software (including bottom layer drive and upper layer application), so that a 4 x 4 MIMO function is realized. The two AD9371 chips and the AD9528 chip share a first SPI bus and are respectively controlled by different CS chip selection signals, and the AD9528 chip is used for providing working clock signals for the AD9371 chip, so that the AD9371 chip can be configured in advance, and SPI bus resources are not occupied; the FPGA chip interacts with the second SPI bus, providing functionality related to configuring the AD9371 and front-end channel parameters, with reference to the existing radio platform.
The bottom layer driving module comprises a first SPI bus equipment management module, a second SPI bus equipment management module and a GPIO control module, the first SPI bus equipment management module is communicated with a first SPI bus, the upper layer application module controls the configuration of two AD9371 chips, and the two AD9371 chips are configured in different copies and the same configuration parameter mode; the second SPI bus equipment management module is communicated with the second SPI bus, drives resources provided by an onboard system to realize reading and writing of each chip equipment of the SPI bus and control of a GPIO port, and provides an IOCTL interface for upper-layer application; the bottom layer driving module group controls the GPIO terminal pins and abstracts the GPIO terminal pins to make the GPIO terminal pins invisible to the upper layer application module. The wireless control system follows the development concept of an embedded system, the functional boundary of a bottom layer driver and an upper layer application is cleared, the bottom layer driver focuses on a specific hardware platform to realize direct control on hardware equipment, the upper layer application focuses on a specific application scene, related functions are converted into operations unrelated to hardware, and required IOCTLs are determined for the operations.
The upper application module communicates with the first SPI bus equipment management module through an IOCTL interface provided by the bottom driving module, and controls the first SPI bus to read and write the AD9371 chip. The upper application module comprises a local operation and maintenance module, a configuration management module and a remote monitoring module. The upper application module follows ADI standard configuration flow and a universal API (application programming interface) provided by the ADI standard configuration flow to carry out configuration on the AD9371 chip one by one.
In an operational aspect, the wireless control system in the embodiment provides a graphical application interactive interface on a PC for a user besides providing a local console interactive interface, so that the user can connect an onboard system to a switch or a local area network through an ETHERNET, thereby realizing remote monitoring and management of the onboard system.
In order to ensure the system security, except opening the necessary ports, unnecessary ports and related services are closed, and a system login password authentication function is added.
The 16 wireless control systems of the embodiment are applied to form 64 antenna arrays for the 5G base station to use, and the wireless control systems adopt the same software and hardware environment, supply power uniformly and are configured uniformly.
As shown in fig. 2, the flow of the local operation and maintenance module in the upper layer application function module is as follows:
firstly, operation and maintenance personnel start to access a local board card system;
checking LOG information by operation and maintenance personnel, and analyzing the current operation condition of the board card system;
③ if there is a failure:
if the equipment is in failure, analyzing and removing the failure reason;
if the software is in fault or needs to be upgraded, the new software is updated;
fourthly, after the software is removed or updated, the operation and maintenance personnel electrify the onboard system again, check whether the operation of the configuration management module is normal or not, and finish the local operation and maintenance work if the operation is confirmed to be correct;
if there is hidden system safety trouble, the operation and maintenance personnel can close unnecessary service and corresponding port, and strengthen the management of login password.
As shown in fig. 3, the configuration management module flow in the upper layer application function module is as follows:
firstly, loading default configuration information by a configuration system;
continuously loading the driving module and opening a corresponding equipment file;
checking the state of the FPGA if the loading is successful;
if the FPGA state is ready, starting to configure an external clock of the AD9371 (which can be realized by configuring the AD 9528);
if the result is successful, the first AD9371 is configured according to the configuration copy 1 (marked by 9371_0 in FIG. 3) following the ADI flow;
sixthly, if the configuration is successful, the second AD9371 is configured according to the configuration copy 2 (marked by 9371_1 in figure 3);
seventhly, if the result is successful, configuring preposed RF channel parameters;
if yes, the configuration work is completed successfully;
otherwise, if any step in the previous operation fails, the configuration work fails, the configuration system will count the error information into the LOG of the system, and the warning can be given by controlling the LED lamp, so that the operation and maintenance personnel can use the warning for later inspection.
As shown in fig. 4, the remote monitoring module in the upper layer application function module has the following flow:
firstly, a PC terminal worker begins to check the running state of an onboard system;
secondly, the PC side application sends a connection request to the board card through the local area network;
if the board card system runs normally, the connection request is received, and connection is established with the PC side application;
fourthly, the PC terminal application sends a state query request to the board card system;
feeding the current state back to the PC side application by the board card system;
judging whether the board card system has a fault by the PC terminal application according to the feedback state information;
if the board card system operates normally, the PC side application sends a disconnection request to the board card system, and the board card system disconnects the connection with the PC side application; otherwise, if the board card system has no response or the feedback has a fault, the monitoring personnel at the PC terminal informs the operation and maintenance personnel to intervene.
As noted above, while the present invention has been shown and described with reference to certain preferred embodiments, it is not to be construed as limited thereto. Various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (7)
1. A5G onboard double 2X 2MIMO wireless control system comprises a hardware platform, a bottom layer driving module and an upper layer application module;
the hardware platform is characterized by at least comprising two idle SPI buses and a plurality of GPIO ports, and the power supply equipment is connected with the GPIO ports and supplies power to the hardware platform; two AD9371 chips, an AD9528 chip and an FPGA chip are carried on the hardware platform, wherein the two AD9371 chips and the AD9528 chip share a first SPI bus and are respectively controlled by different CS chip selection signals, the AD9528 chip is used for providing working clock signals for the AD9371 chip, and the FPGA chip interacts with a second SPI bus to provide functions related to AD9371 configuration and front-end channel parameters;
the bottom layer driving module comprises a first SPI bus equipment management module, a second SPI bus equipment management module and a GPIO control module, the first SPI bus equipment management module is communicated with a first SPI bus, the upper layer application module controls the configuration of two AD9371 chips, and the two AD9371 chips are configured in different copies and the same configuration parameter mode; the second SPI bus equipment management module is communicated with the second SPI bus, drives resources provided by an onboard system to realize reading and writing of each chip equipment of the SPI bus and control of a GPIO port, and provides an IOCTL interface for upper-layer application;
the upper application module communicates with the first SPI bus equipment management module through an IOCTL interface provided by the bottom driving module, and controls the first SPI bus to read and write the AD9371 chip.
2. The 5G on-board dual 2 x 2MIMO wireless control system of claim 1, wherein the hardware platform is an ARM9 embedded platform or an ARM Cortex-A8 embedded platform.
3. A 5G on-board dual 2 x 2MIMO wireless control system as claimed in claim 2, wherein said hardware platform further has one serial or USB port resource, and at least one ETHERNET port resource; the hardware platform is connected to a switch or a local area network through an ETHERNET network port resource.
4. The 5G on-board dual 2 x 2MIMO wireless control system of claim 1 wherein the bottom driver module controls GPIO pins and abstracts them from view to upper application modules.
5. The 5G on-board dual 2 x 2MIMO wireless control system of claim 1, wherein the upper application module comprises a local operation and maintenance module, a configuration management module and a remote monitoring module.
6. The 5G on-board dual 2 x 2MIMO wireless control system of claim 5, wherein the upper layer application module configures the AD9371 chips one by one according to ADI standard configuration flow and the general API interface provided by the ADI standard configuration flow.
7. A5G antenna array comprises 16 wireless control systems according to any one of claims 1 to 6, wherein the wireless control systems adopt the same software and hardware environment, are uniformly powered and are uniformly configured.
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| CN103901448B (en) * | 2014-03-28 | 2017-02-15 | 哈尔滨工程大学 | GPS/BD2 dual-mode universal receiving device |
| CN106464289B (en) * | 2015-11-04 | 2019-07-05 | 深圳博芯科技股份有限公司 | 5.8G remote-wireless data transmission system |
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| EP1460496A1 (en) * | 2003-03-19 | 2004-09-22 | Robert Bosch Gmbh | Peripheral chip set |
| CN203054509U (en) * | 2012-12-26 | 2013-07-10 | 南京长峰航天电子科技有限公司 | Digital signal processing platform |
| WO2014160161A1 (en) * | 2013-03-14 | 2014-10-02 | Rosemount Inc. | Communications unit for an industrial process network |
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