CN112000610B

CN112000610B - Simplified phased array multi-chip synchronous configuration method

Info

Publication number: CN112000610B
Application number: CN202010914565.6A
Authority: CN
Inventors: 俞天成; 李薇; 兰冰; 聂辉; 刘东栋
Original assignee: Zhejiang Jisu Hexin Technology Co ltd
Current assignee: Zhejiang Jisu Hexin Technology Co ltd
Priority date: 2020-09-03
Filing date: 2020-09-03
Publication date: 2023-10-27
Anticipated expiration: 2040-09-03
Also published as: CN112000610A

Abstract

The invention relates to a simplified phased array multi-chip synchronous configuration method. The phased array comprises a master chip and a slave chip, wherein the number of address pins of the slave chip in the phased array is a plurality, and the number of the slave chips which can be accessed by the master chip is determined. The master chip sends addressing information to all slave chips in a broadcasting mode, and only the slave chips with matched chip addresses can respond to subsequent register addresses and configuration values.

Description

Simplified phased array multi-chip synchronous configuration method

Technical Field

The invention relates to the field of chip control protocols, in particular to a method for simplifying synchronous configuration of phased array multiple chips.

Background

Along with commercialization of 5G communication and low-orbit satellite communication, the phased array system becomes an infrastructure of an electronic information system such as a communication radar and the like by virtue of the advantages of concentrated beam energy, strong multi-target capability, high reliability and the like.

The phased array is a system formed by a plurality of chips (hereinafter referred to as array chips) arranged in an array, and at present, an SPI high-speed serial interface is generally adopted to independently control each chip. When the array scale is large, the control signal lines are very many, such as a system with N chips, a three-wire SPI protocol is adopted, SCLK and SDIO of SPI are shared, each chip has independent CSB signals, the whole control signal quantity is N+2, N is more than 128, FPGA with thousands of pins is possible to be used for SPI control, or a plurality of CPLD chips are used for pin expansion control, the PCB wiring is complex, the array chip control difficulty is high, in addition, the serial writing time depends on SPI clock period and address bit width, and the configuration time of a large phased array distributed with a plurality of chips can not meet the requirement of beam scanning speed.

In addition, multiple chips of the phased array need to be mutually associated to jointly complete the beamforming function, but after the serial data writing of the traditional SPI interface is completed, configuration words corresponding to one register are acted every time the configuration is completed, so that the problem that the traditional SPI configuration process is disordered in wave beams, and serious consequences of no functions in the configuration period are caused, and therefore a synchronous configuration mechanism is needed to ensure the realization of the beamforming function of the phased array.

Disclosure of Invention

In view of the above technical drawbacks, the present invention provides a method for simplifying the synchronous configuration of multiple phased array chips.

The technical scheme of the invention is as follows:

a simplified phased array multi-chip synchronous configuration method comprises a master chip and a slave chip, wherein the master chip at least comprises the following IO pins: a unidirectional output chip selection signal pin, a clock signal pin, a synchronous configuration signal pin and a bidirectional read-write data signal pin.

The slave chips are array chips which need to complete register configuration in the phased array, and each slave chip comprises the same IO pins: the device comprises a unidirectional input chip address pin, a chip selection signal pin, a clock signal pin, a synchronous configuration signal pin and a bidirectional read-write data signal pin, wherein the number of the slave chip address pins is multiple, and the number of the slave chips which can be accessed by the master chip is determined.

All the chip selection signal pins of the slave chips are connected with the chip selection signal pins of the master chip, all the clock signal pins of the slave chips are connected with the clock signal pins of the master chip, all the synchronous configuration signal pins of the slave chips are connected with the synchronous configuration signal pins of the master chip, and all the read-write data signal pins of the slave chips are connected with the read-write data signal pins of the master chip. The read-write data signal pins of the slave chip are bidirectional IO pins for outputting three states.

The master chip sends addressing information to all the slave chips in a broadcast mode, and only the slave chips with matched chip addresses respond to the subsequent register addresses and configuration values.

Based on the physical structure, the synchronous configuration method specifically comprises the following steps:

the write configuration mode in the configuration method comprises the following steps:

write configuration mode 1: the long frame broadcast writes successive address configuration values.

All slave chips receive and respond to the same broadcast write instruction which only provides the start register address bits, no register address is subsequently provided, and a fixed bit width configuration word is written starting from the start register bits.

Write configuration mode 2: the write configuration value is broadcast at a single address.

All slave chips receive and respond to the same broadcast write command, and only write one address.

Write configuration mode 3: the single chip consecutive addresses write the configuration values.

Write operations are performed to a plurality of consecutive register addresses of a slave chip.

Write configuration mode 4: the configuration value is written by a single address of a single chip.

A write operation is performed to an address of the single slave chip.

After the writing operation is completed in the four writing configuration modes, the configuration values are temporarily stored in a latch, a register or a RAM, but the configuration is not completed, and the final configuration is completed after waiting for the arrival of the synchronous configuration signal of the main chip and sampling a jump edge of the synchronous configuration signal by the clock signal pin of the slave chip.

The read configuration mode in the configuration method comprises the following steps:

read configuration mode 1: the data is read from the chip sequentially at addresses.

The master chip broadcasts a read command, each slave chip matches a chip address, and only the chips with the chip addresses respond to subsequent commands.

The continuous reading instruction gives out an initial reading register address, the slave chip with the chip selection address accords with the initial reading register address, the output state of the reading and writing data signal pins is adjusted from a high-resistance state to a normal output state, the corresponding register configuration is output from the initial address, and the subsequent continuous output is carried out until the maximum register address.

Read configuration mode 2: a single chip reads data at a single address.

The slave chip for the read operation is selected by broadcasting the chip address.

Further, the main chip may be, but not limited to, an FPGA, a CPLD, or a single chip microcomputer.

Furthermore, in order to ensure the synchronicity of the configuration of the plurality of slave chips, the delay time from the master chip to the synchronic configuration signal pins of each slave chip is as same as possible, and on a specific PCB, the synchronic configuration signal lines and the clock signal lines are arranged in parallel, and wiring is completed according to a tree structure, so that all the slave chips are ensured to complete configuration simultaneously.

The invention has the beneficial effects that: the invention can reduce the difficulty of layout and wiring of the chip control line of the phased array system and realize the function of synchronous configuration of multiple chips.

Drawings

FIG. 1 is a physical structure diagram of a slave chip;

FIG. 2 is a schematic diagram of the address of each slave chip disposed on a PCB;

FIG. 3 is a general architecture diagram of the present invention;

FIG. 4 is an exemplary diagram of data formats in write configuration mode 1;

FIG. 5 is an exemplary diagram of data formats in write configuration mode 2;

FIG. 6 is an exemplary diagram of data formats in write configuration mode 3;

FIG. 7 is an exemplary diagram of data formats in write configuration mode 4;

FIG. 8 is a tree wiring diagram of the sync_load and SCLK signals;

FIG. 9 is a diagram showing an example of data format in the read configuration mode 1;

fig. 10 is a diagram showing an example of the data format in the read configuration mode 2.

Detailed Description

The phased array chip adopts a master-slave (master-slave) structure, a master chip (master) can be but not limited to an FPGA or a singlechip, and IO pins of the master chip at least comprise but not limited to a chip select signal pin (CSB), a clock signal pin (SCLK), a synchronous configuration signal pin (sync_load) and a read-write data signal pin (SDIO). The IO pins are output IO (output) except that the read-write data signal pin (SDIO) is a bidirectional signal, and the signal direction is from master to slave.

The slave chip (slave) is an array chip in the phased array system that needs to complete the register configuration. Each array chip includes the same IO pins, namely a chip address pin (chip address), a chip select signal pin (CSB), a clock signal pin (SCLK), a synchronization configuration signal pin (sync_load), and a read/write data signal pin (SDIO). The IO pins are input IO (input) except that a read-write data signal pin (SDIO) is a bidirectional signal for outputting tri-states, and the signal direction is from master to slave.

As shown in fig. 1, the number of chip address pins (chip address IOs) of the slave chip determines the number of chips that the master chip accesses simultaneously, for example, 10 IO pins are provided for each array chip to do chip address (chip address IOs), so that a maximum of 2≡10=1024 chips can be configured by one master chip at the same time, i.e. a maximum of 1024 chips can be supported by one array. The slave chips supported by the chip address form a phased array subarray.

Each slave chip has the same configuration register inside, and the register address (regaddress) is determined by design according to the number of configuration words.

In phased array subarrays, the chip address of each slave chip is unique (unique), and chip address configuration is completed on the PCB (see FIG. 2), for example, the chip address of the chip 1 is configured to be 000, namely, the chip addresses of the slave chips are all connected to the ground, the chip 2 chip address is configured to be 001, namely, the lowest bit (LSB) of the chip 2 chip address is connected to the high level, and other addresses are grounded; the chip address of the slave chip 8 is configured to 111, i.e. the chip address of the slave chip 3 is all high, and so on.

All slave chip CSBs are connected with master chip CSBs, all slave chip SCLK is connected with master chip SCLK signal, all slave chip SYNC_LOAD pins are connected with master chip SYNC_LOAD, all slave chip SDIO pins are connected with master chip SDIO, forming the architecture of FIG. 3.

Because of the independence of the chip addresses, the master chip (master) can send addressing information to the slave chips in all subarrays in a broadcast mode, and only the slave chips with the same chip address can respond to the subsequent register addresses and configuration values, and the processing is not performed when the chip addresses are not consistent. This can thus be used as a few control pins to achieve a multi-chip configuration. For example, 1024 chips are configured by using a traditional 3-wire SPI, 1026 control wires are required at least, one FPGA does not meet the requirements of GPIO number, and the control wires can be met only by controlling an IO port through a CPLD, so that the PCB wiring and layout are very complex. With the above architecture, the configuration can be completed only with 3 wires, so the system design is greatly simplified.

According to the architecture, a set of communication protocols are designed, and the configuration speed is increased according to the protocol content defined by different modes. The main modes include:

mode 1: the long frame broadcast writes successive address configuration values. That is, all sub-chips receive the same broadcast write instruction from the chip, the instruction only provides the start register address bit, no register address is provided later, and the fixed bit width configuration word is written from the start register bit.

As shown in fig. 5, which is typically 8bit data width, the register address accumulation is then automatically considered. For example, a register bit width of 8 bits, and 24 bits of data are consecutive after writing a start register address of, for example, 0x01, then the internal decoding state machine corresponding to each sub-array chip recognizes as a write command as shown in fig. 5.

Mode 2: the write configuration value is broadcast at a single address. I.e. all sub-chips receive the same broadcast write command from the chip, and only write to one address, such as the data format shown in fig. 6.

And the broadcasting write operation is carried out, and all chips in the subarray complete the same configuration action. The broadcast configuration mode is generally used for performing global initialization configuration or startup self-checking and other operations, and can greatly save configuration time under the condition of large array scale.

Mode 3: the single chip consecutive addresses write the configuration values. Write operations are performed for multiple consecutive register addresses of a certain chip. This first requires distinguishing between the tile address and the register start address. Such as the data format shown in fig. 7.

The data format only carries out continuous register writing operation on a chip with a chip address of 01, the initial address of a register is 0x01, and 3 registers are continuously written. Other slave chips do not respond to subsequent write operations after receiving the chip address and comparing the chip address with the own chip address after not matching the chip address.

It should be noted that the chip address is related to the number of chip address bits of the slave chip, for example, the slave chip provides 10bit chip select address bits, but the actual subarray system only uses 5 bits (2^5 =32 chips), but the chip address must be given to the 10bit chip select address here, which is used for identifying the slave chip internal decoding state machine.

Mode 4: the configuration value is written by a single address of a single chip. Write to an address on a single chip is performed in a similar manner to conventional SPI configuration. Such as the command data format shown in fig. 7.

The above is 4 write configuration modes of the present invention. In order to avoid the problem of disordered phased array functions caused by the completion of the conventional SPI configuration, the invention utilizes a global syncload signal. After the write operation is completed, the configuration value is temporarily stored in a latch, a register or a RAM, but the configuration is not completed, and the final configuration is completed after waiting for the arrival of the syncload and sampling a jump edge from the chip interior to the syncload by SCLK.

In order to ensure the synchronicity of the configuration of the plurality of slave chips, the delay of the sync_load signal output from the master chip to the sync_load pin of each slave chip is as same as possible, and the signal can be arranged in parallel with an SCLK clock signal on a specific PCB, and wiring is generally completed according to a tree structure, so that all the slave chips in the subarray are ensured to complete the configuration simultaneously, as shown in fig. 8.

The read operation is to transfer the register configuration value of the slave chip to the master chip, and since all the SDIO data lines of the slave chips are connected to the same bus, only a single slave chip can be read. The SDIO of the slave chip is a bidirectional IO with three-state output, and the default output is configured into a high-resistance state, so that the SDIO bus conflict is avoided. The read operation includes two modes, described in detail below.

Mode 1: a single chip reads data with consecutive addresses. The master chip broadcasts a read command, each slave chip matches a chip address, and only the chips with the chip addresses respond to subsequent commands. The continuous read command gives a starting register address, after the slave chip with the chip select address accords with the starting register address receives the main chip command, the output state of the SDIO is changed from a high resistance state to a normal output state, the corresponding register configuration is output from the starting address, and the subsequent continuous output is carried out until the register maximum address, such as the data format shown in fig. 9. This mode is mainly used for chip self-checking, so that a lot of master-slave interaction time can be saved.

Mode 2: a single chip reads data at a single address. This mode is the same as a conventional SPI read operation, with the only difference that the chip select operation is not done by CSB, but rather the slave chip of the read operation is selected by broadcasting a slice address, such as the data format shown in fig. 10.

The above 6 read-write mode instructions may be implemented in various manners, for example, the instruction is most simply implemented by all SDIO data, but may also be implemented by sync_load, so that the configuration time is further saved. Similarly, the read-write end flag bit can also be implemented by a combination of sync_load and CSB, for example, the write end flag bit is a combination that CSB is pulled up and sync_load has continuous jump; the end of read flag bit is CSB pulled high and syncload is unchanged.

Claims

1. A simplified phased array multi-chip synchronous configuration method, in which a master chip and a slave chip are included in the phased array, characterized in that:

the main chip at least comprises the following IO pins: a chip selection signal pin, a clock signal pin, a synchronous configuration signal pin and a bidirectional read-write data signal pin which are output in one direction;

the slave chips are array chips which need to complete register configuration in the phased array, and each slave chip comprises the same IO pins: the device comprises a unidirectional input chip address pin, a chip selection signal pin, a clock signal pin, a synchronous configuration signal pin and a bidirectional read-write data signal pin, wherein the number of the slave chip address pins is multiple, and the number of the slave chips which can be accessed by a master chip is determined;

all the chip selection signal pins of the slave chips are connected with the chip selection signal pins of the master chip, all the clock signal pins of the slave chips are connected with the clock signal pins of the master chip, all the synchronous configuration signal pins of the slave chips are connected with the synchronous configuration signal pins of the master chip, and all the read-write data signal pins of the slave chips are connected with the read-write data signal pins of the master chip; the read-write data signal pins of the slave chip are bidirectional IO pins for outputting three states;

the master chip sends addressing information to all the slave chips in a broadcasting mode, and only the slave chips with matched chip addresses can respond to subsequent register addresses and configuration values;

write configuration mode 1: broadcasting and writing continuous address configuration values by long frames;

all slave chips receive and respond to the same broadcast write instruction, which only provides the initial register address bit, and subsequently no longer provides register addresses, but writes a fixed bit width configuration word from the initial register bit;

write configuration mode 2: broadcasting a write configuration value by a single address;

all slave chips receive and respond to the same broadcast write instruction, and only write operation is performed on one address;

write configuration mode 3: writing configuration values by single-chip continuous addresses;

writing a plurality of continuous register addresses of a certain slave chip;

write configuration mode 4: writing configuration values by a single-chip single address;

write operation is performed on a certain address of the single slave chip:

after the writing operation is completed in the four writing configuration modes, the configuration values are temporarily stored in a latch, a register or a RAM, but the configuration is not completed, and the final configuration is completed after waiting for the arrival of a synchronous configuration signal of a main chip and sampling a jump edge of the synchronous configuration signal by a clock signal pin of a slave chip;

read configuration mode 1: reading data from the continuous addresses of the chips;

the master chip broadcasts a read instruction, each slave chip matches a chip address, and only the chips with the chip addresses respond to subsequent commands;

the continuous reading instruction gives out an initial register reading address, a slave chip with which the chip selection address accords receives the reading instruction, the output state of a read-write data signal pin is adjusted from a high-resistance state to a normal output state, corresponding register configuration is output from the initial address, and the subsequent continuous output is carried out until the maximum address of a register;

read configuration mode 2: reading data by a single chip and a single address;

2. The simplified phased array multi-chip synchronization configuration method of claim 1, wherein: the main chip is an FPGA, a CPLD or a singlechip.

3. The simplified phased array multi-chip synchronization configuration method of claim 1, wherein: in order to ensure the synchronism of the configuration of the plurality of slave chips, the delay time of the synchronous configuration signal outputted from the master chip to the synchronous configuration signal pin of each slave chip is as same as possible, and the synchronous configuration signal lines and the clock signal lines are arranged in parallel on a specific PCB (printed circuit board) and are wired according to a tree structure, so that the configuration of all the slave chips is ensured to be completed simultaneously.