CN111881080A

CN111881080A - Integrated circuit chip with on-chip serial bus

Info

Publication number: CN111881080A
Application number: CN202010739410.3A
Authority: CN
Inventors: 湛伟; 马淑彬; 张俐; 夏明刚; 丛伟林
Original assignee: Chengdu Sino Microelectronics Technology Co ltd
Current assignee: Chengdu Sino Microelectronics Technology Co ltd
Priority date: 2020-07-28
Filing date: 2020-07-28
Publication date: 2020-11-03

Abstract

An integrated circuit chip with an on-chip serial bus relates to the integrated circuit technology. The digital function circuit comprises a digital function circuit and an interconnection module which are connected through a wire, wherein the wire is provided with a direction selection driving circuit; the parallel-serial conversion module is a conversion module for converting parallel data into serial data, and the serial-parallel conversion module is a conversion module for converting serial data into parallel data. The invention has the advantages of small occupied chip area, easy interconnection and wiring, simple programming interconnection array and the like.

Description

Integrated circuit chip with on-chip serial bus

Technical Field

The present invention relates to integrated circuit technology.

Background

Between the internal modules of the chip, more signals need to be transmitted and communicated through interconnection.

The most common interconnection Bus in a chip is an advanced micro controller Bus Architecture (AMBA for short) defined by ARM corporation, and includes buses of different applications such as AHB, ASB, APB, AXI, and the like. The buses are parallel buses, and the bus width of 8-1024 bits can be configured.

However, in the circuits such as a Field-Programmable gate array (FPGA) chip, a multi-core CPU chip, and the like, firstly, the bus width even reaches 512-2048 bits, which exceeds the maximum width of the current parallel buses such as the AMBA and the like; secondly, when the parallel buses with larger width are interconnected, a large chip area is occupied.

Disclosure of Invention

The technical problem to be solved by the invention is to provide a chip internal interconnection scheme with small occupied area.

The integrated circuit chip with the in-chip serial bus comprises a digital functional circuit and an interconnection module which are connected through a wire, wherein the wire is provided with a direction selection driving circuit; the parallel-serial conversion module is a conversion module for converting parallel data into serial data, and the serial-parallel conversion module is a conversion module for converting serial data into parallel data.

The on-chip serial bus circuit is particularly suitable for interconnection and communication among programmable logic arrays and CPU cores of chips such as an FPGA (field programmable gate array) and a multi-core CPU (central processing unit). The invention overcomes the defects of large chip area occupied by multi-bit wide parallel data buses, difficult interconnection wiring, complicated programming interconnection array and the like; the method has the advantages of small occupied chip area, easy interconnection and wiring, simple programming interconnection array and the like. The circuit can be completely realized based on a digital circuit, is simpler than a traditional serial bus applicable outside a chip, is convenient for transplanting different processes, and has the advantages of lower power consumption and the like.

Drawings

Fig. 1 is a schematic diagram of the present invention.

Fig. 2 is a circuit diagram of a parallel-to-serial conversion module.

Fig. 3 is a timing diagram of a parallel to serial circuit.

Fig. 4 is a schematic structural diagram of a serial-to-parallel conversion module.

Fig. 5 is a timing diagram of a serial to parallel circuit.

Fig. 6 is a schematic structural diagram of the embodiment.

Detailed Description

In the prior art, a serial bus is generally used in the fields of chip-to-chip, chip-to-optical module, chip-to-chip interconnection via long traces of a Printed Circuit Board (PCB), and the like. Since the attenuation of the high-speed serial wires is severe, the serial bus communication needs complex circuits such as pre-emphasis and equalization. However, the internal environment of the chip is different from the external serial bus environment, and the actual requirements for the driving capability of the Transmitter (TX) and the balancing capability of the Receiver (RX) are lower. Therefore, the disadvantages of the serial bus structure can be tolerated, and the advantages of the serial bus can be fully utilized.

The integrated circuit chip is characterized in that a sending port of the digital function circuit is connected to the direction selection driving circuit through a parallel-serial conversion module, and a receiving port of the digital function circuit is connected to the direction selection driving circuit through a serial-parallel conversion module; the parallel-serial conversion module is a conversion module for converting parallel data into serial data, and the serial-parallel conversion module is a conversion module for converting serial data into parallel data.

See fig. 1. The digital function circuit A (101), the parallel-to-serial circuit (102), and the serial-to-parallel circuit (103) are provided at one end of the serial bus.

The digital function circuit B (106), the parallel-to-serial circuit (105) and the serial-to-parallel circuit (104) are arranged at the other end of the serial bus.

Parallel data [2n:0] of the digital functional circuit A (101) is converted into serial data through a parallel-to-serial circuit (102), and reaches a serial-to-parallel circuit (104) of a receiving end through an on-chip connecting line. Serial to parallel circuitry (104) recovers the serial data into parallel data [2n:0] and passes to digital function circuitry B (106).

When the data is transmitted in the reverse direction, the parallel data [2n:0] of the digital function circuit B (106) is converted into serial data through the parallel-to-serial circuit (105), and reaches the serial-to-parallel circuit (103) of the receiving end through the on-chip connection. The serial to parallel circuit (103) recovers the serial data into parallel data [2n:0] and passes it to the digital function circuit B (101).

Thereby enabling interconnection and communication between digital function circuit a (101) and digital function circuit B (106).

The parallel-to-serial circuit is shown in fig. 2, and here, for example, 4-bit parallel data is converted into serial data.

The parallel data input from the digital function circuit are D0, D1, D2, D3.

The parallel data D [0] is output as D [0] a after passing through the first flip-flop 201,

d1 is output as D1 a after passing through the third flip-flop 203,

d2 is output as D2 a after passing through the second flip-flop 202 and the fifth latch 205,

d [3] passes through the fourth flip-flop 204 and the sixth latch 206 and is output as D [3] a.

Under the control of the clock clk/4, the seventh multiplexer 207 gates D [0] a and D [2] a, the first period selects data D [0] a to be output, the second period selects data D [2] a to be output, and so on. The output signal of the seventh recombiner 207 is D [02 ].

Similarly, the eighth recombiner 208 gates D [1] a and D [3] a, the first period selects data D [1] a for output, the second period selects data D [3] a for output, and so on. The output signal of the eighth recombiner 208 is D [13 ].

D02 is output as D02 a after passing through the ninth flip-flop 209,

d [13] passes through the tenth flip-flop 210 and the eleventh latch 211 and is output as D [13] a.

Under the control of the clock clk/2, the twelfth multiplexor 212 gates D [02] a and D [13] a, the first period selects data D [02] a to be output, the second period selects data D [13] a to be output, and so on. The output signal of the twelfth recombiner 212 is ds.

D [ s ] passes through the thirteenth flip-flop 213 and the driving circuit 214, and then outputs a signal D [ out ].

D [ out ] is serial data that completely contains the information D [0], D [1], D [2], D [3], thus realizing the conversion of parallel data into serial data.

The above described sequence is shown in fig. 3.

The clock clk outputs the clock clk/2 after passing through the divide-by-2 circuit 215, i.e. the frequency is reduced to 1/2 of clk, and the period is 2 times clk.

The clock clk/2 passes through the divide-by-2 circuit 216 to output a clock clk/4, which is 1/2 with a reduced frequency of clk/2 and a period of 2 times clk/2.

The serial data D [ out ] reaches the receiving end after being routed in the chip and is marked as a signal D [ in ].

A serial to parallel circuit is shown in fig. 4.

The input parallel data D [ in ] passes through a signal amplification circuit 401 and then enters a phase detection circuit 402.

The principle of phase detection is to sample the input signal by a plurality of clocks of the same frequency but of equal phase difference. In this example, the clocks with the same frequency and the same phase difference are Clk0, Clk90, Clk180 and Clk 270. The clocks Clk0, Clk90, Clk180 and Clk270 have the same frequency and are sequentially shifted in phase by 90 degrees.

The output signals of the phase detection circuit 402 are Cdata _ even, Cdata _ odd, Edata _ even, Edata _ odd.

Cdata _ even, Cdata _ odd are the even bit and odd bit obtained after the serial data center sampling, respectively.

Edata _ even and Edata _ odd are even bits and odd bits obtained after edge sampling of serial data, respectively.

The input data D [ in ] are D0, D1, D2, D3, D4, D5 and D6 in sequence, and after passing through the phase detection circuit 402, the Cdata _ even data are D0, D2, D4 and D6 in sequence; the Cdata _ even data is d1, d3, d5, d7, and so on.

The principle of Edata _ even, Edata _ odd is similar to Cdata _ even, Cdata _ odd, except that the sample points are closer to the edge positions of the data.

After Cdata _ even, Cdata _ odd, Edata _ even, Edata _ odd passes through the de-multiplexer and synchronization logic 403, the recovered parallel data D [0], D [1], D [2], D [3] are obtained, thus realizing the conversion of the parallel data into serial data.

The clock generation and phase adjustment logic 404 functions to generate multi-phase clocks of the same frequency but of equal phase difference; and along with the data edge change of the input data D [ in ], the second function is to adjust the phase of the multi-phase clock through the phase adjustment logic so as to better sample the data center and the edge.

The sequence of the serial to parallel circuit is shown in fig. 5.

The rising edge of clock Clk0 samples D0 of D [ in ], the rising edge of clock Clk90 samples D1 of D [ in ], the rising edge of clock Clk180 samples D2 of D [ in ], and the rising edge of clock Clk270 samples D3 of D [ in ].

And obtaining Cdata _ even, Cdata _ odd, Edata _ even and Edata _ odd signals corresponding to D [ in ] after clock sampling. In FIG. 5, Cdata _ even is d0, d2, d 4; cdata _ odd is d1, d3, d 5.

Chips interconnected by an on-chip serial bus are shown in fig. 6, for one embodiment.

The digital function circuit 601 is represented in fig. 6 by coordinates x0y0, x1y0, x2y0, x0y1, x1y1, x2y1, x0y2, x1y2, x2y 2.

The digital function circuit 601 may be a programmable logic resource module in an FPGA chip, or may be a single CPU core in a multi-core CPU chip, or the like.

The digital function circuits 601 may be the same digital function circuit or may be different digital function circuits.

The digital function circuit 601 may have one or more of a parallel to serial circuit 602, a serial to parallel circuit 603.

The output parallel signal of the digital function circuit 601 passes through the parallel-to-serial circuit 602 and then reaches the driving circuit 604 with directivity of inter-chip wiring, and the driving circuit 604 with directivity of inter-chip wiring is controlled by the register, and the strobe serial signal comes from the parallel-to-serial circuit 602 or is a signal on the east and west or south and north wiring. In fig. 6, the drive circuits are labeled 1 and 2, and only the signal direction is different, as indicated by the arrows in the figure.

The interconnect block 605, which is also a directional array of driver circuits, functions to gate the east, west, south and north traces through register control, e.g., select the w1 input and the s4 output.

The east-west traces 606 and the south-north traces 607 are respectively 4 traces in the example of fig. 6, and can be increased or decreased as needed, for example, the number of the traces is decreased to only 2, that is, as shown in fig. 1.

The present invention can be implemented by those of ordinary skill in the art through the specification and drawings. Digital function circuits, interconnection modules, direction selection driving circuits (including control of direction selection) belong to the prior art, and are not described herein again.

Claims

1. The integrated circuit chip with the on-chip serial bus comprises a digital function circuit and an interconnection module which are connected through a wire, wherein the wire is provided with a direction selection driving circuit; the parallel-serial conversion module is a conversion module for converting parallel data into serial data, and the serial-parallel conversion module is a conversion module for converting serial data into parallel data.