DE102016208864A1 - computer unit - Google Patents

Abstract

A computing unit (2) comprising a first pipeline-capable arithmetic core (4) with a first memory element (8) and a second pipeline-capable arithmetic core (6) with a second memory element (10) is proposed. The first arithmetic core (4) is adapted to begin a pipeline execution of a command (14), wherein the second arithmetic core (6) is adapted to begin a redundant pipeline execution of the command (14). A comparator unit (20) is configured to determine a deviation (CMP = 0) between a first state (16) of the first memory element (8) and a second state (18) of the second memory element (10), wherein the first and the second arithmetic core (4, 6) is adapted to start a pipeline renewal execution of the command (14) when the deviation (CMP = 0) is detected.

Description

State of the art

The invention relates to a computing unit according to the preamble of claim 1.

It is known that a first arithmetic kernel is monitored by a second arithmetic kernel in a lockstep method to detect errors such as random permanent hardware errors and transient errors caused, for example, by a neutron or an alpha particle. For this purpose, the second arithmetic kernel is constructed essentially redundantly to the first arithmetic kernel and executes the same commands as the first arithmetic kernel.

Disclosure of the invention

The problem underlying the invention of the prior art is solved by a computing unit according to claim 1.

It is proposed that a first pipeline-capable computation core is configured to start a pipeline execution of an instruction that a second pipeline-capable computation core is configured to start a redundant pipeline execution of the instruction that a comparator unit is configured to determine a deviation between a first state of the first memory element and a second state of the second memory element, and that the first and the second arithmetic core are adapted to start a pipeline renewed execution of the command when the deviation is detected ,

In this way, a transient error can be detected in a timely manner by comparing the speculative data in the memory elements. By restarting the pipeline execution of the command, a countermeasure for correcting the detected transient error is also promptly initiated. Thus, transient errors are already handled and resolved in the area of the respective pipeline. In particular, the occurrence of a transient error does not become architecturally visible outside the computing cores, which means that corrupted results are not visible outside of the arithmetic unit due to a transient error. The existing lockstep architecture is thus improved and a tolerance for transient errors is created.

In an advantageous embodiment, the comparator unit is designed to determine a match between the first state of the first memory element and the second state of the second memory element after the beginning of the pipeline's renewed pipeline execution. The first and second arithmetic kernels comprise a writeback unit configured to write a result of the pipeline execution of the instruction to a respective output memory area when the match is determined. As a result, it is advantageously achieved that rapid recuperation of the arithmetic unit is possible even when transient errors occur. This is further advantageously achieved with little time, since in principle not much more than twice the time is needed, which is needed for one-time pipeline execution of the command.

In an advantageous embodiment, the comparator unit is designed to determine a renewed deviation after the pipelined execution of the instruction by the first and second calculation kernels. Thus, a permanent error can be inferred that affects at least one of the two calculation cores.

In an advantageous embodiment, the first and the second arithmetic kernel are designed to interrupt the pipeline processing of further commands which were started after the command, depending on the determination of the deviation. This ensures that no erroneous data generated by processing the other commands is written to the outside and therefore visible.

In an advantageous embodiment, the comparator unit can be executed before the writeback unit for pipeline execution of the instruction. As a result, it is advantageously achieved that a comparison of the states in the two computing cores is carried out even before the production of an outwardly visible state of the computing cores.

In an advantageous embodiment, an execution unit for executing the instruction is formed, wherein for pipeline execution of the instruction, the comparator unit is executable after the execution unit. Thus, the states of the memory elements are compared in a pipeline area which is at the end of the respective pipeline.

In an advantageous embodiment, the first and the second arithmetic core are designed to mark a memory area of the first and second memory element affected by the deviation as defective when the deviation is determined. Thus, it can be advantageously avoided that a faulty state of the memory element of pipeline stages is used in subsequent pipeline executions of further instructions.

In an advantageous embodiment, the first and the second arithmetic core are clock-synchronized. Thus, the comparison unit can be executed at a substantially same time and there are no disadvantageous synchronization problems and / or time delays.

In an advantageous embodiment, the first and the second arithmetic core are operated with a clock offset. This can advantageously be detected suddenly occurring errors that can affect both cores in the same way. This results in advantages in error detection and reliability.

Further embodiments and examples of the invention are shown in the following description of the figures. Here, the same reference numerals are used in different embodiments. In the drawing show:

1 and 2 each schematically a computing unit;

3 a comparator unit;

4 schematically a first and a second pipeline;

5 in schematic form, a pipeline execution;

6 a schematic block diagram;

7 a schematic flow diagram; and

8th in schematic form, a content of a repeat buffer.

1 schematically shows a computing unit 2 with a first pipeline-capable core 4 and a second pipeline-ready kernel 6 , The first calculation kernel 4 comprises a first memory element 8th , The second processor 6 includes a second memory element 10 , An input unit 12 leads both cores 4 and 6 the same command 14 to. The command 14 is for pipeline execution within the respective calculation kernel 4 and 6 intended. This will be a redundant pipeline execution of the command 14 through the cores 4 and 6 carried out.

Depending on the pipeline execution of the command 14 takes the storage element 8th a condition 16 one. Depending on the pipeline execution of the command 14 takes the storage element 10 the condition 18 one. The conditions 16 and 18 become a comparator unit 20 fed. The comparator unit 20 compares the first state 16 with the second state 18 and generates a signal CMP in response to the comparison. The signal CMP either shows a deviation between the first state 16 and the second state 18 or a match of the first state 16 and the second state 18 at. The signal CMP becomes the two calculation cores 4 and 6 fed. The conditions 16 and 18 are a respective content of a selected register or memory area of the respective memory element 8th . 10 ,

The signal CMB shows a match between the first state 16 and the second state 18 and if the command was executed the first time, no error is detected and the pipeline execution of the command 14 so that the calculated result is "committed", that is, written back to an output memory area in a corresponding pipeline stage.

Has now been begun, the pipeline execution of the command 14 by means of the calculation kernels 4 and 6 and by means of the comparator unit 20 a match of the states 16 and 18 after starting the pipeline's pipeline execution again 14 determined, then becomes a respective result 22 and 24 the pipeline execution of the command 14 written in the output memory area, not shown. The beginning of the re-pipeline execution is determined by the previously determined deviation of the states 16 and 18 triggered by the signal CMP.

Will after re-pipelining the command 14 on the other hand, through the cores 4 and 6 a new deviation is determined according to the signal CMP, it is concluded that a permanent error, in particular a hardware defect at least one of the two calculation cores 4 and 6 concerns.

The memory elements 8th and 10 may be part of a respective bypass network, for example. Alternatively or additionally, the memory elements 8th and 10 the respective results 22 and 24 before they are "committed" and written to the output memory area.

The arithmetic unit 2 is in particular part of a control device for a motor vehicle. By the proposed treatment of transient errors by means of the comparator unit 20 it is possible to increase the availability of the overall system as well as to improve the fault tolerance. In particular for a control unit which performs functions for autonomous or highly autonomous driving, the arithmetic unit described here is 2 advantageous. Advantageously, the user experience of the driver is improved, which is informed only about errors, which are not recoverable. Transient errors, however, drivers are not brought to the notice. This is achieved in particular by the fact that transient errors are eliminated quickly and need not be brought to the attention of the driver. In particular, the reaction times required for autonomous driving by the arithmetic unit 2 be respected.

2 shows an alternative embodiment of the arithmetic unit 2 , In contrast to 1 includes the first calculation kernel 4 a comparator unit 20A which analogous to the comparator unit 20 generates a signal CMPA analog to the signal CMP. Accordingly, the second calculation kernel comprises 6 a comparator unit 20B which analogous to the comparator unit 20 and generates a signal CMPB analog to the signal CMP. The signals CMPA and CMPB are in the respective processor cores 4 and 6 used to decide if a repetition of the pipeline execution of the command 14 is carried out.

3 shows by way of example the comparator unit 20 , The conditions 16 and 18 become an XNOR block 26 fed. The XNOR block 26 generates logical-1 (true) if the two states supplied 16 and 18 to match. Voices the two states 16 and 18 do not match, so does the XNOR block 26 Logical-0 (false).

4 schematically shows a first pipeline 30 of the first calculation kernel 4 and a second pipeline 32 the second processor core 6 , Both processor cores 4 and 6 are clock-synchronized, which means among other things that the clock signals CLK1 and CLK2 are substantially the same. The command 14 is loaded in a command load stage IF. In a decode stage D following the instruction load stage IF, the loaded instruction becomes 14 decoded and required data is loaded into corresponding processor core registers. In an execution stage E, the command becomes 14 executed. In a memory access stage M following the execution stage E, a memory is accessed and a determination of a checksum is performed. By calculating the checksum are the respective results 22 . 24 after leaving the calculation kernel 4 . 6 plausibilisierbar. This means that in a comparison stage CM following the memory access stage M, the comparator unit 20 corresponds, the states become 16 and 18 the memory elements 8th and 10 compared with each other and in response thereto, after the comparison stage CM, a write-back stage WB is executed to obtain the result of the pipeline execution of the instruction 14 to write to the output memory area.

This is at the pipeline execution of the command 14 the comparator unit 20 executable before a writeback stage WB corresponding write-back unit. An execution unit, not shown, is for executing the instruction 14 formed according to the execution stage E. The comparator unit 20 for pipeline execution of the command 14 is executable after the execution unit. The first and the second arithmetic kernel 4 and 6 In particular, clocks are synchronized in such a way that before the execution of the comparison stage CM, the state 16 . 18 the respective memory elements 8th and 10 is fixed. Alternatively, the cores can 4 and 6 also operate with a substantially constant clock skew, which means that the individual pipeline stages for redundant execution of the command 14 not simultaneously but with a time delay.

5 schematically shows a pipeline execution in the processor core 4 when a transient error F occurs. The error F occurs, for example, during the execution of the command 14 in the execution stage E and is recognized in the comparison stage CM. Upon detection of the error in the comparison stage CM was already in the pipeline execution of the commands 34 . 36 . 38 and 40 began. Since now a deviation of the states of the memory elements 8th and 10 was determined, the pipeline processing of other commands 34 - 40 which after the command affected by the error F. 14 started, canceled. A loading of another command 42 omitted. Rather, after the determination of the error F in the comparison stage CM, an error flag POIS is set for one clock cycle in order to prevent any execution of a pipeline stage or at least to prevent the writing back of a result in the write-back stage WB. Alternatively, it can first be determined which commands are from the differing states 16 and 18 are concerned, ie the corresponding data dependencies are checked in order to subsequently terminate or discard only those processing instructions which differ from the differing states 16 and 18 are affected.

From time TS, a repetition of the pipeline execution of the command 14 started, during which repetition a flag REPL is set to logical-1. If either the error flag POIS or the flag REPL is set to logical-1, another flag RET is reset to logical-0. After a successful pipeline execution of the command 14 without the detection of an error F in the comparison stage CM, the pipeline execution of instructions can be continued normally. In particular, the commands 34 - 42 come now to the processing. Before a writeback, the write-back stage WB always checks whether the RET flag is set and a writeback occurs only if the RET = 1 flag is set.

The instruction load stage IF also checks if the flag RET is set. If the flag RET is set to logical-0, then the flag REPL is set to logical-1. The loading of a command provided without the detected deviation is not performed. Rather, the command is 14 reloaded, which starts the pipelined pipeline execution of the command. Only after a successful write back of the result of the pipeline execution of the command 14 the flag REPL is set to logical-0 in the write-back stage WB.

If during the repetition phase (REPL = 1) another error in the comparison stage CM are detected, it is concluded that a permanent error and another unit can take appropriate action and shut down, for example, the system in particular the controller in an orderly manner. Of course, the number of repetitions is the execution of the command 14 adjustable.

6 shows a schematic block diagram 50 for generating the flag RET. The block diagram 50 is in particular part of the comparison unit 20 , The signal CMP is negated an AND block 52 fed. Furthermore, the block 52 the flag REPL negated supplied. An AND block 54 the flag REPL and a flag MISM negated is supplied. The flag MISM is set to logical 0 as soon as a first iteration of the pipeline execution of the instruction 14 was successfully carried out. The results of the blocks 52 and 54 become an OR block 56 supplied, which generates the flag RET.

7 shows a schematic flow diagram 58 to explain the function of the comparator unit 20 , According to a block 60 begins a first pipeline execution of the command 14 , In a block 62 it is decided if the memory elements 8th and 10 have a same state. If this is the case, then in a block 64 the result of pipeline execution of the command 14 in the write-back stage WB are written back to the output memory area. However, the conditions are different 16 and 18 the memory elements 8th and 10 , so according to the block 66 a repetition of the pipeline execution of the command 14 through the two cores 4 and 6 instead of. In a block 68 it is determined if the states 16 and 18 the memory elements 8th and 10 to match. If this is the case, then according to the block 70 the result of pipeline execution of the command 14 written back in the write-back stage WB in an output memory area. However, if there is a deviation of the states 16 and 18 from each other, so will in the block 68 decided in the block 72 switch. In the block 72 it is determined that there is a permanent error.

8th shows in schematic form a content of a repeat buffer 80 , This replay buffer 80 includes the flag REPL, an address 90 of the command to be repeated 14 as well as the flag MISM and is from the comparator unit 20 used.

Claims (10)

One arithmetic unit ( 2 ) comprising a first pipeline-capable computation kernel ( 4 ) with a first memory element ( 8th ) and a second pipeline-capable compute kernel ( 6 ) with a second memory element ( 10 ), - where the first calculation kernel ( 4 ) is adapted to execute a pipeline execution of an instruction ( 14 ), and - wherein the second arithmetic kernel ( 6 ) is adapted to perform a redundant pipeline execution of the instruction ( 14 ), characterized in that - a comparator unit ( 20 ) is adapted to cause a deviation (CMP = 0) between a first state ( 16 ) of the first memory element ( 8th ) and a second state ( 18 ) of the second memory element ( 10 ), and - that the first and second arithmetic kernels ( 4 . 6 ) are adapted to re-pipeline the instruction ( 14 ) when the deviation (CMP = 0) is determined. The arithmetic unit ( 2 ) according to claim 1, - wherein the comparator unit ( 20 ) is adapted, after the start of the pipeline's pipeline execution ( 14 ) a match (CMP = 1) between the first state ( 16 ) of the first memory element ( 8th ) and the second state ( 18 ) of the second memory element ( 10 ), and - wherein the first and second arithmetic kernels ( 4 . 6 ) comprise a writeback unit which is adapted to generate a result ( 22 . 24 ) pipeline execution of the command ( 14 ) in a respective output memory area when the match (CMP = 1) is detected. The arithmetic unit ( 2 ) according to claim 1 or 2, - wherein the comparator unit ( 20 ) is adapted, after re-pipelining the instruction ( 14 ) by the first and second arithmetic kernels ( 4 . 6 ) to determine a new deviation (CMP = 0). The arithmetic unit ( 2 ) according to one of the preceding claims, - wherein the first and the second arithmetic kernel ( 4 . 6 ) are adapted, depending on the determination of the deviation (CMP = 0), the pipeline processing of further commands ( 34 - 40 ), which after the command ( 14 ) were canceled. The arithmetic unit ( 2 ) according to one of the preceding claims, - wherein for pipeline execution of the command ( 14 ) the comparator unit ( 20 ) is executable before a writeback unit. The arithmetic unit ( 2 ) according to one of the preceding claims, - an execution unit for executing the command ( 14 ), and wherein for pipelining the instruction ( 14 ) the comparator unit ( 20 ) is executable after the execution unit. The arithmetic unit ( 2 ) according to one of the preceding claims, - wherein the first and the second arithmetic kernel ( 4 . 6 ) are adapted to a memory area affected by the deviation (CMP = 0) of the first and second memory elements ( 8th . 10 ) as faulty if the deviation (CMP = 0) is determined. The arithmetic unit ( 2 ) according to one of the preceding claims, - wherein the first and the second arithmetic kernel ( 4 . 6 ) are clock-synchronized. The arithmetic unit ( 2 ) according to one of claims 1 to 7, - wherein the first and the second arithmetic kernel ( 4 . 6 ) are operated with a clock offset. A control device for a motor vehicle comprising a computing unit ( 2 ) according to any one of the preceding claims.

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