CN206833419U - Dual redundant streamline based on checkpoint technology - Google Patents

Abstract

A kind of dual redundant streamline based on checkpoint technology, it is characterised in that：The dual redundant streamline based on checkpoint technology includes assembly line A, streamline B, instruction buffer (301), back-up registers group (401), CL Compare Logic (501), Write post (601), data buffer storage (701) and register file (801)；The dual redundant streamline based on checkpoint technology is backed up using back-up registers to the content of the level inter-register of streamline, single-particle failure in pipelined units is detected by CL Compare Logic, the method recovered using the value in back-up registers group to streamline, SEU, SET and MBU failure that single particle effect triggers are carried out fault-tolerant.

Description

Dual redundant streamline based on checkpoint technology

Technical field

Detection and the recovery device of a kind of microprocessor pipeline mistake are the utility model is related to, more particularly to it is a kind of The detection of streamline mistake and recovery device in SPARC V8 processors.

Background technology

Single-particle inversion (Single Event Upset, SEU) is under space application environment, because single-particle incidence is led The event of memory cell generation Data flipping mistake in integrated circuit is caused, is that electronic system breaks down and worked under space environment One of abnormal major incentive.With the fast development of semiconductor process technique, the size of chip is constantly reducing, processor work Working frequency improves constantly, and the reduction of node operating voltage make it that single-particle inversion phenomenon is increasingly severe.Single-particle bombards flowing water The combinational logic part of line, causes signal to disturb, it is possible to can be latched by level inter-register and SET failures occur, cause to flow There is mistake in waterline.Single-particle bombards level inter-register, inverts its content deposited, causes SEU and MBU failures.Grind Study carefully and point out, in nanoscale chip, long numeric data upset (MBU) probability is also improving rapidly caused by single-particle inversion, can lead Most 8 random data upset mistakes are caused, bigger harm is produced to the electronic system of space application.In microprocessor and electronics Take reinforcement measure to carry out fault-tolerant design to single-particle failure in system turns into important technological means.

As the important component of Modern microprocessor, the instruction stream that streamline mainly completes program code performs, and Implementing result is write into data storage and register file.Draw if single-particle bombardment streamline causes grade inter-register that upset occurs The wrong data of hair is latched, and it is incorrect to may result in streamline implementing result, pipelined units are carried out it is not fault-tolerant plus Gu in the case of, the implementing result of mistake will be diffused into data storage and register file or perform the instruction stream of mistake, enter And more uncontrollable mistakes are caused to produce.Therefore, for the highly reliable microprocessor of space application, streamline list is carried out The fault-tolerant design of member has great importance.

The existing reinforcement technique to space microprocessor has following three kinds of schemes：Using time-based fault-tolerance approach, energy Effectively solves the problems, such as MBU, but processor performance substantially reduces；Using the fault-tolerance approach based on coding, can only effectively verify The correctness of calculating section, and different coded systems can not be handled all for different single-particle failures, fault-tolerant ability It is limited；Using the scheme based on hardware redundancy, during register stage triplication redundancy, MBU failures can not be tackled；The mould of pipeline stages three is superfluous Remaining, although failure streamline can be oriented, the expense such as hardware resource power consumption is larger；Pipeline stages duplication redundancy can answer It to MBU failures, but can not position, not have the effect of shielding failure, stream can be dramatically increased by carrying out streamline rollback every time Waterline performance cost, especially in the case where single-particle failure is increasingly common disposed of in its entirety speed can be caused substantially to reduce.From Dual redundant streamline (Self-Recovery Dual Pipeline, SRDP) is repaired on the basis of dual redundant streamline, is passed through CL Compare Logic detects failure, self checking logic positioning failure, realizes and mistake caused by SET, SEU, MBU failure is performed, Although SRDP has serial, self checking the coding of good fault-tolerant effect, CL Compare Logic and function logic to single-particle failure The streamline recovery operation of logic and complexity causes the dominant frequency of processor to decline by a big margin.In a word, prior art can not be real Existing one with bottom surface product, low performance overhead and the CPU Scheme of Strengthening for successfully managing SEU, SET and MBU failure.

The content of the invention

The purpose of this utility model is to design a kind of dual redundant streamline based on checkpoint technology, can be from system knot Effectively shielding single-event transients (SET), single-particle inversion (SEU), long numeric data overturn failure caused by (MBU) on structure, and Logical delay is reduced, improves operating rate.

To achieve the above object, technical scheme is used by the utility model：

A kind of dual redundant streamline based on checkpoint technology, it is characterised in that：It is described based on the double superfluous of checkpoint technology Residual current waterline includes assembly line A, streamline B, instruction buffer (301), back-up registers group (401), CL Compare Logic (501), write Cache (601), data buffer storage (701) and register file (801)；The assembly line A includes fetching section (101), decoding section (102) section (103), memory access section (104), are performed, writes back (105) five flowing water sections of section；The streamline B includes fetching section (201), decoding section (202), perform section (203), memory access section (204), write back (205) five flowing water sections of section；Data buffer storage (701) Shared with register file (801) by assembly line A and streamline B, under normal circumstances, default write enters assembly line A during execute instruction stream Implementing result；The instruction buffer (301) is used for the code for storing streamline execution, enters with fetching section (101) in assembly line A Row data interaction, assembly line A are distributed to two streamlines execution after taking out instruction；The back-up registers group (401) is with the cycle Granularity backs up to the level inter-register of assembly line A, once CL Compare Logic (501) detects single-particle failure, by backup Content recovery is into assembly line A and streamline B level inter-register, and streamline normally performs after 2 cycles；The CL Compare Logic (501) it is arranged between assembly line A and streamline B, contrasts the level inter-register content of two streamlines, detection single-particle event Barrier；The Write post (601) is arranged on the entrance of data buffer storage (701) and register file (801), is provided for keeping in streamline Update the data；The data buffer storage (701) is used for the data for storing streamline output, and provides arithmetic operation to streamline Number；The register file (801) is used for the data for storing streamline output, and provides arithmetic operation number to streamline.

A kind of dual redundant streamline based on checkpoint technology that the utility model is realized, in embedded microprocessor, By the information back-up of level inter-register into back-up registers group, once comparator detects single-particle failure, backup is deposited Information recovering in device group can not only shield single-particle bombardment streamline list into the corresponding level inter-register of two streamlines SET, SEU and MBU failure caused by member, so as to improve the reliability that microprocessor is applied under the adverse circumstances such as space, Also reduce fault detect and streamline recovers the complexity of function, reduce logical delay, lift the work dominant frequency of processor.

Brief description of the drawings

Fig. 1 is five-stage pipeline structure chart；

Fig. 2 is SRDP structure charts；

Fig. 3 is according to the dual redundant pipeline organization figure of the present utility model based on checkpoint technology；

Fig. 4 is Failure detection and recovery mechanism structure figure；

Fig. 5 is the SEU/MBU Failure detection and recovery timing diagrams of grade inter-register；

Fig. 6 is the SET Failure detection and recovery timing diagrams of function logic；

Fig. 7 is Write post fault-tolerant architecture figure；

Fig. 8 is the SEU/MBU fault-tolerant timing diagram of Write post；

Fig. 9 is the SET fault-tolerant timing diagram of Write post.

Embodiment

The present embodiment combines a kind of embedded microprocessor LEON2 of SPARC V8 architectures to tool of the present utility model Body embodiment illustrates.The embedded microprocessor LEON2 of the SPARC V8 architectures uses the RISC Architecture of 32, Its pipelined units is classical five-stage pipeline, each pipelining-stage and instruction buffer, data buffer storage and the register of streamline Heap carries out data interaction.

The pipelined units of LEON2 processors include fetching (IF), decoding (ID), perform (EX), memory access (ME), write back (WR) five groups of level inter-registers IF, IF/ID, ID/EX, the EX/ set between five combinatorial logic units, and each pipelining-stage ME, ME/WR, its structure are as shown in Figure 1.The combinational logic part of single-particle bombardment streamline causes SET failures, it is possible to can quilt Level inter-register, which latches, causes streamline mistake.Single-particle bombards level inter-register, overturns its content deposited, causes SEU and MBU failures.Key message caused by combinational logic will be transmitted by level inter-register between pipelining-stage, be deposited between level Error message in device causes pipelined units to perform the result that makes mistake, and arrives data storage or deposit in the renewal of ME or WR sections Device heap.Meanwhile the mistake of IA disorder may cause the execution sequence of instruction stream to make a mistake.

Selfreparing dual redundant streamline (Self-Recovery Dual Pipeline), abbreviation SRDP, its structural representation As shown in Figure 2.Thoughts of the SRDP based on hardware redundancy, traditional pipeline stages dual modular redundancy is improved, at two Set comparator to carry out fault detect to pipelined units between streamline, school is carried out to level inter-register using self checking module Assay position to be out of order streamline, streamline recovered according to comparative result and self checking error message, realize to SET, Mistake caused by SEU, MBU failure is performed, although SRDP has good fault-tolerant effect, CL Compare Logic to single-particle failure The dominant frequency of processor is caused to decline with serial, self checking the codimg logic of function logic and the streamline recovery operation of complexity Amplitude is very big.

The utility model is directed to the defects of SRDP fault freedoms, on the basis of fault-tolerant effect is ensured, with the fault-tolerant time Expense is cost, avoids the fault-tolerant logic of complexity and causes processor performance to be greatly lowered, and proposes that one kind is based on checkpoint technology Dual redundant streamline.

Dual redundant streamline based on checkpoint technology is based on pipeline stages duplication redundancy, performs identical parallel Instruction stream, the level inter-register of two streamlines is contrasted to detect single-particle failure by comparator.With cycle granularity level The content of register is backed up, and when detecting single-particle failure, streamline is recovered using 2 cycles.To avoid Dirty data flows out streamline, and Write post is set in the entrance of data buffer storage and register file, ensures that information can by postponing to write By property.Relative to SRDP schemes, this scheme eliminates self checking logic, parallel perform function logical AND CL Compare Logic and simplification Streamline Restoration Mechanism, introduce less delay to the critical path of processor, relative to LEON2 prototypes, this scheme is realized The clock frequency of processor be reduced only by 9.8%, area overhead increase by 66% or so.Compared with DMR and SRDP, carried in performance 36.9% and 70.3% are risen.With the rapid development of integrated circuit, area overhead is no longer the bottleneck of fault-tolerant processor design, The performance cost of fault-tolerant networks is bigger for the meaning of processor, and smaller critical path delay means the disposal ability of processor It is stronger.Therefore, advantage is had more in terms of area and performance cost based on the level inter-register back mechanism of cycle granularity.

Based on above-mentioned general principle with setting, one kind of the dual redundant streamline of the present utility model based on checkpoint technology Embodiment is as follows：

In the embedded microprocessor of SPARC V8 architectures, pipelined units are arranged to as shown in figure 3, main Including assembly line A, streamline B, instruction buffer (301), back-up registers group (401), CL Compare Logic (501), Write post (601), data buffer storage (701) and register file (801).

Assembly line A and streamline B include fetching (IF), decoding (ID), perform (EX), memory access (ME), write back (WR) combination The level inter-register (IF, IF/ID, ID/EX, EX/ME, ME/WR) set between logic unit, and each pipelining-stage.Two streams Waterline possesses respective data path, while shared instruction caching, data buffer storage and register file.It is parallel to perform same instructions Stream, and give tacit consent to and carry out data interaction, streamline B with instruction buffer, data buffer storage and register file with the implementing result of assembly line A For backup units.

Instruction buffer (301) is used for the code for storing streamline execution, and data interaction, stream are carried out with IF sections in assembly line A Waterline A is distributed to two streamlines execution after taking out instruction.

Back-up registers group (401) is backed up with cycle granularity to the level inter-register of assembly line A, once CL Compare Logic (501) single-particle failure is detected, by the content recovery of backup to assembly line A and streamline B level inter-register, 2 week Streamline normally performs after phase, so as to avoid failure accumulation and propagation effect.

CL Compare Logic (501) is arranged between assembly line A and streamline B, in the level inter-register for contrasting two streamlines Hold, so as to detect single-particle failure.Because fetching section needs to take out instruction, decoding section from instruction buffer according to IA The extract operation number from register file is needed, section is performed and memory access Duan Junhui produces the information interacted with instruction buffer, write back section meeting Register file is arrived into implementing result renewal.Therefore, it is necessary to which the level inter-register of Pyatyi is contrasted, streamline is avoided to occur altogether Wrong data renewal is arrived data storage and register file by mould mistake.

Write post (601) must assure that data buffer storage (701) and register file (801) will not provide by pipelined units Mistake updates.Set 1 Write post and register file entrance that 2 Write posts are set in data buffer storage entrance respectively, for caching Streamline needs to write the value of data buffer storage and register file, and the content for contrasting the Write post of register file entrance (is used to examine Survey the SET failures of WR section function logics), once CL Compare Logic (501) detects single-particle failure, destroy the number in Write post According to, avoid dirty data flow out streamline.

Data buffer storage (701) and register file (801) are used for the data for storing pipelined units needs, pipelined units root Operation can be written and read to register file and data buffer, interacted with the information that assembly line A provides, flowing water according to coding line Implementing result is write register file and data buffer by line A, or reads out data distribution to two pile line operations.

The dual redundant streamline based on checkpoint technology is using following steps with method to the error number in streamline According to being detected and handled：

(1) fetching section, back-up registers group is arrived into the level inter-register content storage of assembly line A fetching section (101) (401)；The fetching section (101) of assembly line A provides IA, and instruction is taken out from instruction buffer (301) and is distributed to two streams Waterline performs；CL Compare Logic (501) contrasts the level inter-register information of two streamlines, if comparative result is identical, illustrates stream The fetching section of pipeline units does not have coverlet particle bombardment, and streamline continues to perform downwards, if comparative result is different, illustrates one SEU/MBU failures occur for the level inter-register of the fetching section of streamline, provide the error signal of streamline fetching section；

(2) decoding section, back-up registers group is arrived into the level inter-register content storage of assembly line A decoding section (102) (401)；The decoding section (102) of assembly line A reads address information, judges that operand whether there is in Write post (601), if deposited Operand is then being taken out from Write post (601) and is being distributed to two pile line operations, otherwise, is being taken from register file (801) Go out operand and be distributed to two pile line operations；CL Compare Logic (501) contrasts the decoding section level inter-register letter of two streamlines Breath, if comparative result is identical, illustrating the decoding section of pipelined units does not have coverlet particle bombardment, and streamline continues to hold downwards OK, if comparative result is different, illustrate that SET failures, or decoding section occur for the function logic of the fetching section of streamline SEU/MBU failures occur for level inter-register, provide the error signal of pipeline decoding section；

(3) section is performed, back-up registers group is arrived in the level inter-register content storage that assembly line A is performed to section (103) (401)；The execution section (103) of assembly line A reads address information, judges that operand whether there is in Write post (601), if deposited Operand is then being taken out from Write post (601) and is being distributed to two pile line operations, otherwise, is being taken from data buffer storage (701) Go out operand and be distributed to two pile line operations；CL Compare Logic (501) contrasts the level inter-register information of two streamlines, if Comparative result is identical, illustrates the execution section of pipelined units and does not have coverlet particle bombardment, and streamline continues to perform downwards, if than It is different compared with result, illustrate that SET failures occur for the function logic of the decoding section of certain streamline, or perform the level inter-register of section Generation SEU/MBU failures, provide the error signal that streamline performs section；

(4) memory access section, back-up registers group is arrived into the level inter-register content storage of assembly line A memory access section (104) (401)；The memory access section (104) of assembly line A provides writes interactive information with data buffer storage (701), and is updated Write post (601)；CL Compare Logic (501) contrasts the level inter-register information of two streamlines, if comparative result is identical, illustrates streamline The memory access section of unit does not have coverlet particle bombardment, and streamline continues to perform downwards, if comparative result is different, illustrates certain flowing water SET failures occur for the function logic of the execution section of line, or SEU/MBU failures occur for the level inter-register of memory access section, provide stream The error signal of waterline memory access section；

(5) section is write back, back-up registers group is arrived in the level inter-register content storage that assembly line A is write back to section (105) (401)；The section (205) that writes back for writing back section (105) and streamline B of assembly line A provides and interacts letter with writing for register file (701) Breath, and updated Write post (601)；CL Compare Logic (501) contrasts the level inter-register information of two streamlines, if than Identical compared with result, illustrating the section that writes back of pipelined units does not have coverlet particle bombardment, and streamline continues to perform downwards, if compared As a result it is different, illustrate that SET failures occur for the function logic of the memory access section of certain streamline, or write back the level inter-register hair of section Raw SEU/MBU failures, provide the error signal that streamline writes back section；

(6) information in CL Compare Logic (501) contrast step (5) in two streamline deposit Write posts (601), if than It is identical compared with result, illustrate that pipelined units do not have coverlet particle bombardment, if comparative result is different, illustrate the function of writing back section SET failures occur for logic, provide error signal；

(7) error signal in step (1), (2), (3), (4), (5), (6) is carried out or operation, generation recovers signal, such as Fruit recovery signal is effective, cancels all operations of current period pipelined units, and the content in back-up registers group (401) is extensive Again into level inter-register corresponding to two streamlines, while the information of Write post (601) is emptied, forbid updating the data caching (701) and register file (801), streamline re-execute the operation broken down.

In order to describe the fault-tolerance approach of the dual redundant streamline based on checkpoint technology in detail, carried out in terms of following three Analysis：

1st, the fault-tolerant dual redundant pipeline organization of multidigit：Two pipeline parallel methods perform the flowing water sequentially of same instructions stream Line, assembly line A, streamline B are named as, with assembly line A implementing result with being interacted outside pipelined units, comparator is to two The content of bar streamline middle rank inter-register is compared, so as to realize the detection to the single-particle failure of pipelined units.

2nd, the level inter-register back mechanism of cycle granularity：After single-particle failure occurs, in order to be carried out to pipelined units Recover, while avoid failure accumulation and propagation effect, it will pipeline stages inter-register is backed up with cycle granularity, once Comparator detects single-particle failure, by the level inter-register of the content recovery of backup to streamline, streamline after 2 cycles It is normal to perform.

3rd, the Write post mechanism of output data：The mechanism backed up with cycle granularity to level inter-register can only ensure to flow The correctness of pipeline units data, therefore, it is necessary to Write post is set in the entrance of data buffer storage and register file, for cache flow Waterline needs to write the value of data buffer storage and register file, once CL Compare Logic detects single-particle failure, destroys Write post In data, avoid dirty data flow out streamline.

Fault detect and the Restoration Mechanism of dual redundant streamline based on checkpoint technology are as shown in figure 4, level inter-register Ij is streamline i (i=A, B) jth (j=1,2,3,4,5) level level inter-register, and function logic ij is streamline i j-th stage Function logic, back-up registers j be streamline j-th stage back-up registers, comparator j be streamline j-th stage comparator. By taking the error detection and recovery operation of the 2nd grade of streamline as an example, current period, function logic A1/B1 result of calculation DA2/DB2.The Two cycles, DA2/DB2 are latched in grade inter-register A2/B2, and QA2/QB2 is DA2/DB2 latch result.3rd week Phase, back-up registers 2 back up to level inter-register A2 content, and BP2 is QA2 latch result.Error is comparator 2 The error signal provided, for controlling the content recovery of back-up registers into level inter-register.As the above analysis：When Clock clk can by periodic refresh level inter-register ij, meanwhile, back-up registers j in assembly line A level inter-register carry out it is standby Part, comparator is by comparing the content detection single-particle failures of two pipeline stages inter-registers, and comparative result is identical, then flowing water Line proper flow, once comparative result is different, error message Error is set to effectively, by the value in back-up registers j next Cycle returns in the level inter-register of two streamlines and re-executed.

From in Fig. 4, pipelined units have three big critical pieces：Level inter-register, back-up registers and function logic. Level inter-register and back-up registers are sequential logical circuit, are easily influenceed by single-particle and trigger SEU and MBU failures.Function Logic is then combinational logic circuit, and easy coverlet particle bombardment causes signal that transition occurs, and is triggered after being latched by level inter-register SET failures.Run because back-up registers are not interfered with processor by single-particle bombardment, therefore, only deposited between discussion level Device and function logic break down after error detection and restoration methods：

(1) after SEU/MBU failures occur for level inter-register, following three step will be used to carry out error detection with recovering, its sequential is such as Shown in Fig. 5：

The first step：Normal perform is instructed in streamline；

Second step：Back-up registers latch the instruction in the first step, and the level inter-register coverlet particle bombardment of streamline is led SEU/MBU is caused, by the content of comparative degree inter-register, detects single-particle failure, streamline is suspended；

3rd step：The content update that back-up registers in second step are latched re-executes to pipeline stages inter-register Instruction in first step streamline.

(2) after SET failures occur for function logic, following three step will be used to carry out error detection with recovering, its sequential such as Fig. 6 institutes Show：

The first step：The function logic coverlet particle bombardment of streamline causes SET, and improper execution is instructed in streamline；

Second step：Back-up registers latch the instruction in the first step, and SET is latched by level inter-register, by between comparative degree The content of register, detects single-particle failure, and streamline is suspended；

3rd step：The content update that back-up registers in second step are latched re-executes to pipeline stages inter-register Instruction in first step streamline.

After single-particle failure occurs, set forth herein Failure detection and recovery mechanism can control two streamlines again Execution is broken down instruction, so as to ensure the data recovery of pipelined units to normal condition, but register file and data buffer storage It may be updated by the dirty data in streamline.

As shown in fig. 7, Write post is set to be used for temporal data in data buffer storage and register file entrance.In data buffer storage Entrance sets a Write post, and caching assembly line A provides address, data and the control for changing data buffer storage in memory access section Signal.Two Write posts are set in the entrance of register file, assembly line A and streamline B is cached respectively and is used for writing back section and provide Change address, data and the control signal of register file.In set forth herein detection and Restoration Mechanism, if 5, streamline SEU/MBU failures, and the SET failures that 4 grades of function logic occurs before streamline occur for the level inter-register of pipelining-stage, To be detected by comparator, but the function logic for writing back section occurs SET failures and can not then detected.Therefore, entering in register file Mouthful set two Write posts, the result of two streamlines is all cached, and in next cycle compares two Write posts in Hold, both reached the purpose for detecting to write back SET failures in section function logic, extra delay will not be increased critical path again.

Because the entrance in data buffer storage and register file is provided with Write post, cause, when streamline normally performs, to prolong Data renewal is arrived data buffer storage/register file by slow a cycle.Pipelined units send reading to data buffer storage and register file During request of data, it can preferentially judge that purpose information whether there is in Write post.If it is present the number needed is read from Write post Performed according to two streamlines are distributed to, if it does not exist, then reading data distribution from register file/data buffer storage to two streams Waterline performs.When detecting single-particle failure, then cancel the data in Write post, prevent it from updating the data caching/deposit Device heap, while forbid renewal of the current period to Write post.

Fig. 8 is the fault-tolerant timing diagram that SEU/MBU failures occur for pipeline stages inter-register.6th cycle, rising edge clock By the content update in Write post to data buffer storage and register file, while by ME and WR are provided in the 5th cycle renewal number Write post is arrived according to the storage of the information of caching and register file；The ME of single-particle bombardment streamline level inter-register causes SEU/ MBU failures, comparator detection are out of order, and empty Write post, then streamline provides in the 5th clock cycle delays for changing data Deposit and cancelled with the value of register file.7th cycle, rising edge clock forbid ME and WR are provided in the 6th cycle data more Write post newly is arrived, the level inter-register by the content update in back-up registers group to two streamlines, when re-executing the 5th All operations in clock cycle.8th cycle, rising edge clock by ME and WR in the 7th cycle provide update the data caching and Write post is arrived in the information storage of register file.In 8th cycle, rising edge clock is by the content update in Write post to data buffer storage And register file.

Fig. 9 is the fault-tolerant timing diagram that SET failures occur for pipeline function logic.In 5th cycle, rising edge clock will be write slow Content update in punching updates the data caching to data buffer storage and register file, while by what ME and WR in the 4th cycle was provided Write post is arrived in information storage with register file；The ME of single-particle bombardment streamline level inter-register causes SET failures.6th In the individual cycle, rising edge clock is by SET fault latches, and by the content update in Write post to data buffer storage and register file, together When by ME and WR in the 5th cycle provide update the data caching and register file information storage arrive Write post；Comparator is examined Failure is measured, empties Write post, then streamline provides the value for changing data buffer storage and register file in the 5th clock cycle Cancelled.7th cycle, rising edge clock are forbidden the data renewal that ME and WR are provided in the 6th cycle to arrive Write post, will backed up Content update in register group re-executes all operations of the 5th clock cycle to the level inter-register of two streamlines. 8th cycle, the information for updating the data caching and register file that rising edge clock provides ME and WR in the 7th cycle store To Write post.In 9th cycle, rising edge clock is by the content update in Write post to data buffer storage and register file.

In summary, be ensure that based on the fault tolerant mechanism of Write post by increasing the time overhead in the 6th, 7 two cycle Dirty data caused by write operation and SET failures that SEU/MBU failures will not be repeated to data buffer storage/register file will not Data buffer storage and register file are updated.

A kind of dual redundant streamline based on checkpoint technology that the utility model is realized, by the level inter-register of streamline Content backup into back-up registers group, by CL Compare Logic detect pipelined units in single-particle failure, utilize backup Value in register group is recovered to streamline, so as to solve embedded microprocessor for SET caused by single-particle, The Fault-Tolerant Problems of SEU and MBU failures, the reliability that embedded microprocessor works under space environment can be improved.

Claims (3)

1. A kind of 1. dual redundant streamline based on checkpoint technology, it is characterised in that：The dual redundant based on checkpoint technology Streamline include assembly line A, streamline B, instruction buffer (301), back-up registers group (401), CL Compare Logic (501), write it is slow Deposit (601), data buffer storage (701) and register file (801)；The assembly line A include fetching section (101), decoding section (102), Perform section (103), memory access section (104), write back (105) five flowing water sections of section；The streamline B includes fetching section (201), decoding Section (202), perform section (203), memory access section (204), write back (205) five flowing water sections of section；Data buffer storage (701) and register file (801) shared by assembly line A and streamline B, under normal circumstances, default write enters the implementing result of assembly line A during execute instruction stream； The instruction buffer (301) is used for the code for storing streamline execution, and data interaction is carried out with fetching section (101) in assembly line A, Assembly line A is distributed to two streamlines execution after taking out instruction；The back-up registers group (401) is with cycle granularity to streamline A level inter-register is backed up, once CL Compare Logic (501) detects single-particle failure, by the content recovery of backup to stream In waterline A and streamline B level inter-register, streamline normally performs after 2 cycles；The CL Compare Logic (501) is arranged on Between assembly line A and streamline B, the level inter-register content of two streamlines is contrasted, detects single-particle failure；The Write post (601) entrance of data buffer storage (701) and register file (801) is arranged on, is updated the data for keep in that streamline provides；Institute The data that data buffer storage (701) is used to store streamline output are stated, and arithmetic operation number is provided to streamline；The register file (801) it is used for the data for storing streamline output, and arithmetic operation number is provided to streamline.
2. A kind of 2. dual redundant streamline based on checkpoint technology according to claim 1, it is characterised in that：The data Cache (701) entrance and 1 Write post (601) is set, be used to update the data caching for caching assembly line A memory access section (104) (701) information；Register file (801) entrance sets 2 Write posts (601), and section is write back for caching assembly line A (105) and streamline B writes back the information that section (205) is used to update register file (801).
3. A kind of 3. dual redundant streamline based on checkpoint technology according to claim 2, it is characterised in that：The comparison The quantity of logic (501) is 6, wherein 5 are separately positioned between each flowing water section of two streamlines, is posted for contrasting between level Storage information, detect single-particle failure；1 is used to contrast two streamlines in Write post (601) and is used to update register file (801) information, detection pipelined units write back the SET failures of section generation.