WO2017113333A1

WO2017113333A1 - Fpga circuit and method for processing configuration file thereof

Info

Publication number: WO2017113333A1
Application number: PCT/CN2015/100196
Authority: WO
Inventors: 何轲
Original assignee: 京微雅格（北京）科技有限公司
Priority date: 2015-12-31
Filing date: 2015-12-31
Publication date: 2017-07-06
Also published as: CN107710325A

Abstract

An FPGA circuit, comprising: a configuration memory for storing an FPGA configuration file, wherein the configuration file comprises configuration data, an ECC code and a CRC code; a hardware ECC decoder for performing error correction and error detection on the configuration data by using the ECC code; a hardware CRC decoder for performing error correction on the configuration data by using the CRC code; and a single event upset controller for reading back the configuration file, performing detection and error correction on the readback configuration file by using the hardware ECC decoder and the hardware CRC decoder, recording an error state and information about the configuration file, generating corresponding control according to the detection states of the hardware ECC and CRC decoders, sending an error signal to a system-level application, and requesting to reconfigure the FPGA configuration file. By using the circuit, the capability of an FPGA for supporting single event upset can be enhanced, so that the FPGA can be applied to space navigation and aviation or other fields relatively sensitive to an error of a device.

Description

FPGA circuit and its configuration file processing method

Technical field

The present invention relates to an integrated circuit, and more particularly to an FPGA circuit and a method of processing the same.

Background technique

With the advancement of technology, the requirements for on-board signal processing capabilities are getting higher and higher, and FPGAs are increasingly being applied to the aerospace field, becoming a key component of on-board signal processing and control. At present, from the use of FPGAs in spaceborne models, single-event effects have become a major factor affecting the availability and reliability of large-scale FPGAs.

Aerospace-class large-scale FPGAs are based on SRAM type. SRAM type FPGAs must be readback by configuration file readback when applied to high reliability requirements, but their internal registers are susceptible to single instance effects. error. Therefore, research on anti-single-particle effects for large-scale FPGAs is very important and urgent.

Summary of the invention

In a first aspect, an embodiment of the present invention provides an FPGA circuit. The circuit includes a configuration memory for storing an FPGA configuration file, the configuration file includes configuration data and an ECC code and a CRC code, a hardware ECC decoder, and an error correction and error detection of the configuration data by using an ECC code; a hardware CRC decoder, utilizing The CRC code corrects the configuration data; the single-event flip controller is used to read back the configuration file, and uses the hardware ECC decoder and the hardware CRC decoder to check and correct the readback configuration file, and record the configuration file error. Status, information; according to the hardware CRC, ECC decoder detection status, generate corresponding control, and can send an error signal to the system level application, request to reconfigure the FPGA file.

Preferably, the single-event flip controller reads the configuration file in blocks from the configuration memory and transmits them to the CRC decoder to check the configuration file; when the check is in error, the single-event flip controller transmits the faulty configuration file to the ECC decoding. ECC detection or error correction in the device; configuration file has passed ECC After detection or error correction, it is written back to the configuration memory; the single-event flip-flop controller retransmits the profile file that was detected or missed by the ECC to the CRC decoder for CRC detection.

Preferably, the single-event inversion controller reads the configuration file in groups from the configuration memory, and performs ECC detection or error correction in the ECC decoder; each group of configuration files are written back to the ECC detection or error correction. In the configuration file of the block; when the last set of data of this block is written back to the configuration memory, the single-event flip controller reads and transmits the configuration file of the block to the CRC module for verification.

The ECC code can be a Hamming, BCH, RS code or other form of encoding.

Preferably, the configuration file has a block structure, each configuration block comprising a plurality of sets of data and ECC encoded check bits; each of the sets of data has a CRC encoded check bit.

In a second aspect, an embodiment of the present invention provides a configuration file processing method for an FPGA circuit. The method includes: reading a configuration file by a block from a configuration memory, performing a CRC check on the configuration file; and performing an error when checking for an error. The configuration file performs ECC detection or error correction; after the configuration file performs ECC detection or error correction, it is written back to the configuration memory; the configuration file block that is detected or missed by the ECC is again subjected to CRC detection.

In a third aspect, an embodiment of the present invention provides a configuration file processing method for an FPGA circuit, which includes: reading a configuration file by group from a configuration memory, performing ECC detection or error correction; each group of configuration files has passed After the ECC detects or corrects the error, it is written back to the configuration file of the own block; when the last set of data of the block is written back to the configuration memory, the configuration file of the block is read and transmitted to the CRC module. Check it out.

By using a combination of CRC and ECC architecture, the ability of FPGAs to support single-event ups can be greatly enhanced, making FPGAs applicable to aerospace, aerospace or other areas that are sensitive to equipment errors, and therefore have broad and significant implications. .

DRAWINGS

Figure 1 is a configuration file structure with ECC and CRC check code;

2 illustrates an FPGA with ECC error correction and CRC check functionality in accordance with a first embodiment of the present invention. chip;

3 illustrates an FPGA chip with ECC error correction and CRC check functionality in accordance with a second embodiment of the present invention;

Figure 4 illustrates the FPGA design and download process with ECC and CRC checksums;

Figure 5 is another configuration file structure with BCH or RS encoding function;

6 illustrates an FPGA chip with ECC error correction and CRC check functionality in accordance with a third embodiment of the present invention;

FIG. 7 illustrates an FPGA chip with ECC error correction and CRC check function according to a fourth embodiment of the present invention; FIG.

Figure 8 illustrates the FPGA design and download process with BCH or RS encoding.

detailed description

The technical solution of the present invention will be further described in detail below through the accompanying drawings and embodiments.

The embodiment of the invention adds a configuration structure of the CRC and the ECC code in the FPGA configuration file, and the FPGA device performs the readback, check and error correction of the FPGA configuration file based on the CRC and the ECC code during the running process. By using this architecture, the ability of the FPGA to support single-event flipping is greatly enhanced.

Figure 1 depicts a configuration file structure with ECC and CRC checksums. In FIG. 1, each group data Data corresponds to each configuration memory chain, and each configuration memory chain has an ECC-encoded parity bit; each of the plurality of configuration memory chains has a CRC-encoded parity bit, which constitutes a Configure the block structure. The configuration file of the entire configuration FPGA chip contains several such block-like block structures, that is, the configuration file (bitstream, ie bitstream) of the entire FPGA contains CRC-encoded parity bits of multiple blocks.

2 is a schematic diagram of the principle of an FPGA chip according to a first embodiment of the present invention. As shown in FIG. 2, the FPGA chip includes a configuration memory, a hardware ECC (Error Correcting Code) decoder, a hardware CRC (Cyclic Redundancy Check) decoder, and Single event upset (hereinafter referred to as SEU) controller.

The configuration memory can store an FPGA configuration file as shown in Figure 1. Profiles are binary files that customize the functionality of the FPGA device to control the internal logic of the FPGA, internal registers and I/O register initialization, I/O driver enable, and more. The user describes the required functionality in graphics or language, and the development system turns it into the final configuration file. In one example, the FPGA uses SRAM cells to store configuration files. Typically, SRAMs in FPGAs are volatile, especially in aerospace and other fields where single-particle effects affect the FPGA chip and cause errors. The configuration file must be re-downloaded to the FPGA before each power-up. It is also necessary to read back the configuration file for checking and correcting errors during the running process. To this end, in addition to the configuration data, the configuration file is pre-combined with an ECC code and a CRC code to perform ECC error correction and CRC check on the configuration file during writing or reading back.

The ECC decoder detects and corrects the readback configuration data based on the ECC code in the configuration file. The ECC code has, for example, a Hamming code and its improvement code. The principle of ECC code decoding is to add some redundant codes in the configuration file to establish a certain relationship between these data source codes and redundant codes according to certain rules. Once read back, the configuration file is for some reason (for example, single event effect). When some errors occur, the relationship between the data source code and the check code is destroyed, and an illegal code is formed. The ECC decoding mode has the ability to correct single bit flips and detect multi-bit flips.

The CRC decoder performs a corresponding CRC check check on the readback configuration data based on the CRC code in the configuration file, and then transmits the CRC check result to the single particle controller. The CRC code has only error correction function and no error detection function.

The SEU controller is used to perform readback, inspection and error correction of the FPGA configuration file during operation. In one example, the SEU controller can include an FPGA profile readback controller, a state detection controller, and an FPGA configuration file written back to the controller. The FPGA configuration file is read back to the controller to control the configuration file block or group read operation and the corresponding address, the status detection controller records the error information, and the FPGA configuration file is written back to the controller to control the write operation of the configuration file block or group and the corresponding address.

In operation, the SEU controller reads a block's configuration file from the configuration memory and transfers it to the CRC decoder for a profile check of the block (see Figure 1). If no error is detected, The result is fed back to the SEU controller, which will check the configuration file for the next block.

If an error occurs, it indicates that there is an error in the configuration file of this block, then the SEU controller will transmit the configuration file of the erroneous block, one by one, to the ECC decoder for ECC decoding detection or error correction. (See icon 2).

After each set of configuration files has been detected or corrected by ECC decoding, it is written back to the configuration file of this block (see Figure 3).

The SEU controller transmits the profile file that was detected or missed by the ECC to the CRC decoder for CRC detection. In this case, no error occurs in the CRC detection, indicating that the erroneous configuration file block has been successfully corrected by the ECC hardware, and a request is sent to the SEU controller (see icon 4) to perform the same detection on the next configuration file block; The CRC still detects that an error has occurred, indicating that the erroneous configuration file block has exceeded the error correction capability of the ECC code, the error has been miscorrected, and there is no real problem to solve the error. At this time, the status result is sent to the SEU controller ( See icon 4), the controller will issue a corresponding request to the system level based on this result.

By using this new FPGA configuration architecture, SRAM-based FPGA devices can perform the process of reading back, checking, and correcting FPGA configuration files during operation. Due to the limitations of the error correction capability of the ECC codec, the configuration architecture adds a Cyclic Redundancy Check (CRC). Ensure that each FPGA configuration file is correct by using a combination of CRC and ECC. By using this architecture, the ability of the FPGA to support single-event ups can be greatly enhanced, making FPGAs applicable to aerospace, aerospace or other areas that are sensitive to equipment errors, and therefore have broad and significant implications.

Figure 3 depicts an architecture for error correction of a configuration file in accordance with a second embodiment of the present invention. Compared with Figure 2, this mode of operation is that each group performs ECC check and error correction one by one, and then through the CRC to check whether the configuration file is successfully corrected, so the implementation speed will be slower than that proposed in Figure 2. Operating mode.

In operation, the SEU controller reads the configuration file of the first group of a block from the configuration memory, and performs detection or error correction of the decoding in the ECC decoder.

After each set of configuration files has been detected or corrected by ECC decoding, it is written back to the configuration file of this block.

When the last set of data for this block is written back to the configuration memory, the SEU controller issues an instruction to read and transfer the configuration file for that block to the CRC module for verification.

If the CRC detection error occurs, it indicates that the error configuration file block has exceeded the error correction capability range of the ECC code, the error is miscorrected, and there is no real problem to solve the error. At this time, the status result is sent to the SEU controller. Based on this result, a corresponding request will be sent to the system level.

Figure 4 shows the FPGA design and download flow chart with ECC and CRC check functions. As shown in Figure 3, the FPGA design flow generally includes circuit design and input, functional simulation, synthesis, integrated simulation, and implementation.

First, in the circuit design and input phase, the designed function is described to the EDA software using the hardware description language HDL.

In the synthesis phase, design inputs such as the HDL language are translated into logical connections (net tables) consisting of basic logical units such as AND, OR, NOT, RAM, and registers, and the speed and area are logically optimized according to design constraints.

In the implementation phase, the integrated network logic netlist is adapted to the FPGA device based on the model of the selected chip.

In the process of generating the code stream, the check codes of the ECC and the CRC corresponding thereto are added according to the information of the block and the group of the configuration file.

Finally, the configuration file of the ECC and CRC check code is added and downloaded to the configuration chip based on, for example, the JTAG configuration.

After the FPGA is powered on, it first enters the configuration mode. After the last configuration data is loaded into the FPGA, it enters the initialization mode (initialization) and enters the user mode (user-mode) after the initialization is completed. In configuration mode and initialization mode, the user I/O of the FPGA is in a high-impedance state (or internal weak pull-up state). When entering user mode, the user I/O works according to the user-designed function.

The foregoing embodiment of the present invention has been described in connection with a Hamming code which is characterized by error correction of one bit and detection of two bits. Obviously, the invention is not limited thereto, and can also be extended to an error correctable multi-bit coding scheme such as BCH, RS or other error correction coding. The BCH code is a multi-stage, loop, error correction, variable length digital code for correcting multiple random error modes. The RS (Reed-Solomon) code is a special type of non-binary BCH code with strong error correction capability.

5-8 illustrate a configuration file structure, an FPGA chip structure, and an FPGA design and download process of an embodiment of the present invention using a BCH or RS check code. The difference from the case of Figures 1 - 4 is that the encoding is different. Other content is basically the same and will not be repeated.

By using BCH (Bose-Ray-Hocquenghem code) or RS (Reed-solomon code) encoding, it is possible to perform error correction on multiple bits or bytes for each group of configuration files. The configuration architecture and processing circuit proposed by the embodiments of the present invention are still applicable, and the detection and error correction capability for single-event flipping can be further enhanced.

The specific embodiments of the present invention have been described in detail with reference to the preferred embodiments of the present invention. All modifications, equivalent substitutions, improvements, etc., made within the spirit and scope of the invention are intended to be included within the scope of the invention.

Claims

An FPGA circuit comprising:

a configuration memory for storing an FPGA configuration file, the configuration file including configuration data and an ECC code and a CRC code;

a hardware ECC decoder that performs error correction and error detection on the configuration data by using an ECC code;

a hardware CRC decoder that corrects configuration data using a CRC code;

Single-event flip controller for reading back configuration files, and using hardware ECC decoder and hardware CRC decoder to check and correct the readback configuration file, record the error status and information of the configuration file; according to hardware CRC, ECC The detection state of the decoder generates corresponding control and can send an error signal to the system level application requesting reconfiguration of the FPGA file.
The FPGA circuit of claim 1 wherein the single event flip controller reads the configuration file in blocks from the configuration memory and transmits them to the CRC decoder to check the configuration file; in the event of an error check, the single event flip controller The erroneous configuration file is transferred to the ECC decoder for ECC detection or error correction; after the configuration file has been ECC detected or corrected, it is written back to the configuration memory; the single-event flip-flop controller will be detected or missed by the ECC. The profile block is again transmitted to the CRC decoder for CRC detection.
The FPGA circuit of claim 1 wherein the single event rollover controller reads the configuration file in groups from the configuration memory, performs ECC detection or error correction in the ECC decoder; each set of configuration files is subjected to ECC detection or correction After the error, it is written back to the configuration file of the own block; when the last set of data of the block is written back to the configuration memory, the single-event flip controller reads and transmits the configuration file of the block to the CRC module. Check in.
The FPGA circuit of claim 1 wherein the ECC code is a Hamming, BCH or RS code.
The FPGA circuit of claim 1 wherein the configuration file has a block structure, each configuration block comprising a plurality of sets of data and ECC encoded check bits; each of the sets of data having a CRC encoded check bit.
A configuration file processing method for an FPGA circuit, comprising:

Read the configuration file by block from the configuration memory, and perform CRC check on the configuration file;

When checking for an error, the error configuration file is subjected to ECC detection or error correction; after the configuration file is ECC detected or corrected, it is written back to the configuration memory;

The configuration file block to be detected or missed by the ECC is subjected to CRC detection again.
A configuration file processing method for an FPGA circuit, comprising:

Read configuration files by group from configuration memory for ECC detection or error correction;

After each set of configuration files has been ECC detected or corrected, it is written back to the configuration file of the owning block;

When the last set of data for this block is written back to the configuration memory, the configuration file for that block is read and transferred to the CRC module for verification.