CN109491821B - Reinforcing system and method for resisting single event upset - Google Patents

Abstract

The invention provides a reinforcing system and method for resisting single event upset, which comprises the following steps: the system comprises a mode selection input interface, a bit stream memory, a reinforcing system controller, a soft error correction controller IP core, a remote control and remote measurement interface and a field programmable gate array FPGA; wherein: the bit stream memory is used for storing bit streams of the FPGA so as to provide source data for configuration, read-back and refreshing operation of the FPGA; the reinforcing system controller is used for loading configuration data of the FPGA, completing interface protocol conversion and monitoring the state of an IP core of the soft error correction controller; and the soft error correction controller IP core is used for executing read-back, detection and error correction operations of the FPGA configuration. The invention realizes the real-time monitoring and correction of the single event upset error accurate to the frame by adopting the IP core of the soft error correction controller, and reduces the influence of readback refreshing on the system function to the minimum, thereby ensuring the stability of the novel Xilinx FPGA aerospace application.

Description

Reinforcing system and method for resisting single event upset

Technical Field

The invention relates to the technical field of spaceflight, in particular to a reinforcing system and method for resisting single event upset.

Background

In order to solve the problem that a high-performance Field-Programmable Gate Array (FPGA) is influenced by Single Event Upset (SEU), a read-back refreshing technology is provided. The read-back refreshing technology is to read back the configuration information of the detected FPGA in real time and compare the configuration information with the original correct configuration information, detect and position the SEU fault of the FPGA and write the correct data configuration frame into the FPGA by using a method of partial reconstruction of the FPGA, thereby repairing the fault. But as Xilinx does not disclose the bit stream data structure of 7Series FPGAs. Therefore, how to realize read-back refresh of 7Series FPGAs under the condition that the bitstream data structure is unknown becomes a problem which needs to be solved urgently nowadays.

Through retrieval, patent application with publication number CN104051002A discloses a single event upset resistant reinforcement method for refreshing configuration files of Xilinx FPGA. However, the method cannot position the configuration error of the FPGA, and only corrects the single event upset error through the cyclic global refreshing, so that the efficiency is low, and the work of the FPGA can be influenced.

The patent application publication No. CNl03325411A discloses a method for reading the configuration file of Xilinx FPGA through SelectMAP or JTAG interface and comparing the configuration file with the original configuration file read from PROM for error correction. The method is based on the premise that a Static Random-Access Memory (SRAM) -oriented FPGA bit stream data structure is known, but the method is difficult to be directly and effectively applied to FPGAs which do not disclose bit stream structures, such as Xilinx 7Series FPGAs, and the like, and the FPGA configuration piece of the method is PROM, and the condition that the configuration piece adopts Flash or MRAM is not considered.

Therefore, the radiation-resistant reinforcing requirement of the novel FPGA is difficult to meet by using the conventional SRAM type FPGA single event effect-resistant reinforcing method.

Disclosure of Invention

Aiming at the defects in the prior art, the invention aims to provide a reinforcing system and a reinforcing method for resisting single event upset.

In a first aspect, the present invention provides a single event upset resistant reinforcement system, comprising: the system comprises a mode selection input interface, a bit stream memory, a reinforcing system Controller, a Soft Error correction Controller (SEM) IP core, a remote control and remote measurement interface and a Field Programmable Gate Array (FPGA); the mode selection input interface, the bit stream memory, the soft error correction controller IP core, the remote control and remote measurement interface and the field programmable gate array FPGA are respectively and electrically connected with the reinforcement system controller, wherein:

the mode selection input interface is used for configuring the reinforcement mode of the reinforcement system controller according to an input signal;

the bit stream memory is used for storing bit streams of the FPGA so as to provide source data for configuration, read-back and refresh operations of the FPGA;

the reinforcement system controller is used for loading configuration data of the FPGA, completing interface protocol conversion and monitoring the state of the IP core of the soft error correction controller;

the soft error correction controller IP core is used for executing readback, detection and error correction operations of the FPGA configuration;

and the remote control and remote measurement interface is used for transmitting remote control and remote measurement instructions to the reinforcing system controller.

Optionally, the mode selection input interface determines a configuration interface form of the FPGA; the mode selection input interface takes any of the following forms:

master Serial interface, Master SPI interface, Master BPI interface, Master SelectMAP interface, JTAG interface, Slave SelectMAP interface, and Slave Serial interface. The bit width of the SelectMap interface supports three bit widths of 8, 16 and 32.

Optionally, the storage capacity of the bitstream memory is not less than the bitstream size of the FPGA in the system, and the bitstream memory includes: any one of SPI Flash, BPI Flash and MRAM. Wherein the bit stream memory supports the use of serial NOR Flash, parallel NOR Flash, MRAM.

Optionally, the soft error correction controller IP core completes repairing of the frame error in a dynamic partial reconfiguration manner. Therefore, any error frame can be repaired without influencing the work of other non-fault areas.

Optionally, the telemetry interface comprises an RS422 or RS232 serial port.

Optionally, the reinforcement system controller employs triple modular redundancy software, using an antifuse-type FPGA as the reinforcement system controller. Therefore, the software and hardware of the reinforcing system controller adopt the radiation-resistant reinforcing design. In addition, the controller of the reinforcement system supports protocol conversion, and Flash can be directly programmed through a Platform Cable USB loading line in the debugging process.

Optionally, the FPGA is an FPGA facing a static random access memory type; the FPGA comprises: the logical part of SoC and 7Series in Zynq-7000 Series from Xilinx corporation. Namely the logic part of Zynq-7000 Series SoC of Xilinx corporation and all the FPGAs of 7 Series.

In a second aspect, the present invention provides a single event upset resistant reinforcement method, which applies the single event upset resistant reinforcement system according to any one of the first aspect, and the method includes:

loading configuration information on the FPGA after power-on, and if loading fails, re-loading the FPGA until loading succeeds;

enabling the IP core of the soft error correction controller by the reinforcing system controller to compare the configuration information of the FPGA with preset reference configuration information in real time, and correcting error frames if bit stream errors are found;

responding to a remote control and remote measurement command transmitted by a remote control and remote measurement interface, and controlling the operation of the reinforcement system according to the remote control and remote measurement command; downloading system state information according to the remote control and remote measuring instruction;

if the reinforcing system controller monitors that the IP core of the soft error correction controller is in error, the FPGA is reconfigured.

Compared with the prior art, the invention has the following beneficial effects:

the invention realizes the read-back refreshing of the FPGA under the condition of unknown structure of the bit stream data, realizes the real-time monitoring and correction of Single Event Upset (SEU) errors accurate to frames by adopting the IP core of the soft error correction controller, and reduces the influence of the read-back refreshing on the system function to the minimum, thereby ensuring the stability of the novel Xilinx FPGA aerospace application.

Drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:

fig. 1 is a schematic structural diagram of a reinforcing system for resisting single event upset.

Detailed Description

The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.

Fig. 1 is a schematic structural diagram of a principle of a reinforcement system for resisting single event upset, as shown in fig. 1, including: the system comprises a Kintex-7FPGA, a reinforcing system controller, an STM32 auxiliary test board and two SPI Flash pieces. Wherein the Kintex-7FPGA is a reinforced device; an anti-fuse FPGA A54SX72A (not influenced by a single event effect) of ACTEL company is used as a reinforcing system controller, and the internal software adopts a triple modular redundancy design; the STM32 auxiliary test board is used for simulating an upper computer and performing fault injection; the SPI Flash is used for storing a configuration file of the Kintex-7 FPGA.

Specifically, the method for applying the system in fig. 1 to perform the reinforcement against the single event upset may include the following steps:

s1: after the system is powered on, the controller of the ruggedized system writes the content of the configuration slice into a Kintex-7FPGA through a SelectMap interface or an SPI-1 interface, the configuration bit stream is stored in a storage medium connected with the controller of the ruggedized system, and the protocol conversion from the SPI Flash to the FPGA configuration interface is realized in the controller of the ruggedized system.

S2: monitoring the configuration information of the Kintex-7FPGA in real time in a Replace mode of an SEM IP core, if a turnover error is detected, acquiring correct bit stream data by the IP core through an SPI-2 interface to correct an error configuration frame in the Kintex-7FPGA, wherein the Kintex-7FPGA normally operates in the correction process, and a reinforcement system controller can acquire IP core state information through LocalBus and download the IP core state information and control a read-back refreshing process according to a remote control instruction;

s3: if the IP core is turned over, the IP core reports an error to the reinforcement system controller through a LocalBus signal, and the reinforcement system controller reads a bit stream from a storage medium to reconfigure the KINTEX-7 FPGA;

s4: step S2 is repeated after the reconfiguration is completed.

In the embodiment, the read-back refreshing of the Kintex-7FPGA is realized by combining the SEM IP with the reinforcing system controller under the condition that the structure of the bitstream data is unknown. By adopting the SEM IP core, the real-time monitoring and correction of the SEU error accurate to the frame are realized, and the influence of the read-back refreshing on the system function is reduced to the minimum. The stability of high-performance FPGA aerospace application such as Kintex-7FPGA is ensured.

It should be noted that, the steps in the single event upset resistance reinforcing method provided by the present invention may be implemented by using corresponding modules, devices, units, and the like in the single event upset resistance reinforcing system, and those skilled in the art may implement the step flow of the method with reference to the technical scheme of the system, that is, the embodiment in the system may be understood as a preferred example for implementing the method, and details are not described here.

Those skilled in the art will appreciate that, in addition to implementing the system and its various devices provided by the present invention in purely computer readable program code means, the method steps can be fully programmed to implement the same functions by implementing the system and its various devices in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Therefore, the system and various devices thereof provided by the present invention can be regarded as a hardware component, and the devices included in the system and various devices thereof for realizing various functions can also be regarded as structures in the hardware component; means for performing the functions may also be regarded as structures within both software modules and hardware components for performing the methods.

The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.

Claims (5)

1. A single event upset resistant reinforcement system, comprising: the system comprises a mode selection input interface, a bit stream memory, a reinforcing system controller, a soft error correction controller IP core, a remote control and remote measurement interface and a field programmable gate array FPGA; the mode selection input interface, the bit stream memory, the soft error correction controller IP core, the remote control and remote measurement interface and the field programmable gate array FPGA are respectively and electrically connected with the reinforcement system controller, wherein: the FPGA is an FPGA facing to a static random access memory type; the FPGA comprises: the logical part and 7Series of SoC in Zynq-7000 Series of Xilinx corporation;

the mode selection input interface is used for configuring the reinforcement mode of the reinforcement system controller according to an input signal;

the bit stream memory is used for storing bit streams of the FPGA so as to provide source data for configuration, read-back and refreshing operations of the FPGA;

the reinforcement system controller is used for loading configuration data of the FPGA, completing interface protocol conversion and monitoring the state of the IP core of the soft error correction controller; the reinforcement system controller adopts triple-modular redundancy software and uses an anti-fuse FPGA as the reinforcement system controller;

the soft error correction controller IP core is used for executing readback, detection and error correction operations of the FPGA configuration; the IP core of the soft error correction controller completes the repair of frame errors in a dynamic partial reconfiguration mode;

and the remote control and remote measurement interface is used for transmitting remote control and remote measurement instructions to the reinforcing system controller.

2. The reinforcement system for resisting single event upset according to claim 1, wherein the mode selection input interface determines a configuration interface form of the FPGA; the mode selection input interface takes any of the following forms:

master Serial interface, Master SPI interface, Master BPI interface, Master SelectMAP interface, JTAG interface, Slave SelectMAP interface, and Slave Serial interface.

3. The single event upset resistant reinforcement system of claim 1, wherein the storage capacity of the bit stream memory is not less than the bit stream size of the FPGA in the system, and the form of the bit stream memory comprises: SPIFlash, BPI Flash, MRAM.

4. The single event upset resistant ruggedization system of claim 1, wherein the telemetric interface comprises an RS422 or RS232 serial port.

5. A single event upset resistant reinforcement method, wherein the single event upset resistant reinforcement system of any one of claims 1-4 is applied, the method comprising:

loading configuration information on the FPGA after power-on, and if loading fails, re-loading the FPGA until loading succeeds;

enabling the IP core of the soft error correction controller by the reinforcing system controller to compare the configuration information of the FPGA with preset reference configuration information in real time, and correcting error frames if bit stream errors are found;

responding to a remote control and remote measurement command transmitted by a remote control and remote measurement interface, and controlling the operation of the reinforcement system according to the remote control and remote measurement command; downloading system state information according to the remote control and remote measuring instruction;

if the reinforcing system controller monitors that the IP core of the soft error correction controller is in error, the FPGA is reconfigured.

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