CN109542670B - FPGA soft error refreshing method based on error quick positioning and refresher - Google Patents

Abstract

The invention provides an FPGA soft error refreshing method based on error quick positioning, which comprises the following steps: step S1, identifying the parts with high sensitivity to soft errors in the circuit design; step S2, backing up the high sensitive part of the soft error, and obtaining the corresponding relation of the position information between the comparator output and the memory for soft error configuration, namely, positioning the soft error; and step S3, storing the acquired position information corresponding relation on the FPGA, analyzing the output of the comparator by utilizing the hardware of the refresher when the actual circuit runs, and acquiring the position information of the memory configured by the soft error, thereby accurately positioning and refreshing the error. A refresher is also provided. The adopted random fault injection result shows that under the condition of protecting all circuits, the soft error relieving performance of the invention is improved by 16 percent on average, the average error detection time of the circuit is shortened by 45 percent on average, and the effective protection of the soft error of the circuit is realized.

Description

FPGA soft error refreshing method based on error quick positioning and refresher

Technical Field

The invention belongs to the technical field of FPGA (field programmable gate array) soft error protection and structure support technology, and particularly relates to an FPGA soft error refreshing method and a refresher based on error quick positioning.

Background

At present, protection technologies for FPGA Single Event Upset (SEU) soft errors are mainly classified into three categories, namely a technology based on a manufacturing process, a technology based on a design and a refreshing technology.

The technology based on the process is mainly considered from the manufacturing process, and the representative technology is soi (silicon on insulator) process of IBM. The technology improves the process, and has the main advantages of fundamentally reducing the possibility of soft errors and maintaining the single particle turnover at a low level. However, such techniques are often too expensive and do not completely eliminate SEU soft errors, but only to reduce the susceptibility of the circuit to SEU.

An advantage of design-based techniques is that no changes are required to the manufacturing process and the hardware architecture of the FPGA. This technique is mainly used to detect whether the output in the system is correct and how to mask the erroneous output of the system. The technology mainly includes Triple Modular Redundancy (TMR), dual backup comparison technology (DWC), temporal Redundancy technology, Error Detection and Correction coding (EDAC), and the like. Here, TMR and DWC techniques also need to be matched with refresh techniques to avoid accumulation of soft errors. While EDAC technology is more suitable for protecting large memory cells. Design-based techniques mainly utilize circuit redundancy, which often results in additional area overhead and certain performance loss. In practical application, due to the fact that the TMR redundant circuit is too high in overhead, the redundant circuit is required to be simplified to a certain extent.

The refresh technology is a technology for correcting error upset in the FPGA configuration memory. Such techniques include read-back verification, reconfiguration, and partial reconfiguration. The refresh technique can only mitigate circuit configuration errors caused by configuring the memory and does not protect the user memory cells. However, the refresh technology is independent of the user circuit, and the effective protection of the user circuit structure can be realized by combining a universal refresh hardware unit and a TMR technology, wherein the main function of the refresh technology is to repair SEU soft errors in the configuration register and avoid error accumulation.

At present, research aiming at the refresh technology often focuses on optimization of the refresh structure and reduction of average error detection time so as to achieve better soft error protection effect. In the new technologies, some methods pay attention to the combination of software and hardware, and carry out error detection and correction on single-particle upset soft errors by combining a mixed refreshing method of an internal configuration access port ICAP of the FPGA and a software configuration access port PCAP, wherein the method needs to configure corresponding soft cores on the FPGA; in addition, the power consumption of the triple modular redundancy technology is reduced through the triple modular redundancy of the configuration file from the aspect of reducing the power consumption, but the technology does not reduce the redundancy overhead and also reduces the soft error protection effect of the triple modular redundancy to a certain extent; the other technology provides the purposes of improving the refreshing efficiency and reducing the average error correction time by properly rearranging key bits, reallocating resources and compressing the number of configuration frames to be refreshed by analyzing the FPGA configuration structure, but the effect of the technology is reduced under the condition of high cost of circuit design resources; in addition, an on-demand refreshing method according to error detection signals of a redundant circuit is adopted, but the method is still a traversal error detection refreshing method, which can only reduce the average detection time of soft errors to a certain extent, and has a poor effect on the condition that the cost of design circuit resources is high.

Although the current refresh technology is optimized from many angles, the fault detection is performed by performing traversal scanning on the configuration unit. Some refresh methods only detect and refresh configuration frames used in the design, but such methods still need to detect a large number of configuration units to find soft errors under the condition of large design circuit resource overhead, which results in that the average error detection time of the refresh methods is usually very long.

Disclosure of Invention

In the prior art, the refreshing technology of the FPGA single event upset soft error adopts a traversal scanning mode to detect the fault position, so that the refreshing technology has longer error detection time, which is not beneficial to the soft error protection of an FPGA circuit. Aiming at the problem of longer error detection time of the refresh technology, the invention provides a quick positioning method of soft errors on the FPGA configuration level by combining the double backup comparison technology, thereby shortening the average error detection time of the refresh technology and effectively improving the reliability of FPGA application design.

The memory structure of an SRAM type FPGA can be divided into configuration memory, block memory, distributed memory, and flip-flops. The configuration memory is a storage unit with the maximum capacity in the SRAM type FPGA and can be used for controlling configurable resources such as wiring, lookup tables and the like. The statistical result shows that the proportion of SEU (single event upset) generated in the configuration memory reaches 91%, which indicates that most soft errors are generated in the configuration memory. Once the configuration memory is affected by an SEU, the configuration bits stored in the configuration memory may be toggled from 1 to 0 and also from 0 to 1. This may cause a logic gate of the circuit to fail, thereby affecting the output and result of the circuit as a whole.

The invention provides a real-time refreshing technology which is combined with double backup comparison and can quickly position errors for a commercial FPGA (field programmable gate array), and aims to solve the problem of circuit faults caused by SEU (secure element unit) soft errors in an FPGA configuration memory. Fig. 1 shows, by way of a simple example, the effect of this technique on the actual FPGA circuit design. The circuit of fig. 1 (a) is an original circuit without any protection technique applied. The circuit can be divided into A, B, C, D four functional blocks. The circuit in fig. 1 (b) is protected by a refresh method of double backup comparison and error fast positioning. When an actual circuit runs, once a comparator of a module A or a module B detects an error, collected comparator output information is converted into a configuration memory address, a refresher is immediately enabled to detect a series of configuration memories corresponding to the module, which is different from a method that most refreshing technologies search for the position of the error in the configuration memories in a traversing manner, and the position of the configuration memory where the error occurs can be locked in a smaller range through error positioning and a corresponding hardware structure, so that the position of the configuration memory where the error occurs can be detected more quickly, and the correctness of the overall output and the function of the circuit can be effectively protected.

In order to realize the soft error protection of the FPGA circuit, the invention provides an FPGA soft error refreshing method and a refresher based on quick error positioning.

According to one aspect of the invention, an FPGA soft error refreshing method based on error quick positioning is provided, which comprises the following steps:

step S1, identifying the parts with high sensitivity to soft errors in the circuit design;

step S2, backing up the high sensitive part of the soft error, and obtaining the corresponding relation of the position information between the comparator output and the memory for soft error configuration, namely, positioning the soft error;

and step S3, storing the acquired position information corresponding relation on the FPGA, analyzing the output of the comparator by utilizing the hardware of the refresher when the actual circuit runs, and acquiring the position information of the configuration memory with the soft error, thereby accurately positioning the error and quickly refreshing the error.

Preferably, in the step S1, a part of the circuit design that is highly sensitive to soft errors is identified through a redundant circuit selection algorithm; where sensitivity is the result of a fault injection test, the first thirty percent of the circuit's sensitivity test results are typically selected to be ranked as the highly sensitive portion of soft errors.

Preferably, in step S2, the soft error locating is to locate the configuration frame where the soft error occurs, that is, the obtained location information corresponding relationship is a corresponding configuration frame physical address, and the corresponding relationship between the comparator output and the configuration frame physical address is a one-to-many relationship.

Preferably, in step S3, the obtained location information corresponding relationship is stored on the FPGA by using a data structure of a linked list.

Preferably, the positioning of the configuration frame where the soft error occurs includes the following steps:

step S21, each module layout in the circuit design is restricted at the designated position through the xdc restriction file of Vivado, namely corresponding to the resource;

step S22, acquiring the frame physical address interval corresponding to each module through the resource position occupied by the interpretation module;

step S23, when a module error is detected, the position of the configuration frame where the soft error is located is in the frame physical address interval corresponding to the error module resource, thereby implementing error location.

Preferably, the linked list is implemented by using two storage structures for storing the obtained corresponding relationship of the position information, wherein the first storage structure stores the start and end addresses for the second storage structure, and the second storage structure stores the position information corresponding to the addresses.

Preferably, in step S3, when the actual circuit runs, the hardware of the refresher parses the comparator output to obtain the location information of the memory configured with the soft error, including the following steps:

step S31, integrating all error signals output by the comparator when the actual circuit runs to form an error vector, and uniformly processing the error vector;

step S32, obtaining corresponding error vector according to the error information of the module in the error vector, and obtaining the corresponding relation between the error vector and the error frame physical address;

step S33, when an error output by the comparator is detected, decoding the error vector, reading the start and end addresses of the error vector corresponding to the second block storage structure from the first block storage structure as the priority detection address by using the decoded result as the address, and further finding out the frame physical address where the soft error occurs and performing error recovery.

Preferably, in step S33, the configuration memory in which the soft error occurs implements error recovery by an inverter.

According to another aspect of the present invention, there is provided a refresher including:

a frame address generation module for judging whether there is circuit error and generating the next physical address of the frame to be refreshed;

a main control module of the refresher for integral control;

an ICAP control module for performing port access with the ICAP port;

a correction module for modifying the specific error bit;

wherein:

the frame address generating module comprises a first block storage structure and a second block storage structure which are used for realizing a linked list data storage structure; the first block storage structure stores a start address and an end address for the second block storage structure, and the second block storage structure stores location information corresponding to the addresses.

Compared with the prior art, the invention has the following beneficial effects:

the invention mainly protects FPGA configuration bits, utilizes IWLS2005 test reference to carry out random fault injection test on the invention, and has the following technical effects:

according to the method, under the condition that all circuits are protected, compared with a common refreshing technology, the error positioning quick refreshing technology combined with double backup comparison adopted in the FPGA soft error refreshing method based on the error quick positioning improves the soft error relieving performance by 16% on average, shortens the circuit average error detection time by 45% on average, and realizes effective protection of the circuit soft errors.

Drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:

FIG. 1 is a schematic diagram illustrating a working principle of a fast error localization-based FPGA soft error refresh method according to an embodiment of the present invention; wherein, (a) is the original circuit, (b) is the circuit after the refreshing method protection that the invention provides;

FIG. 2 is a schematic diagram of an FPGA configuration resource arrangement according to an embodiment of the present invention;

FIG. 3 is a diagram of a hardware memory structure for error frame physical address according to an embodiment of the present invention;

FIG. 4 is a layout of a MEMORY CONTROL circuit on an FPGA in accordance with an embodiment of the present invention;

fig. 5 is a block diagram of a hardware structure of a refresher according to another embodiment of the present invention.

Detailed Description

The following examples illustrate the invention in detail: the embodiment is implemented on the premise of the technical scheme of the invention, and a detailed implementation mode and a specific operation process are given. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention.

Example 1

The embodiment provides an FPGA soft error refreshing method based on error quick positioning, which adopts an error quick positioning mode of double backup comparison and comprises the following steps:

modules or cells in a circuit design that are highly sensitive to soft errors are first identified. Of course, it is also possible to perform module division on the whole circuit and add dual backup redundancy protection to all modules, but this is equivalent to copying the circuit once, which brings about twice more resource overhead. Analysis shows that the influence on the circuit is different after SEU soft errors occur to different module units in the same circuit design, some unit errors even have no influence on the circuit, and some circuit errors can be easily caused. When the circuit error is easy to cause, namely the module unit with high sensitivity to soft error is effectively protected, the soft error occurring in the remaining low sensitivity module will not have great influence on the circuit output and function, and the soft error occurring in the module units can be effectively eliminated through the traversal type refresh detection.

Secondly, the circuit module or unit with high sensitivity to the soft error is backed up, and the corresponding relation between the output of the comparator and the position information of the memory configured by the soft error is obtained, and the step is error positioning. In Xilinx's FPGA, a frame is the smallest addressable unit in the FPGA configuration storage space, and all operations to the configuration layer operate on the entire frame. Therefore, positioning the error requires positioning the configuration frame where the error is located, i.e. acquiring the physical address of the corresponding configuration frame. Fig. 2 shows the arrangement of resources in the FPGA, which are configurable, i.e. corresponding configuration frames. On this basis, the error location of this embodiment is divided into two steps, i.e., the first step restricts the layout of each module of the circuit at a designated position by using the xdc restriction file of Vivado, i.e., corresponds to a resource, and the second step obtains a frame physical address interval corresponding to each module by reading the positions of the resources occupied by the modules. xdc the constraint file can limit all circuit layout related to the module circuit in the designated position, so once the module has error, the position of the configuration frame where the soft error is located is between the configuration frame physical addresses corresponding to the position resources, thus realizing error location.

And finally, storing the acquired corresponding relation on the FPGA, so that the output of the comparator can be analyzed by the hardware of the refresher when the actual circuit runs, and the position information of the configuration unit with the soft error is obtained, thereby accurately positioning the error and quickly refreshing the error. Since the redundancy detection result of each module only needs to be represented by one bit, i.e. 0 means no error and 1 means error. The error signals collected by all the redundancy detection modules can be integrated to form an error vector, and then the error vector is processed in a unified way. The module can be laid out at a specified position through the constraint of the xdc file, and a corresponding frame physical address range can be obtained through the analysis of the position, and then a corresponding error vector can be obtained according to the position of the error information of the module in the error vector. Thus, there is a correspondence between the error vector and the physical address of the error frame, and this correspondence is often a one-to-many relationship. For this reason, the error vector resolution and frame physical address storage circuit designed in this embodiment is as shown in fig. 3. Here the storage of the frame physical address is performed using a linked list data structure. Two block memory structures are needed, the first for storing the start and end addresses for the second block memory, and the second for storing the corresponding frame physical addresses. When the double backup comparison circuit detects an error, the error vector is decoded first, then the decoded result is used as an address to read the starting address and the ending address of the second block storage structure corresponding to the error vector from the first block storage structure, and finally the addresses are preferentially detected to find out the error as soon as possible. FIG. 3 illustrates the data path with particular regard to the memory structure. Taking the example of collecting 0001 error vector, the decoder translates the position of 1 in the error vector, and uses the result in the address of the first block to read the start and end addresses of the second block, start 000 and end 001. The stored output is simply parsed by a counter module, which in turn provides address signals for the second block of memory based on the parsing result. And then the frame physical address of the error vector needing refresh detection can be obtained by sampling the storage output of the second block. And then other modules of the refresher control the configuration layer access interface to realize the detection and refreshing of the physical address of the specified frame.

When the actual circuit runs, when the circuit finds that the output of the comparator is wrong, the refresher analyzes the output of the comparator to obtain the position information of the wrongly-configured memory, and controls an FPGA configuration layer access interface through the refresher to detect and eliminate the errors; when the output of the comparator of the circuit is correct, the refresher can perform ergodic refresh detection on the configuration memory, so that error accumulation is avoided.

In summary, the FPGA soft error refresh method based on fast error positioning provided by this embodiment mainly includes the following three technical points:

1. redundant circuit selection algorithm: a module or unit for selecting a soft error highly sensitive;

2. the error positioning method comprises the following steps: establishing a corresponding relationship between circuit errors and configuration memory locations;

3. an error control circuit: when the actual circuit runs, the output of the comparator can be analyzed to obtain the corresponding configuration memory position information, and error detection and correction are carried out on the configuration memory at the specified position.

The error positioning method and the error control circuit ensure the implementation of the error positioning quick refresh technology combined with double backup comparison on the FPGA device from the problem of circuit structure.

In this embodiment, the expression of high sensitivity is a result of circuit differences. For example, the module sensitivity measurements in the a circuit may be 1 to 5, and the module sensitivity measurements in the B circuit may be 6 to 8, so that 1 to 3 for a may be highly sensitive, and 6 for B may be highly sensitive, and a fixed pre-percentage of the circuits may be selected for backup, usually according to the sensitivity measurements, wherein the determination of the percentage is related to the specific circuit and the actual application requirements. In this embodiment, the first thirty percent of circuits are selected as the soft error highly sensitive portion for the next steps.

The above embodiments of the present invention are further described in detail with reference to a specific application example.

The core of the FPGA soft error refreshing method based on the error quick positioning provided by the embodiment of the invention is to realize quick error detection and correction through error positioning, and the FPGA soft error refreshing method mainly comprises an error positioning method and an error control circuit. Error location is the relationship between circuit errors and configuration memory locations that can be determined without running the actual circuit, and error control circuitry mainly implements how to implement accurate location of errors and fast error detection and correction by specific circuitry in actual operation of the circuit. The MEMORY CONTROL circuit is used as an example to explain how to implement the refresh operation of the FPGA based on the fast positioning of the soft error.

In the embodiment described in detail below, the MEMORY CONTROL circuit is divided into eight modules, namely, an mc _ rf module, an mc _ adr _ sel module, an mc _ object _ top module, an mc _ dp module, an mc _ refresh module, an mc _ timing module, an mc _ wb _ if module and an mc _ mem _ if module.

The error positioning method comprises the following steps: the error positioning is mainly to obtain the corresponding relation between the internal error of the circuit and the position of the FPGA configuration memory. The resource space occupied by each module is comprehensively recorded through the Vivado circuit, and then the layout of each module of the circuit is restricted at the designated position by using the xdc restriction file of the Vivado according to the circuit required resource. Next is interpreting the frame physical address of the specified location. The frame physical address of the Kintex-7 series FPGA of the Xil inx at present has 26 bits, and is divided into five parts: frame type, top/bottom address, row address, column address, and small address. Fig. 2 is a diagram of the physical addresses of frames, and the main operable frame type is 000, to which all are shown. This is also the most one of the configuration memory types. Then, the top/bottom addresses can be distinguished according to whether the top half or the bottom half belongs to the FPGA, and the row address and the column address can be interpreted according to a schematic diagram. But also as shown in the diagram, the small addresses cannot be one-to-one associated with the resources. It can be seen that a column contains multiple CLBs, but the arrangement direction of the frames in a column is just perpendicular to the arrangement direction of the CLBs, which results in a frame containing partial information of multiple CLBs, and the configuration information of a CLB requires the information of all the frames in the column for interpretation.

The final layout of the MEMORY CONTROL circuit is shown in fig. 4. The mc _ adr _ sel module and the mc _ wb _ if module occupy less resources, so they are arranged in the same column, and the same mc _ object _ top module and mc _ refresh module are also arranged in the same column. Taking mc _ rf module as an example, the module is constrained in a rectangular interval from SLICE _ X68Y75 to SLICE _ X71Y99 through xdc file constraint, and then the corresponding frame physical address is interpreted, and similarly, the frame physical addresses of other modules can be obtained. xdc the constraint position is determined by iteration through measuring the number of configuration resources needed by the module and the connection relationship between the modules, and finally the error positioning is realized.

An error control circuit: the circuit mainly has the functions of analyzing the detection result from the redundant circuit in real time to obtain the physical address of the configuration frame where the soft error is located and controlling the access port of the FPGA configuration layer to detect and refresh the specified physical address of the frame. The overall hardware architecture of the design refresher is shown in fig. 5. It can be seen that the refresher mainly includes a frame address generation module for judging whether there is a circuit error and generating a physical address of a next frame to be refreshed, a main control module of the refresher responsible for overall control, an ICAP control module responsible for being associated with an ICAP port, a correction module responsible for modifying a specific error bit, and some auxiliary modules. Besides, the primitives instantiated with ICAP and FRAME _ ECC are responsible for connecting the FPGA internal configuration access ports and checking the logic unit ports. Only two blocks of memory cells are shown, a Block RAM1 for storing one frame of data, 101 deep by 32 bits, and a Block RAM2 for storing ICAP read-back and write command sequences. Where Block RAM1 is dual-ported and Block RAM2 is single-ported and read-only. And the storage structure for storing frame address information at the frame address generation module is shown in fig. 3. The error control circuit is independent of the user circuit, so that a fixed structure can be used, and the user circuit only needs to update the storage unit for storing the frame address information when being replaced.

The frame address generation module is controlled by the refresh main control module, is the key of the whole refresher and mainly used for generating the next frame physical address for refreshing. The module needs to receive an error signal from a user clock domain, analyze whether a user circuit has errors or not, quickly position the circuit errors by utilizing an optimized storage structure of an error frame physical address, and provide position information to the main control module. The refresh main control module is the core of the whole refresher and mainly comprises a finite state machine, and controls all units to carry out correct operation. Also, if desired, a report of the refresher status signal may be provided for external control. And the fault injection function can be realized by simply modifying the state machine of the main control unit because the used basic unit is consistent with the action of the correction module of the refresher. The ICAP control module is mainly responsible for controlling the reading and writing of the ICAP port, and because the reading and writing of the ICAP port are relatively complex, one module is especially used for controlling the behavior of the ICAP port. The correction module is mainly responsible for modifying the configuration frame, and if in a fault injection state, the module generates a fault at a specified position. The module functions to invert a certain bit of data at a given position in a frame, thereby realizing one-bit fault injection or one-bit fault repair. This module is controlled by the FRAME _ ECC port signal and the refresher master module. In addition, the correction module also translates error information delivered by the ECC port for the refresher to work.

The result of the random fault injection test shows that compared with a sequential refresh structure, the FPGA soft error accurate positioning and fast refresh technology combined with double backup comparison can improve the soft error relieving performance by 15% for the MEMORY CONTROL circuit and reduce the average error fault detection time by 30%.

The error quick-positioning-based FPGA soft error refreshing method provided by the embodiment of the invention can position the position of the configuration memory with soft errors by using the comparison result of the backup circuit so as to realize quick refreshing. Wherein, the layout on FPGA includes: the layout is constrained by xdc files and everything else is the way this can be done. The physical address of the FPGA configuration frame corresponding to the analysis circuit comprises the following steps: and analyzing the corresponding relation between FPGA resources and configuration frames and other ways for realizing the purpose, and acquiring the corresponding relation between circuit errors and configuration memory positions. The structure for analyzing the circuit error and configuring the physical address relationship of the frame comprises the following steps: the corresponding relation between the circuit error and the configuration frame physical address is stored and analyzed in a linked list mode, and all other structures can realize the purpose, and the configuration frame physical address with the error is obtained. A structure for a refresher circuit comprising: the addition of logic control circuit in the refresher and other structures for realizing the purpose are used for controlling the analysis of circuit errors and the operation of the refresher. Configuring error recovery of a memory, comprising: the configuration memory for error detection implements an error recovery function through a not gate and all other ways to accomplish this.

Example 2

The present embodiment provides a refresher, including:

a frame address generation module for judging whether there is circuit error and generating the next physical address of the frame to be refreshed;

a main control module of the refresher for integral control;

an ICAP control module for performing port access with the ICAP port;

a correction module for modifying the specific error bit;

wherein:

the frame address generating module comprises a first block storage structure and a second block storage structure which are used for storing the corresponding relation of the position information; the first block storage structure stores a start address and an end address for the second block storage structure, and the second block storage structure stores location information corresponding to the addresses.

The first block storage structure and the second block storage structure form a linked list data storage structure.

The refresher provided by the embodiment can be applied to the FPGA soft error refresh method based on the error fast positioning provided by embodiment 1.

The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes and modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention.

Claims (7)

1. An FPGA soft error refreshing method based on error quick positioning is characterized by comprising the following steps:

step S1, identifying the parts with high sensitivity to soft errors in the circuit design; wherein, the thirty percent of the circuit part in the test result of the circuit sensitivity is used as the part with high sensitivity of soft errors;

step S2, backing up the high-sensitivity part of the soft error, and obtaining the corresponding relation between the comparator output and the position of the soft error configuration memory when the actual circuit runs, namely, positioning the soft error; the soft error positioning is to position the configuration frame where the soft error occurs, that is, the acquired position information is the physical address of the corresponding configuration frame, and the corresponding relationship between the comparator output and the physical address of the configuration frame is a one-to-many relationship; the method for positioning the configuration frame where the soft error occurs comprises the following steps:

step S21, each module layout in the circuit design is restricted at the designated position through the xdc restriction file of Vivado, namely corresponding to the resource;

step S22, acquiring the frame physical address interval corresponding to each module through the resource position occupied by the interpretation module;

step S23, when module error is detected, the position of the configuration frame where the soft error is located is in the frame physical address interval corresponding to the error module resource, thus realizing error location;

and step S3, storing the acquired position information corresponding relation on the FPGA, analyzing the output of the comparator by utilizing the hardware of the refresher when the actual circuit runs, and acquiring the position information of the configuration memory with the soft error, thereby accurately positioning the error and quickly refreshing the error.

2. The FPGA soft error refresh method based on error fast localization as claimed in claim 1, wherein in step S1, the parts of the circuit design that are highly sensitive to soft errors are identified by a redundant circuit selection algorithm.

3. The FPGA soft error refresh method based on error fast positioning as claimed in claim 1, wherein in step S3, the obtained location information corresponding relation is stored on the FPGA by using a data structure of a linked list.

4. The FPGA soft error refresh method based on error fast localization as claimed in claim 3, wherein two block storage structures are used to implement a linked list for storing the obtained correspondence of the location information, wherein the first block storage structure stores the start and end addresses for the second block storage structure, and the second block storage structure stores the corresponding frame physical address.

5. The FPGA soft error refresh method based on error fast localization as claimed in claim 1, wherein in step S3, when the actual circuit is running, the output of the hardware analysis comparator of the refresher obtains the location information of the memory configured by the soft error, comprising the following steps:

step S31, integrating all error signals output by the comparator when the actual circuit runs to form an error vector, and uniformly processing the error vector;

step S32, obtaining corresponding error signal according to the error information of the module in the error vector, and obtaining the corresponding relation between the error signal and the error frame physical address;

step S33, when an error output by a comparator is detected, decoding the error signal, using the decoded result as an address to read out the start and end addresses of the error signal corresponding to the second block storage structure from the first block storage structure as the priority detection address, and further finding out the frame physical address where the soft error occurs and performing error recovery.

6. The FPGA soft error refresh method based on error fast localization as claimed in claim 5, wherein in step S33, the configuration memory where the soft error occurs realizes the error recovery through NOT gate.

7. A refresher, comprising:

a frame address generation module for judging whether there is circuit error and generating the next physical address of the frame to be refreshed;

a main control module of the refresher for integral control;

an ICAP control module for performing port access with the ICAP port;

a correction module for modifying the specific error bit;

it is characterized in that the preparation method is characterized in that,

the frame address generating module comprises a first block storage structure and a second block storage structure which are used for realizing a linked list data storage structure; the first block storage structure stores a start address and an end address for a second block storage structure, the second block storage structure storing a corresponding frame physical address;

the judging whether a circuit error exists and a next physical address of a detection frame needing to be refreshed is carried out, and the method comprises the following steps:

step S1, identifying the parts with high sensitivity to soft errors in the circuit design; wherein, the thirty percent of the circuit part in the test result of the circuit sensitivity is used as the part with high sensitivity of soft errors;

step S2, backing up the high-sensitivity part of the soft error, and obtaining the corresponding relation of the position information between the comparator output and the soft error configuration memory when the actual circuit runs, namely, positioning the soft error; the soft error positioning is to position the configuration frame where the soft error occurs, that is, the obtained position information corresponding relation is the corresponding configuration frame physical address, and the comparator output and the configuration frame physical address corresponding relation is a one-to-many relation; the method for positioning the configuration frame where the soft error occurs comprises the following steps:

step S21, each module layout in the circuit design is restricted at the designated position through the xdc restriction file of Vivado, namely corresponding to the resource;

step S22, acquiring the frame physical address interval corresponding to each module through the resource position occupied by the interpretation module;

step S23, when module error is detected, the position of the configuration frame where the soft error is located is in the frame physical address interval corresponding to the error module resource, thus realizing error location;

and step S3, storing the acquired position information corresponding relation on the FPGA, analyzing the output of the comparator by utilizing the hardware of the refresher when the actual circuit runs, and acquiring the position information of the configuration memory with the soft error, thereby accurately positioning the error and quickly refreshing the error.

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