CN113268263B - Method and system for refreshing readback of FPGA - Google Patents

Method and system for refreshing readback of FPGA Download PDF

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CN113268263B
CN113268263B CN202110659507.8A CN202110659507A CN113268263B CN 113268263 B CN113268263 B CN 113268263B CN 202110659507 A CN202110659507 A CN 202110659507A CN 113268263 B CN113268263 B CN 113268263B
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configuration
read
data
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CN113268263A (en
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刘晗
张海林
彭飞
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Beijing Institute of Radio Measurement
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Beijing Institute of Radio Measurement
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/60—Software deployment
    • G06F8/65—Updates
    • G06F8/654—Updates using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The invention discloses a readback refreshing method and a readback refreshing system of an FPGA, and relates to the field of fault tolerance of satellite-borne FPGAs. The method comprises the following steps: setting communication states of a preset data transmission interface and the FPGA respectively; sending a read-back instruction to the set FPGA through a preset data transmission interface, and obtaining a read-back file in an FPGA configuration memory; and reading the bit file stored in the external memory, comparing the bit file with the read-back file, judging whether the FPGA is in error according to the comparison result, if so, writing the corresponding correct data packet into the configuration memory of the FPGA, replacing the error data packet, and finishing real-time online configuration refreshing of the FPGA. The method has the advantages that the FPGA configuration state is automatically detected and configuration errors are repaired while the real-time work of the FPGA is not affected, the fault tolerance performance of the satellite-borne FPGA system is improved, the influence of space radiation environment is restrained, and the working stability of the satellite-borne FPGA is improved.

Description

Method and system for refreshing readback of FPGA
Technical Field
The invention relates to the field of fault tolerance of a satellite-borne FPGA, in particular to a method and a system for reading back and refreshing the FPGA.
Background
The FPGA has the characteristics of being capable of being programmed repeatedly, rich in logic resources and high in integration level; in existing part of the on-board systems, FPGAs have been used as system controllers, data processors, and communication interface devices; however, when the space-borne system works in a space radiation environment, the influence of space radiation particles on the total dose effect, single event effect and the like generated by an electronic circuit is one of the reasons for causing circuit faults, and particularly for a circuit system with high integration level such as an FPGA, the faults such as single event upset and the like are easy to generate logic errors in the space radiation environment;
in the FPGA circuit system, a timing reset method can be used for controlling the FPGA to perform periodic reset and reload configuration files to repair the FPGA logic errors. The method is simple in principle and easy to realize; however, since the FPGA is in an inactive state during the resetting of the FPGA, the method is not suitable for application scenarios with high real-time requirements, such as state monitoring, data transmission, and the like.
Disclosure of Invention
The invention aims to solve the technical problem of providing a method and a system for reading back and refreshing an FPGA aiming at the defects in the prior art.
The technical scheme for solving the technical problems is as follows:
A read-back refreshing method of an FPGA comprises the following steps:
S1, respectively setting communication states of a preset data transmission interface and an FPGA;
s2, sending a read-back instruction to the set FPGA through a preset data transmission interface, and obtaining a read-back file in an FPGA configuration memory;
s3, reading a bit file stored in an external memory, comparing the bit file with a read-back file, and if the bit file is different from the read-back file, generating an error by the FPGA;
s4, acquiring a first data packet with errors in the readback file according to the comparison result, and searching a correct second data packet corresponding to the first data packet in the bit file;
And S5, writing the second data packet into a configuration memory of the FPGA through the preset data transmission interface according to preset refreshing logic, and finishing real-time online configuration refreshing of the FPGA.
The beneficial effects of the invention are as follows: according to the scheme, the readback file in the FPGA configuration memory is obtained through the preset data transmission interface, the readback file is compared with the bit file stored in the external memory, whether the FPGA is in error is judged according to the comparison result, if so, the corresponding correct data packet is written into the FPGA configuration memory to replace the error data packet, the FPGA configuration state is automatically detected and the configuration error is repaired while the real-time work of the FPGA is not influenced, the fault tolerance performance of the satellite-borne FPGA system is improved, the influence of space radiation environment is restrained, and the working stability of the satellite-borne FPGA is improved. The scheme can be applied to scenes with high real-time requirements, such as state monitoring and data transmission.
The purpose of automatically detecting and repairing the configuration errors of the FPGA is achieved. The method solves the problem of configuration errors caused by factors such as total dose effect, single event effect and the like of the FPGA in a space radiation environment, and by the method, the FPGA circuit system can automatically detect and repair the configuration errors of the FPGA while working in real time, so that the fault tolerance of the spaceborne FPGA is improved.
Further, before S1, the method further includes: and writing the configuration file in the configuration manager into a configuration memory of the FPGA for the external equipment to read the readback file.
The beneficial effects of adopting the further scheme are as follows: according to the scheme, the FPGA writes bit stream data into a configuration memory in the FPGA from a configuration manager according to control logic, and an internal circuit structure is generated to realize a program function.
Further, before S3, the method further includes:
S31, reading the value of a read-back state register of the FPGA through the preset data transmission interface;
S32, judging the read-back status register value, resetting the FPGA if the status register is abnormal, reloading the configuration file, and then executing the step S31; if the status register is normal, step S3 is performed.
The beneficial effects of adopting the further scheme are as follows: according to the scheme, if the abnormal state value is read, the FPGA is required to be reset, the bit stream data is reloaded, and the readback operation and the generated readback file are ensured to be normal.
Further, the step S3 further includes: and if the bit file is the same as the read-back file, the FPGA does not generate an error, and the S2 step is executed in a return mode.
The beneficial effects of adopting the further scheme are as follows: the method and the device realize real-time online monitoring of whether the FPGA is wrong or not, and prevent the FPGA from being affected by configuration errors caused by factors such as total dose effect, single event effect and the like in a space radiation environment.
Further, the preset refresh logic sequentially includes: command header data refresh, data portion refresh, and command tail data refresh.
The beneficial effects of adopting the further scheme are as follows: the scheme can realize online refreshing, and the FPGA chip does not need global reset and reconfiguration.
The read-back and refreshing operation of the FPGA1 is realized, so that the purposes of automatically detecting and repairing the configuration errors of the FPGA1 are realized.
The other technical scheme for solving the technical problems is as follows:
a readback refresh system for an FPGA, comprising: the system comprises a state setting module, a readback module, a comparison module, a search module and a refreshing module;
The state setting module is used for setting communication states of a preset data transmission interface and the FPGA respectively;
The read-back module is used for sending a read-back instruction to the set FPGA through the preset data transmission interface to obtain a read-back file in the FPGA configuration memory;
The comparison module is used for reading the bit file stored in the external memory, comparing the bit file with the read-back file, and if the bit file is different from the read-back file, generating an error by the FPGA;
the searching module is used for acquiring a first data packet with errors in the readback file according to the comparison result, and searching a correct second data packet corresponding to the first data packet in the bit file;
and the refreshing module is used for writing the second data packet into the configuration memory of the FPGA through the preset data transmission interface according to preset refreshing logic to complete real-time online configuration refreshing of the FPGA.
The beneficial effects of the invention are as follows: according to the scheme, the readback file in the FPGA configuration memory is obtained through the preset data transmission interface, the readback file is compared with the bit file stored in the external memory, whether the FPGA is in error is judged according to the comparison result, if so, the corresponding correct data packet is written into the FPGA configuration memory to replace the error data packet, the FPGA configuration state is automatically detected and the configuration error is repaired while the real-time work of the FPGA is not influenced, the fault tolerance performance of the satellite-borne FPGA system is improved, the influence of space radiation environment is restrained, and the working stability of the satellite-borne FPGA is improved. The scheme can be applied to scenes with high real-time requirements, such as state monitoring and data transmission.
The purpose of automatically detecting and repairing the configuration errors of the FPGA is achieved. The method solves the problem of configuration errors caused by factors such as total dose effect, single event effect and the like of the FPGA in a space radiation environment, and by the method, the FPGA circuit system can automatically detect and repair the configuration errors of the FPGA while working in real time, so that the fault tolerance of the spaceborne FPGA is improved.
Further, the method further comprises the following steps: and the loading module is used for writing the configuration file in the configuration manager into the configuration memory of the FPGA so as to read the readback file by the external equipment.
The beneficial effects of adopting the further scheme are as follows: according to the scheme, the FPGA writes bit stream data into a configuration memory in the FPGA from a configuration manager according to control logic, and an internal circuit structure is generated to realize a program function.
Further, the method further comprises the following steps: the register judging module is used for reading the value of the readback state register of the FPGA through the preset data transmission interface;
judging the value of the read-back status register, resetting the FPGA, reloading the configuration file, and then continuously reading the value of the read-back status register of the FPGA if the status register is abnormal; and if the status register is normal, comparing the bit file with the read-back file.
The beneficial effects of adopting the further scheme are as follows: according to the scheme, if the abnormal state value is read, the FPGA is required to be reset, the bit stream data is reloaded, and the readback operation and the generated readback file are ensured to be normal.
Further, the comparison module is further configured to return to continue reading the readback file if the bit file is the same as the readback file and the FPGA is not in error.
The beneficial effects of adopting the further scheme are as follows: the scheme realizes real-time online monitoring of whether the FPGA is wrong or not, and prevents the FPGA from being influenced by configuration errors caused by factors such as total dose effect, single event effect and the like in a space radiation environment.
Further, the preset refresh logic sequentially includes: command header data refresh, data portion refresh, and command tail data refresh.
The beneficial effects of adopting the further scheme are as follows: the scheme can realize online refreshing, and the FPGA chip does not need global reset and reconfiguration.
Additional aspects of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
Fig. 1 is a schematic flow chart of a read-back refreshing method of an FPGA according to an embodiment of the present disclosure;
FIG. 2 is a block diagram of a read-back refresh system for an FPGA according to an embodiment of the present invention;
Fig. 3 is a schematic block diagram of a fault tolerant circuit according to other embodiments of the present invention.
Detailed Description
The principles and features of the present invention are described below with reference to the drawings, the illustrated embodiments are provided for illustration only and are not intended to limit the scope of the present invention.
As shown in fig. 1, a method for refreshing a read-back of an FPGA according to an embodiment of the present invention includes:
S1, respectively setting communication states of a preset data transmission interface and an FPGA 1; the preset data transmission interface can be a specific SELECTMAP data transmission interface functional module in the FPGA1, the part is not in conflict with other functional modules, and the FPGA1 still works normally in the read-back process. In addition, SELECTMAP data transmission interfaces are bidirectional interfaces, and data flow can be set by respectively reading and writing the FPGA1 register during read-back and refresh.
It should be noted that, in an embodiment, during the operation of the FPGA1, the external refresh device 3 may perform a read-back operation at intervals, and in each read-back period, the external refresh device 3 may send a control instruction to the FPGA1 through the data transmission interface, set the FPGA1 to a read-back state, and set the data transmission interface to a readable state;
In one embodiment, S1 may further include: a fault tolerant circuit is built, the circuit comprising: the system comprises an FPGA1, a configuration manager 2, an external refreshing device 3 and an external FLASH memory 4; the configuration manager 2 is used for writing bit stream data into a configuration memory of the FPGA1 after the system is powered on, generating a circuit structure of the FPGA1 and completing configuration of the FPGA 1; the external refresher 3 is used for controlling the read-back and refresh operations of the FPGA 1; the external FLASH memory 4 is used for storing a bit file, and when the FPGA1 is in error, the bit file can be used for refreshing the FPGA 1;
In one embodiment, after the FPGA1 software development is completed, a "curing" operation may be performed in a development environment, such as Vivado, and a file jic may be generated using the compiled software and downloaded to the configuration manager 2, i.e., the SPI interface FLASH chip. The jic files stored in the configuration manager 2 may be written to the configuration memory of the FPGA1 after the system is powered up in the form of a plurality of data packets, collectively referred to as bitstream data. The FPGA1 may generate an internal circuit structure from the bitstream data, thereby implementing a function of software design. The bit stream data is a program file to be loaded after the FPGA1 is powered on, and after loading is completed, the FPGA1 can realize the expected function.
It should be noted that in one embodiment, the bit file and the bit stream data are the same, and are all the jic files stored in the FLASH memory. The bit files are static files stored in FLASH, but in different forms, and the bit stream data is a generic term for a plurality of packets.
In one embodiment, the schematic block diagram of the fault tolerant circuit may be as shown in fig. 3, in the fault tolerant circuit, the configuration manager 2 may be a FLASH chip of the SPI interface, the external FLASH memory 4 is also a FLASH chip, and these two devices may select multiple brands of products with different specifications according to the storage capacity requirement; the FPGA1 is mainly A7 Series FPGA chip produced by Xilinx company, can comprise various specifications of products of three sub-Series A7, K7 and Z7, and can be selected according to actual requirements without specific limitation. The external refreshing device 3 refers to a JFMRS RH readback refreshing circuit of a compound micro-electronic company, but other manufacturers including products corresponding to foreign manufacturers can also realize external corresponding functions without specific limitation of models. The invention is based on Xilinx K7FPGA+ JFMRS01RH hardware platform for design and verification, and the invention is more focused on the principle readback refreshing method of the fault-tolerant circuit, and is not limited to a specific hardware platform, but can also be the fault-tolerant circuit of other platforms.
S2, sending a read-back instruction to the set FPGA1 through a preset data transmission interface, and obtaining a read-back file in a configuration memory of the FPGA 1;
In one embodiment, the external refresher 3 can periodically read back the FPGA 1; in each readback period, the external refresher 3 sends a control instruction to the FPGA1 through the data transmission interface, sets the FPGA1 to a readback state, and sets the data transmission interface to a readable state; after the setting is completed, the external refreshing device 3 sends a read-back instruction, reads data in the configuration memory of the FPGA1 according to the address sequence, generates bit stream data, and generates a read-back file according to the bit stream data; the readback of the FPGA1 by the external refresher 3 is controlled by reading and writing the register. The bit stream data is the data stream when the FPGA1 loads the configuration file into the configuration memory, and the read-back operation is to restore another data stream from the configuration memory to the external refresh device 3 to generate the read-back file.
S3, reading a bit file stored in an external memory, comparing the bit file with a read-back file, and if the bit file is different from the read-back file, generating an error by the FPGA 1;
In a certain embodiment, the bit file stored in the external FLASH memory 4 is the same as the configuration file solidified in the configuration manager 2, that is, the bit stream data of the two are the same, and both the bit stream data are composed of data packets in the format of packet header+packet body. After the external refreshing device 3 completes the read-back operation and obtains the read-back file, reading the bit file stored in the external FLASH memory 4, and comparing the bit file with the read-back file; if the bit file is the same as the read-back file, the FPGA1 is proved to have no error and can work continuously; if the bit file is different from the read-back file, the FPGA1 is indicated to have errors, and the FPGA1 needs to be configured and refreshed;
It should be noted that, in one embodiment, the relationship between the bit file, the configuration file, and the read-back file may be: on the content, three files are all the jic files generated by the development environment. The bitfiles and configuration files are downloaded directly into FLASH from the jic file. Wherein the bit file is a file jic stored in the external FLASH memory 4, and the configuration file is a file jic stored in the configuration manager 2; the read-back file is a file restored from the configuration memory of the FPGA1 by the external refresher 3 reading back the FPGA 1. If no configuration error occurs in FPGA1, the content of the read-back file should be the same as jic. This is the principle of comparing the read-back file with the bit file.
S4, acquiring a first data packet with errors in the read-back file according to the comparison result, and searching a correct second data packet corresponding to the first data packet in the bit file;
And S5, writing the second data packet into a configuration memory of the FPGA1 according to a preset refreshing logic through a preset data transmission interface, and completing real-time online configuration refreshing of the FPGA 1.
It should be noted that, in a certain embodiment, when the read-back file is different from the bit file stored in the external FLASH memory 4, the external refresh device 3 will refresh the FPGA 1; the external refreshing device 3 reads packet header information of the data packet with errors in the read-back file according to the comparison condition of the bit file and the read-back file, reads the external FLASH memory 4 according to the packet header information, searches the corresponding data packet in the bit file and reads the data packet into the data buffer area; after reading the bit file data packet, sending a refreshing instruction to the FPGA1 through a data transmission interface, and writing the data packet into a configuration memory of the FPGA1 according to preset refreshing logic to finish refreshing operation;
In a certain embodiment, the buffer may be a buffer of the external refresh device 3. The external refresher 3 can locate the position of the error of the read-back file, find the corresponding content in the external FLASH memory 4, store the data packets into the buffer area, then the external refresher 3 needs to pack the data, write the data into the configuration memory of the FPGA1 according to the set time sequence, finish refreshing;
wherein the preset refresh logic may include: the first part is command header data, which is automatically generated by the external refresher 3, and includes an AA995566 sync word, a write CMD register, a write WCFG command, a write FDRI register, and a written data amount;
The second part is a data part, and the data is stored in the buffer; the third part is the command tail, which is automatically generated by the external refresher 3.
During the refresh process, the external refresher 3 writes data into the FPGA1, SELECTMAP through the SELECTMAP interface, which is a standard interface, and its transmission timing is fixed.
According to the scheme, the readback file in the configuration memory of the FPGA1 is obtained through the preset data transmission interface, the readback file is compared with the bit file stored in the external memory, whether the FPGA1 is in error or not is judged according to the comparison result, if so, the corresponding correct data packet is written into the configuration memory of the FPGA1 to replace the error data packet, the configuration state of the FPGA1 is automatically detected and the configuration error is repaired while the real-time work of the FPGA1 is not influenced, the fault tolerance performance of a satellite-borne FPGA1 system is improved, the influence of space radiation environment is restrained, and the working stability of the satellite-borne FPGA1 is improved. The scheme can be applied to scenes with high real-time requirements, such as state monitoring, data transmission and the like.
The purpose of automatically detecting and repairing the configuration errors of the FPGA1 is achieved. The method solves the problem of configuration errors caused by factors such as total dose effect, single event effect and the like of the FPGA1 in a space radiation environment, and by the method, the circuit system of the FPGA1 can automatically detect and repair the configuration errors of the FPGA1 while working in real time, so that the fault tolerance of the spaceborne FPGA1 is improved.
Preferably, in any of the above embodiments, before S1, further includes: and writing the configuration file in the configuration manager 2 into a configuration memory of the FPGA1 for external equipment to read back the read-back file. Wherein the external device may be an external refresher.
In one embodiment, after the development environment compiles the FPGA1 program, a configuration file may be generated, and the configuration file is stored in the configuration manager 2 by means of solidification; after the system is electrified, the FPGA1 loads a configuration file from the configuration manager 2, bit stream data is stored in the configuration file, the bit stream data consists of a plurality of data packets with the format of packet header plus packet body, wherein the packet header corresponds to an address of an internal configuration memory of the FPGA1, and the packet body corresponds to a specific configuration instruction; the FPGA1 writes bit stream data into a configuration memory in the FPGA1 from a configuration manager 2 according to control logic, an internal circuit structure is generated, a program function is realized, and the FPGA1 starts to work after configuration is completed.
It should be noted that in one embodiment, the configuration file may be the file jic described above, and the configuration instructions may be the content of the FPGA1 software design, because the bitstream data includes a plurality of data packets, and the package body of each data packet is a part of the FPGA1 software content. This sub-loading process is done automatically by FPGA1 and the designer does not need to participate.
In one embodiment, FPGA1 is a programmable logic device, and a large number of logic gates are inside the device. The FPGA1 software can be analogically connected to the wires of these logic gates. Through designing an FPGA1 program, connecting a plurality of resources in the FPGA1 to obtain a circuit with a specific function. The work of the connection is completed by a development environment, and the connection can be automatically performed after the program is compiled by only designing the program, so that the generated bit stream file can be understood as a circuit diagram, and the FPGA1 performs internal connection according to the bit stream file to generate an internal circuit structure. This internal circuit structure is implemented inside the FPGA1 chip, for example, when a serial transceiver program is designed using a development environment, it is solidified into the FPGA 1. Therefore, the internal circuit structure of the FPGA1 is the circuit structure of the serial port, and the function of serial port receiving and transmitting can be realized.
According to the scheme, the FPGA1 writes bit stream data into a configuration memory in the FPGA1 from the configuration manager 2 according to control logic, and an internal circuit structure is generated to realize a program function.
Preferably, in any of the above embodiments, S3 further includes:
S31, reading the value of a readback state register of the FPGA1 through a preset data transmission interface;
s32, judging the read-back status register value, resetting the FPGA1 if the status register is abnormal, reloading the configuration file, and then executing the step S31; if the status register is normal, step S3 is performed.
In one embodiment, the external refresher 3 status monitoring the FPGA1 may include:
The read-back operation of the external refreshing device 3 does not influence the working state of the FPGA1, the value of the read-back state register of the FPGA1 can be read through the data transmission interface in the process of controlling the FPGA1 to read back by the external refreshing device 3, and if the value of the read-back state register is correct, the read-back operation and the generated read-back file are normal;
It should be noted that, in a certain embodiment, the working state of the FPGA1 may not be affected: the on-line refreshing can be realized, and the FPGA1 chip does not need global reset and reconfiguration. The specific flow is as follows:
The external refresher 3 supports an error positioning function, can identify the error position in the bit stream data, extracts a corresponding data packet from the bit file, and writes the data packet into the FPGA1 configuration memory through a data transmission interface. In other words, if the program module 1 is in a configuration error, only the program module 1 needs to be reconfigured, and other program modules do not need to be reconfigured.
It should be noted that, compared to the scheme of global reset reconfiguration of FPGA1, the read-back refresh method has less influence on FPGA1, but still has influence on the real-time function, which is unavoidable. For example, the time for resetting and reloading the FPGA1 is 500ms, the real-time function failure time is 500ms, the refresh time is 50ms, and the real-time function failure time is only 50ms, so that the effect caused by the refresh time is negligible, which is equivalent to not affecting the normal operation of the FPGA 1.
It should be noted that, the judgment of the register value may be: the invention designs and verifies based on the Xilinx K7FPGA+ JFMRS01RH hardware platform. The data transmission interface under the platform is SELECTMAP interface, the read-back refreshing chip firstly writes 0XEC8300 into the FAR register of the FPGA, then reads the value of the FAR register, if the read value is 0XEC8300, the read-back can be normally carried out, if the read value is abnormal, the FPGA needs to be reset, and the bit stream data is reloaded; in the read-back stage, the value of the STAT state register is read through the SELECTMAP interface, 1 is normal, 0 is abnormal, and if the abnormal state value is read, the reset is needed, and the bit stream data is reloaded.
In a certain embodiment, the method may further include: in the read-back stage, the value of the STAT status register is read through the SELECTMAP interface, and if the abnormal status value is read, the FPGA1 needs to be reset, and the bitstream data is reloaded.
According to the scheme, if the abnormal state value is read, the FPGA1 is required to be reset, the bit stream data is reloaded, and the readback operation and the generated readback file are ensured to be normal.
Preferably, in any of the above embodiments, S3 further includes: if the bit file is the same as the read-back file, the FPGA1 does not have an error, and returns to execute step S2.
The scheme realizes real-time online monitoring of whether the FPGA1 is wrong or not, and prevents the FPGA1 from being influenced by configuration errors caused by factors such as total dose effect, single event effect and the like in a space radiation environment.
Preferably, in any of the above embodiments, the preset refresh logic sequentially includes: command header data refresh, data portion refresh, and command tail data refresh.
The scheme can realize online refreshing, and the FPGA1 chip does not need global reset and reconfiguration.
The read-back and refreshing operation of the FPGA1 is realized, so that the purposes of automatically detecting and repairing the configuration errors of the FPGA1 are realized.
In one embodiment, as shown in fig. 2, a read-back refresh system of an FPGA includes: a state setting module 110, a readback module 120, a comparison module 130, a search module 140, and a refresh module 150;
The state setting module 110 is configured to set communication states of the preset data transmission interface and the FPGA1 respectively;
The read-back module 120 is configured to send a read-back instruction to the set FPGA1 through a preset data transmission interface, and obtain a read-back file in the configuration memory of the FPGA 1;
The comparison module 130 is configured to read a bit file stored in the external memory, compare the bit file with a read-back file, and if the bit file is different from the read-back file, generate an error in the FPGA 1;
The searching module 140 is configured to obtain, according to the comparison result, a first data packet in which an error occurs in the read-back file, and search for a correct second data packet corresponding to the first data packet in the bit file;
The refresh module 150 is configured to write the second data packet into the configuration memory of the FPGA1 according to a preset refresh logic through a preset data transmission interface, so as to complete real-time online configuration refresh of the FPGA 1.
According to the scheme, the readback file in the configuration memory of the FPGA1 is obtained through the preset data transmission interface, the readback file is compared with the bit file stored in the external memory, whether the FPGA1 is in error or not is judged according to the comparison result, if so, the corresponding correct data packet is written into the configuration memory of the FPGA1 to replace the error data packet, the configuration state of the FPGA1 is automatically detected and the configuration error is repaired while the real-time work of the FPGA1 is not influenced, the fault tolerance performance of a satellite-borne FPGA1 system is improved, the influence of space radiation environment is restrained, and the working stability of the satellite-borne FPGA1 is improved. The scheme can be applied to scenes with high real-time requirements, such as state monitoring and data transmission.
The purpose of automatically detecting and repairing the configuration errors of the FPGA1 is achieved. The method solves the problem of configuration errors caused by factors such as total dose effect, single event effect and the like of the FPGA1 in a space radiation environment, and by the method, the circuit system of the FPGA1 can automatically detect and repair the configuration errors of the FPGA1 while working in real time, so that the fault tolerance of the spaceborne FPGA1 is improved.
Preferably, in any of the above embodiments, the method further includes: and the loading module is used for writing the configuration file in the configuration manager 2 into the configuration memory of the FPGA 1.
According to the scheme, the FPGA1 writes bit stream data into a configuration memory in the FPGA1 from the configuration manager 2 according to control logic, and an internal circuit structure is generated to realize a program function.
Preferably, in any of the above embodiments, the method further includes: the register judging module is used for reading the value of the readback state register of the FPGA1 through a preset data transmission interface;
Judging the value of the read-back status register, resetting the FPGA1 if the status register is abnormal, reloading the configuration file, and then continuously reading the value of the read-back status register of the FPGA 1; if the status register is normal, a comparison of the bit file and the read-back file is made.
According to the scheme, if the abnormal state value is read, the FPGA1 is required to be reset, the bit stream data is reloaded, and the readback operation and the generated readback file are ensured to be normal.
Preferably, in any of the above embodiments, the comparison module 130 is further configured to return to continue reading the readback file if the bit file is the same as the readback file and no error occurs in the FPGA 1.
The scheme realizes real-time online monitoring of whether the FPGA1 is wrong or not, and prevents the FPGA1 from being influenced by configuration errors caused by factors such as total dose effect, single event effect and the like in a space radiation environment.
Preferably, in any of the above embodiments, the preset refresh logic sequentially includes: command header data refresh, data portion refresh, and command tail data refresh.
The scheme can realize online refreshing, and the FPGA1 chip does not need global reset and reconfiguration.
It is to be understood that in some embodiments, some or all of the alternatives described in the various embodiments above may be included.
It should be noted that, the foregoing embodiments are product embodiments corresponding to the previous method embodiments, and the description of each optional implementation manner in the product embodiments may refer to the corresponding description in the foregoing method embodiments, which is not repeated herein.
The reader will appreciate that in the description of this specification, a description of terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
In the several embodiments provided by the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of elements is merely a logical functional division, and there may be additional divisions of actual implementation, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted, or not performed.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiment of the present invention.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention is essentially or a part contributing to the prior art, or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods of the embodiments of the present invention. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a Read-only memory (ROM), a random access memory (RAM, randomAccessMemory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The present invention is not limited to the above embodiments, and various equivalent modifications and substitutions can be easily made by those skilled in the art within the technical scope of the present invention, and these modifications and substitutions are intended to be included in the scope of the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.

Claims (4)

1. The method for refreshing the FPGA by the read-back is characterized by comprising the following steps of:
S1, respectively setting communication states of a preset data transmission interface and an FPGA;
S2, sending a read-back instruction to the set FPGA through the preset data transmission interface, and obtaining a read-back file in an FPGA configuration memory;
The external refreshing device performs periodic readback on the FPGA; in each readback period, the external refresher sends a control instruction to the FPGA through the data transmission interface, the FPGA is set to be in a readback state, and the data transmission interface is set to be in a readable state; after the setting is completed, the external refreshing device sends a read-back instruction, reads data in the FPGA configuration memory according to the address sequence, generates bit stream data, generates a read-back file according to the bit stream data, wherein the read-back of the external refreshing device to the FPGA is controlled through a read-write register, the bit stream data is a data stream when the FPGA loads the configuration file into the configuration memory, and the read-back operation is to restore another data stream from the configuration memory to the external refreshing device, so as to generate the read-back file;
s3, reading a bit file stored in an external memory, comparing the bit file with the read-back file, and if the bit file is different from the read-back file, generating an error by the FPGA;
s4, acquiring a first data packet with errors in the readback file according to the comparison result, and searching a correct second data packet corresponding to the first data packet in the bit file;
s5, writing the second data packet into a configuration memory of the FPGA according to a preset refreshing logic through the preset data transmission interface, and finishing real-time online configuration refreshing of the FPGA;
The preset refreshing logic sequentially comprises the following steps: the method comprises the steps of command head data refreshing, data part refreshing and command tail data refreshing, wherein the command head data is automatically generated by an external refresher and comprises an AA995566 synchronous word, a write CMD register, a write WCFG command, a write FDRI register and a written data quantity; a data section in which data is stored in the buffer; the command tail part is automatically generated by an external refreshing device; s1 further comprises the following steps:
Building a fault tolerant circuit, wherein the fault tolerant circuit comprises: the system comprises an FPGA, a configuration manager, an external refreshing device and an external FLASH memory; the configuration manager is used for writing bit stream data into a configuration memory of the FPGA after the system is powered on, generating an FPGA circuit structure and completing configuration of the FPGA; the external refresher is used for controlling the read-back and refreshing operation of the FPGA; the external FLASH memory is used for storing a bit file, and when the FPGA is in error, the bit file is used for refreshing the FPGA;
The method further comprises the following steps before the step S1: writing a configuration file in the configuration manager into a configuration memory of the FPGA for external equipment to read the readback file;
The step S3 further includes:
S31, reading the value of a read-back state register of the FPGA through the preset data transmission interface;
S32, judging the read-back status register value, resetting the FPGA if the status register is abnormal, reloading the configuration file, and then executing the step S31; if the status register is normal, executing step S3;
In the readback stage, reading the value of a STAT state register through a SELECTMAP interface, and resetting the FPGA and reloading bit stream data if the abnormal state value is read;
After compiling the FPGA program, the development environment generates a configuration file, and the configuration file is stored in a configuration manager in a solidifying mode; after the system is electrified, the FPGA loads a configuration file from a configuration manager, bit stream data is stored in the configuration file, the bit stream data consists of a plurality of data packets with the formats of packet header and packet body, wherein the packet header corresponds to an address of an internal configuration memory of the FPGA, and the packet body corresponds to a specific configuration instruction; the FPGA writes bit stream data into a configuration memory in the FPGA from a configuration management device according to control logic to generate an internal circuit structure, so as to realize a program function, and the FPGA starts working after the configuration is completed;
The relationship of the bit file, the configuration file and the read-back file is: in terms of content, the three files are the jic files generated by the development environment, the bit files and the configuration files are the jic files directly downloaded into FLASH, wherein the bit files are the jic files stored in an external FLASH memory, and the configuration files are the jic files stored in the configuration manager 2; the read-back file is a file restored from the configuration memory of the FPGA1 by the external refresher reading back the FPGA 1.
2. The method for read-back refreshing of an FPGA of claim 1, wherein S3 further comprises: and if the bit file is the same as the read-back file, the FPGA does not generate an error, and the S2 step is executed in a return mode.
3. A readback refresh system for an FPGA, comprising: the system comprises a state setting module, a readback module, a comparison module, a search module and a refreshing module;
The state setting module is used for setting communication states of a preset data transmission interface and the FPGA respectively;
The read-back module is used for sending a read-back instruction to the set FPGA through the preset data transmission interface to obtain a read-back file in the FPGA configuration memory;
The external refreshing device performs periodic readback on the FPGA; in each readback period, the external refresher sends a control instruction to the FPGA through the data transmission interface, the FPGA is set to be in a readback state, and the data transmission interface is set to be in a readable state; after the setting is completed, the external refreshing device sends a read-back instruction, reads data in the FPGA configuration memory according to the address sequence, generates bit stream data, generates a read-back file according to the bit stream data, wherein the read-back of the external refreshing device to the FPGA is controlled through a read-write register, the bit stream data is a data stream when the FPGA loads the configuration file into the configuration memory, and the read-back operation is to restore another data stream from the configuration memory to the external refreshing device, so as to generate the read-back file;
the comparison module is used for reading the bit file stored in the external memory, comparing the bit file with the read-back file, and if the bit file is different from the read-back file, generating an error by the FPGA;
the searching module is used for acquiring a first data packet with errors in the readback file according to the comparison result, and searching a correct second data packet corresponding to the first data packet in the bit file;
The refreshing module is used for writing the second data packet into the configuration memory of the FPGA according to preset refreshing logic through the preset data transmission interface to complete real-time online configuration refreshing of the FPGA;
The preset refreshing logic sequentially comprises the following steps: the method comprises the steps of command head data refreshing, data part refreshing and command tail data refreshing, wherein the command head data is automatically generated by an external refresher and comprises an AA995566 synchronous word, a write CMD register, a write WCFG command, a write FDRI register and a written data quantity; a data section in which data is stored in the buffer; the command tail part is automatically generated by an external refreshing device;
Further comprises:
Building a fault tolerant circuit, wherein the fault tolerant circuit comprises: the system comprises an FPGA, a configuration manager, an external refreshing device and an external FLASH memory; the configuration manager is used for writing bit stream data into a configuration memory of the FPGA after the system is powered on, generating an FPGA circuit structure and completing configuration of the FPGA; the external refresher is used for controlling the read-back and refreshing operation of the FPGA; the external FLASH memory is used for storing a bit file, and when the FPGA is in error, the bit file is used for refreshing the FPGA;
further comprises: the loading module is used for writing the configuration file in the configuration manager into the configuration memory of the FPGA so as to read the readback file by the external equipment;
Further comprises: the register judging module is used for reading the value of the readback state register of the FPGA through the preset data transmission interface;
judging the value of the read-back status register, resetting the FPGA, reloading the configuration file, and then continuously reading the value of the read-back status register of the FPGA if the status register is abnormal; if the status register is normal, comparing the bit file with the readback file;
In the readback stage, reading the value of a STAT state register through a SELECTMAP interface, and resetting the FPGA and reloading bit stream data if the abnormal state value is read;
After compiling the FPGA program, the development environment generates a configuration file, and the configuration file is stored in a configuration manager in a solidifying mode; after the system is electrified, the FPGA loads a configuration file from a configuration manager, bit stream data is stored in the configuration file, the bit stream data consists of a plurality of data packets with the formats of packet header and packet body, wherein the packet header corresponds to an address of an internal configuration memory of the FPGA, and the packet body corresponds to a specific configuration instruction; the FPGA writes bit stream data into a configuration memory in the FPGA from a configuration management device according to control logic to generate an internal circuit structure, so as to realize a program function, and the FPGA starts working after the configuration is completed;
The relationship of the bit file, the configuration file and the read-back file is: in terms of content, the three files are the jic files generated by the development environment, the bit files and the configuration files are the jic files directly downloaded into FLASH, wherein the bit files are the jic files stored in an external FLASH memory, and the configuration files are the jic files stored in the configuration manager 2; the read-back file is a file restored from the configuration memory of the FPGA1 by the external refresher reading back the FPGA 1.
4. A read-back refreshing system for an FPGA as claimed in claim 3 wherein said comparison module is further configured to return to continue reading said read-back file if said bit file is the same as said read-back file, and if no error occurs in the FPGA.
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