CN113778822B - Error correction capability test method and device, readable storage medium and electronic equipment - Google Patents
Error correction capability test method and device, readable storage medium and electronic equipment Download PDFInfo
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- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3466—Performance evaluation by tracing or monitoring
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
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Abstract
The invention discloses an error correction capability test method, an error correction capability test device, a readable storage medium and electronic equipment, which are used for receiving a flash memory error correction capability test request of a hard disk to be tested, and writing test data in the test request into a flash memory based on a flash memory conversion layer of the hard disk to be tested; acquiring original data corresponding to the test data from the flash memory based on firmware of the hard disk to be tested through a protocol interface, and modifying the original data according to a preset rule to obtain modified original data; the method comprises the steps of sending an overwriting instruction corresponding to original data before modification to firmware through a protocol interface, wherein the overwriting instruction comprises the original data after modification; based on the flash memory conversion layer, reading the test data corresponding to the modified original data from the flash memory, acquiring the health information of the hard disk to be tested according to the received reading completion information, and obtaining the test result of the test request according to the health information, thereby improving the effectiveness and controllability of error correction capability test.
Description
Technical Field
The present invention relates to the field of memory technologies, and in particular, to a method and apparatus for testing error correction capability, a readable storage medium, and an electronic device.
Background
An SSD (Solid State Disk) storage medium is Nand-flash (NAND flash memory). With the increase of the service time and the influence of the ambient temperature, the Nand-flash is easy to cause instability of the charge amount of each memory cell in the repeated erase/program/read process, and when data is read from the Nand-flash, the read failure occurs. In order to make the data as error-free as possible, FW (FirmWare) and HW (Hard Ware) do a lot of work, including hardware error correction and software error correction, different manufacturers' implementation modes are different, but their purpose is to restore the data to a consistent state when the data is error-prone. At present, for testing the error correction capability of the NAND flash memory, the whole disk is generally put into a high-temperature box for baking, and collision is carried out by utilizing random probability, so that a controllable and effective testing method is difficult.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: provided are an error correction capability test method, an error correction capability test device, a readable storage medium, and an electronic device, which can improve the effectiveness and controllability of error correction capability test.
In order to solve the technical problems, the invention adopts a technical scheme that:
an error correction capability test method, comprising:
receiving a flash memory error correction capability test request of a hard disk to be tested, and writing test data in the test request into the flash memory based on a flash memory conversion layer of the hard disk to be tested;
acquiring original data corresponding to the test data from the flash memory based on the firmware of the hard disk to be tested through a protocol interface, and modifying the original data according to a preset rule to obtain modified original data;
transmitting an overwriting instruction corresponding to the original data before modification to the firmware through a protocol interface, wherein the overwriting instruction comprises the original data after modification;
and reading test data corresponding to the modified original data from the flash memory based on the flash memory conversion layer, acquiring health information of the hard disk to be tested according to the received reading completion information, and obtaining a test result of the test request according to the health information.
In order to solve the technical problems, the invention adopts another technical scheme that:
an error correction capability test apparatus comprising:
the data writing module is used for writing test data in the test request into the flash memory based on a flash memory conversion layer of the hard disk to be tested according to the received flash memory error correction capability test request of the hard disk to be tested;
the data modification module is used for acquiring original data corresponding to the test data from the flash memory based on the firmware of the hard disk to be tested through a protocol interface, and modifying the original data according to a preset rule to obtain modified original data;
the command sending module is used for sending an overwriting command corresponding to the original data before modification to the firmware through a protocol interface, wherein the overwriting command comprises the original data after modification;
and the test result determining module is used for reading the test data corresponding to the modified original data from the flash memory based on the flash memory conversion layer, acquiring the health information of the hard disk to be tested according to the received reading completion information, and obtaining the test result of the test request according to the health information.
In order to solve the technical problems, the invention adopts another technical scheme that:
a computer readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of a method of testing error correction capability as described above.
In order to solve the technical problems, the invention adopts another technical scheme that:
an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of a method for testing error correction capability as described above when the computer program is executed.
The invention has the beneficial effects that: the method comprises the steps of firstly writing normal data based on a flash memory conversion layer, then obtaining original data corresponding to test data from a flash memory based on firmware through a protocol interface, modifying the original data according to a preset rule, then overwriting the original data with modified original data, then obtaining a test result according to health information of a hard disk to be tested after the test data is read normally, after the normal data writing is completed, modifying the original data based on the firmware, skipping the flash memory conversion layer, avoiding triggering an automatic error correction mechanism in the flash memory conversion layer, and not using random probability collision test to test error correction capability like the prior art, but using the protocol interface to test, constructing a controllable test scene, improving the controllability of error correction capability test, under the condition that the error correction capability is normal, firstly modifying the original data according to the preset rule, then triggering an automatic error correction mechanism/ECC (Uncorrectable Error Correcting Code error/Error Checking and Correction) of a hard disk when the test data is read normally, checking error/checking and correcting the health information of the hard disk, and checking the corresponding information of the UNC/ECC can be checked through the health information of the hard disk, so that whether the error correction capability is normal or not can be judged, thereby improving the effectiveness and controllability of error correction capability.
Drawings
FIG. 1 is a flow chart illustrating steps of a method for testing error correction capability according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an error correction capability test apparatus according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a host in a method for testing error correction capability according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a host in a method for testing error correction capability according to an embodiment of the present invention for reading and writing data through a VU;
FIG. 6 is a reference diagram of a standard interaction format of a VU in an error correction capability test method according to an embodiment of the present invention;
fig. 7 is a flowchart of a method for testing error correction capability according to an embodiment of the present invention.
Detailed Description
In order to describe the technical contents, the achieved objects and effects of the present invention in detail, the following description will be made with reference to the embodiments in conjunction with the accompanying drawings.
Referring to fig. 1, an embodiment of the present invention provides a method for testing error correction capability, including:
receiving a flash memory error correction capability test request of a hard disk to be tested, and writing test data in the test request into the flash memory based on a flash memory conversion layer of the hard disk to be tested;
acquiring original data corresponding to the test data from the flash memory based on the firmware of the hard disk to be tested through a protocol interface, and modifying the original data according to a preset rule to obtain modified original data;
transmitting an overwriting instruction corresponding to the original data before modification to the firmware through a protocol interface, wherein the overwriting instruction comprises the original data after modification;
and reading test data corresponding to the modified original data from the flash memory based on the flash memory conversion layer, acquiring health information of the hard disk to be tested according to the received reading completion information, and obtaining a test result of the test request according to the health information.
From the above description, the beneficial effects of the invention are as follows: the method comprises the steps of firstly writing normal data based on a flash memory conversion layer, then obtaining original data corresponding to test data from a flash memory based on firmware through a protocol interface, modifying the original data according to a preset rule, then overwriting the original data with modified original data, then obtaining a test result according to health information of a hard disk to be tested after the test data is read normally, after the normal data writing is completed, modifying the original data based on the firmware, skipping the flash memory conversion layer, avoiding triggering an automatic error correction mechanism in the flash memory conversion layer, and not using random probability collision test to test error correction capability like the prior art, but using the protocol interface to test, constructing a controllable test scene, improving the controllability of error correction capability test, under the condition that the error correction capability is normal, firstly modifying the original data according to the preset rule, then triggering an automatic error correction mechanism/ECC (Uncorrectable Error Correcting Code error/Error Checking and Correction) of a hard disk when the test data is read normally, checking error/checking and correcting the health information of the hard disk, and checking the corresponding information of the UNC/ECC can be checked through the health information of the hard disk, so that whether the error correction capability is normal or not can be judged, thereby improving the effectiveness and controllability of error correction capability.
Further, before writing the test data in the test request into the flash memory based on the flash memory conversion layer of the hard disk to be tested according to the received flash memory error correction capability test request of the hard disk to be tested, the method includes:
receiving a full-disc formatting instruction;
and formatting the hard disk to be tested according to the full-disk formatting instruction.
According to the description, the hard disk to be tested is formatted before testing, so that the moving of the existing data in the normal running process of the hard disk to be tested can be avoided, the influence on testing is effectively reduced, and the reliability of error correction capability testing is further improved.
Further, writing the test data in the test request into the flash memory based on the flash memory conversion layer of the hard disk to be tested according to the received flash memory error correction capability test request of the hard disk to be tested includes:
selecting any target logic block address from the flash memory according to the received flash memory error correction capability test request of the hard disk to be tested;
and writing the test data in the test request into the target logic block address of the flash memory based on the flash memory conversion layer of the hard disk to be tested.
From the above description, the test data is written into the target logical block address of the flash memory through the flash memory conversion layer, so as to realize normal writing of the data.
Further, before the obtaining, by the protocol interface, the original data corresponding to the test data from the flash memory based on the firmware of the hard disk to be tested, the method includes:
acquiring a data pointer corresponding to the target logical block address;
transmitting the target logical block address and the data pointer to firmware of the hard disk to be tested through a protocol interface;
receiving a physical address corresponding to the target logical block address sent by the firmware;
the obtaining, by the protocol interface, the original data corresponding to the test data from the flash memory based on the firmware of the hard disk to be tested includes:
transmitting the physical address and the data pointer to firmware of the hard disk to be tested through a protocol interface;
and receiving original data which is sent by the firmware and corresponds to the test data obtained from the flash memory according to the physical address and the data pointer.
As can be seen from the above description, the physical address corresponding to the target logical block address is the real position of the test data on the flash memory, which is favorable for sending the physical address and the data pointer to the firmware through the protocol interface, and obtaining the original data from the flash memory through the firmware, so that the original data on the flash memory can be directly obtained by bypassing the flash memory conversion layer without affecting the original function of the flash memory conversion layer, and the subsequent data processing is facilitated.
Further, the modifying the original data according to a preset rule, and obtaining modified original data includes:
determining a target bit with a bit value of a first preset value from the original data;
determining a preset number of bits to be modified from the target bits;
and modifying the value of the bit to be modified to a second preset value to obtain modified original data.
From the above description, the number of the modified bits determines whether ECC or UNC will be triggered later, and the tester can set the preset number according to the test requirement, so that a controllable test scene is simply and effectively constructed, and the controllability of the test is improved.
Further, the reading, based on the flash memory conversion layer, the test data corresponding to the modified original data from the flash memory includes:
reading test data corresponding to the modified original data from the target logical block address of the flash memory based on the flash memory conversion layer;
the health information comprises a historical UNC value, a historical ECC value, a current UNC value and a current ECC value;
the obtaining the test result of the test request according to the health information comprises the following steps:
judging whether the current UNC value is larger than the historical UNC value, if so, the error correction capability of the flash memory is normal, and if not, the error correction capability of the flash memory is abnormal;
or judging whether the current ECC value is larger than the historical ECC value, if so, the error correction capability of the flash memory is normal, and if not, the error correction capability of the flash memory is abnormal.
As can be seen from the above description, the UNC value indicates the number of times of occurrence of UNC, and the ECC value indicates the number of times of occurrence of ECC, and by comparing the current UNC value with the historical UNC value or comparing the current ECC value with the historical ECC value, it can be quickly determined whether the ECC/UNC of the flash memory is triggered when the test data corresponding to the modified original data is read normally, so that the reliability of the error correction capability of the flash memory can be effectively tested, and the effectiveness of the error correction capability test is improved.
Further, the protocol interface is a VENDOR UNQUE.
Referring to fig. 2, another embodiment of the present invention provides an error correction capability test apparatus, including:
the data writing module is used for writing test data in the test request into the flash memory based on a flash memory conversion layer of the hard disk to be tested according to the received flash memory error correction capability test request of the hard disk to be tested;
the data modification module is used for acquiring original data corresponding to the test data from the flash memory based on the firmware of the hard disk to be tested through a protocol interface, and modifying the original data according to a preset rule to obtain modified original data;
the command sending module is used for sending an overwriting command corresponding to the original data before modification to the firmware through a protocol interface, wherein the overwriting command comprises the original data after modification;
and the test result determining module is used for reading the test data corresponding to the modified original data from the flash memory based on the flash memory conversion layer, acquiring the health information of the hard disk to be tested according to the received reading completion information, and obtaining the test result of the test request according to the health information.
Another embodiment of the present invention provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of a method for testing error correction capability described above.
Referring to fig. 3, another embodiment of the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and capable of running on the processor, where the processor implements the steps of the above-mentioned error correction capability test method when executing the computer program.
The error correction capability test method, the device, the readable storage medium and the electronic equipment of the present invention can be applied to a flash memory having error correction capability, such as a NAND-flash (NAND flash), and the following description is made by specific embodiments:
example 1
Referring to fig. 1, 4, 6-7, first, the normal writing process of data from host (host) to NAND-flash is: assuming that a user writes a user data (user data) with a data amount of 16K from host, the FTL layer (Flash translation layer, flash conversion layer) will carry a certain amount of verification data after receiving the data, referred to herein as metadata (meta data), if the metadata has 2K, the total 16k+2k data will be written onto the NAND-flash at the back end, so that 18K data is written in total when writing the NAND-flash; when host reads data from NAND-flash, the data which need to be read 18K altogether is returned to host after being checked by the FTL layer, as shown in FIG. 4;
as can be seen from fig. 4, no matter how read or write, the data is processed by the FTL layer, for example, optimizing performance and processing error data, if bad block data and a data block with high ECC value are encountered, the FTL layer may directly process the data, so that it is not easy to grasp to verify the bad block/weak block of the NAND-flash, and a controllable test scene cannot be constructed;
therefore, before testing, development and design of a VENDOR UNIQUE (VU) protocol interface is required, and the implementation function of the VU is defined as follows:
(1) LBA (logical block address ) and data pointer can be transferred to firmware through VU, and command it to return PUA (physical unit address, physical address on NAND-flash) corresponding to LBA;
(2) The PUA and the data pointer can be transmitted to the firmware through the VU, and the firmware is instructed to return raw data;
(3) The PUA and the data pointer can be transmitted to the firmware through the VU, so that the firmware can overwrite the raw data corresponding to the PUA, and command the firmware to return the execution success information;
the standard interaction format of VU may refer to NVMe spec (Non-Volatile Memory express spec, nonvolatile memory host controller interface specification), as shown in fig. 6;
the error correction capability test method of the embodiment comprises the following steps:
s1, receiving a full-disc formatting instruction;
s2, formatting the hard disk to be tested according to the full-disk formatting instruction;
specifically, format (format) is performed on the SSD to be tested according to the full disk formatting instruction;
s3, receiving a flash memory error correction capability test request of the hard disk to be tested, and writing test data in the test request into the flash memory based on a flash memory conversion layer of the hard disk to be tested;
specifically, as shown in fig. 7, any target logical block address is selected from the flash memory according to the received flash memory error correction capability test request of the hard disk to be tested;
writing test data in the test request into the target logic block address of the flash memory based on a flash memory conversion layer of the hard disk to be tested;
in an alternative embodiment, assuming that the test data is 16K, a valid target LBA is randomly selected from the NAND-flash, for example, LBA1, and host writes the 16K data normally, that is, writes the 16K data into LBA1 of the flash memory through the FTL layer;
s4, acquiring a data pointer corresponding to the target logical block address;
transmitting the target logical block address and the data pointer to firmware of the hard disk to be tested through a protocol interface;
receiving a physical address corresponding to the target logical block address sent by the firmware;
specifically, since the implementation function of the VU is defined before the test, a data pointer corresponding to the LBA1 is acquired, the host sends the LBA1 and the data pointer to the firmware through the VU, and commands the host to return to the corresponding PUA1 of the LBA1, wherein the PUA1 is the real position of the 16K data on the NAND-flash;
s5, acquiring original data corresponding to the test data from the flash memory based on the firmware of the hard disk to be tested through a protocol interface, and modifying the original data according to a preset rule to obtain modified original data;
s6, sending an overwriting instruction corresponding to the original data before modification to the firmware through a protocol interface, wherein the overwriting instruction comprises the original data after modification;
and S7, reading test data corresponding to the modified original data from the flash memory based on the flash memory conversion layer, acquiring health information of the hard disk to be tested according to the received reading completion information, and obtaining a test result of the test request according to the health information.
Example two
Referring to fig. 1, 5 and 7, the present embodiment further defines how to acquire the original data, modify the original data and complete the test based on the first embodiment, specifically:
the step S5 specifically comprises the following steps:
transmitting the physical address and the data pointer to firmware of the hard disk to be tested through a protocol interface;
receiving original data which is sent by the firmware and corresponds to the test data obtained from the flash memory according to the physical address and the data pointer;
determining a target bit with a bit value of a first preset value from the original data;
determining a preset number of bits to be modified from the target bits;
modifying the value of the bit to be modified to a second preset value to obtain modified original data;
it should be noted that, because of the corresponding relationship between LBA and PUA, one PUA unit is operated at a time, different FWs (FirmWare) have different constraints and regulations, and the hard disk protocol standard is required to be determined according to an actual development version, and is not limited to SATA/NVME (hard disk interface specification/non-volatile memory host controller interface specification), and in principle, the overwriting only allows the value of the original data bit to be changed from "1" to "0";
therefore, in this embodiment, the first preset value is 1, the second preset value is 0, and the preset number determines whether UNC or ECC is triggered, which can be flexibly set according to actual situations;
specifically, as shown in fig. 7, host sends PUA1 and data pointer to firmware through VU, commands it to return raw_data1 of the 16K data, and if more than 50 bits need to be modified in test to trigger UNC, and not more than 50 bits need to be modified to trigger ECC, then the preset number is set to 55, the UNC is triggered, a target bit with bit value of 1 is determined from raw_data1, 55 bits to be modified are determined from the target bit, the value of the bit to be modified is modified to 0, and modified original data, namely raw_data1, is obtained;
the step S7 is specifically as follows:
as shown in fig. 7, based on the flash memory conversion layer, reading test data corresponding to the modified original data from the target logical block address of the flash memory;
the health information comprises a historical UNC value, a historical ECC value, a current UNC value and a current ECC value;
judging whether the current UNC value is larger than the historical UNC value, if so, the error correction capability of the flash memory is normal, and if not, the error correction capability of the flash memory is abnormal;
or judging whether the current ECC value is larger than the historical ECC value, if so, the error correction capability of the flash memory is normal, and if not, the error correction capability of the flash memory is abnormal;
specifically, host reads test data normally, namely, reads test data of LBA on NAND-flash through FTL layer, should trigger ECC or UNC at this moment, firmware and hardware will make corresponding processing at the same time, the hardware will correct error condition and return to firmware, if firmware receives UNC and produces, will mark bad block to manage, and return to host and read I/O (input/output) error, if firmware receives ECC and produces, mark this block bit as the weak block;
as described above, assuming that the preset number is set to 55, the UNC is triggered, then it can be determined whether the current UNC value is greater than the historical UNC value, if yes, the error correction capability of the NAND-flash is normal, if no, the error correction capability of the NAND-flash is abnormal, assuming that the preset number is set to 20, the ECC is triggered, then it can be determined whether the current ECC value is greater than the historical ECC value, if yes, the error correction capability of the NAND-flash is normal, and if no, the error correction capability of the NAND-flash is abnormal;
the data on the NAND-flash can be directly acquired by bypassing the FTL layer through the VU without affecting the original function of the FTL layer, and returned to the host, or the data can be written into the NAND-flash without passing through the FTL layer, so that the raw data (original data) on the NAND-flash can be indirectly destroyed, UNC/ECC is generated, and then the host is used for normally reading to trigger the FTL layer to process abnormality, thereby verifying the error correction capability, as shown in figure 5.
Example III
Referring to fig. 2, an error correction capability test apparatus includes:
the data writing module is used for writing test data in the test request into the flash memory based on a flash memory conversion layer of the hard disk to be tested according to the received flash memory error correction capability test request of the hard disk to be tested;
the data modification module is used for acquiring original data corresponding to the test data from the flash memory based on the firmware of the hard disk to be tested through a protocol interface, and modifying the original data according to a preset rule to obtain modified original data;
the command sending module is used for sending an overwriting command corresponding to the original data before modification to the firmware through a protocol interface, wherein the overwriting command comprises the original data after modification;
and the test result determining module is used for reading the test data corresponding to the modified original data from the flash memory based on the flash memory conversion layer, acquiring the health information of the hard disk to be tested according to the received reading completion information, and obtaining the test result of the test request according to the health information.
Example IV
A computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the error correction capability test method of either embodiment one or embodiment two.
Example five
Referring to fig. 3, an electronic device includes a memory, a processor, and a computer program stored on the memory and executable on the processor, where the processor implements the steps of the error correction capability test method in the first or second embodiments when executing the computer program.
In summary, according to the error correction capability test method, the device, the readable storage medium and the electronic equipment provided by the invention, test data in a test request is written into a flash memory based on a flash memory conversion layer of a hard disk to be tested, then a target logical block address and a data pointer are sent to firmware through a protocol interface, a physical address corresponding to the target logical block address is received, the physical address and the data pointer are sent to the firmware through the protocol interface, original data sent by the firmware is received, and the flash memory conversion layer can be bypassed under the condition that the original function of the flash memory conversion layer is not affected, so that the original data on the flash memory can be directly obtained; the method comprises the steps of modifying original data according to a preset rule, sending an overwriting instruction corresponding to the original data before modification to firmware through a protocol interface, overwriting the original data before modification into the original data after modification by the firmware, skipping a flash memory conversion layer, avoiding triggering an automatic error correction mechanism in the flash memory conversion layer, simply and effectively constructing a controllable test scene, then reading test data corresponding to the original data after modification from a target logic block address of the flash memory based on the flash memory conversion layer, triggering UNC/ECC at the moment, comparing a current UNC value with a historical UNC value according to acquired health information, or comparing the current ECC value with the historical ECC value, so as to judge whether error correction capability is normal or not, effectively testing the reliability of the error correction capability, and therefore improving the effectiveness and controllability of the error correction capability test.
In the foregoing embodiments provided by the present application, it should be understood that the disclosed method, apparatus, computer readable storage medium and electronic device may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, and for example, the division of the modules is merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple components or modules may be combined or integrated into another apparatus, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with respect to each other may be an indirect coupling or communication connection via some interfaces, devices or components or modules, which may be in electrical, mechanical, or other forms.
The components illustrated as separate components may or may not be physically separate, and components shown as components may or may not be physical modules, i.e., may be located in one place, or may be distributed over multiple network modules. Some or all of the components may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional module in each embodiment of the present invention may be integrated into one processing module, or each component may exist alone physically, or two or more modules may be integrated into one module. The integrated modules may be implemented in hardware or in software functional modules.
The integrated modules, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied essentially or in part or all of the technical solution or in part in the form of a software product stored in a storage medium, including instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
It should be noted that, for the sake of simplicity of description, the foregoing method embodiments are all expressed as a series of combinations of actions, but it should be understood by those skilled in the art that the present invention is not limited by the order of actions described, as some steps may be performed in other order or simultaneously in accordance with the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily all required for the present invention.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments.
The foregoing description is only illustrative of the present invention and is not intended to limit the scope of the invention, and all equivalent changes made by the specification and drawings of the present invention, or direct or indirect application in the relevant art, are included in the scope of the present invention.
Claims (8)
1. An error correction capability test method, comprising:
receiving a flash memory error correction capability test request of a hard disk to be tested, and writing test data in the test request into the flash memory based on a flash memory conversion layer of the hard disk to be tested;
acquiring original data corresponding to the test data from the flash memory based on the firmware of the hard disk to be tested through a protocol interface, and modifying the original data according to a preset rule to obtain modified original data;
transmitting an overwriting instruction corresponding to the original data before modification to the firmware through a protocol interface, wherein the overwriting instruction comprises the original data after modification;
based on the flash memory conversion layer, reading test data corresponding to the modified original data from the flash memory, acquiring health information of the hard disk to be tested according to the received reading completion information, and obtaining a test result of the test request according to the health information;
writing the test data in the test request into the flash memory based on the flash memory conversion layer of the hard disk to be tested according to the received flash memory error correction capability test request of the hard disk to be tested comprises:
selecting any target logic block address from the flash memory according to the received flash memory error correction capability test request of the hard disk to be tested;
writing test data in the test request into the target logic block address of the flash memory based on a flash memory conversion layer of the hard disk to be tested;
the reading the test data corresponding to the modified original data from the flash memory based on the flash memory conversion layer comprises the following steps:
reading test data corresponding to the modified original data from the target logical block address of the flash memory based on the flash memory conversion layer;
the health information comprises a historical UNC value, a historical ECC value, a current UNC value and a current ECC value;
the obtaining the test result of the test request according to the health information comprises the following steps:
judging whether the current UNC value is larger than the historical UNC value, if so, the error correction capability of the flash memory is normal, and if not, the error correction capability of the flash memory is abnormal;
or judging whether the current ECC value is larger than the historical ECC value, if so, the error correction capability of the flash memory is normal, and if not, the error correction capability of the flash memory is abnormal.
2. The method for testing the error correction capability according to claim 1, wherein the step of writing the test data in the test request to the flash memory based on the flash memory conversion layer of the hard disk to be tested according to the received flash memory error correction capability test request of the hard disk to be tested comprises:
receiving a full-disc formatting instruction;
and formatting the hard disk to be tested according to the full-disk formatting instruction.
3. The method for testing error correction capability according to claim 1, wherein before the obtaining, by the protocol interface, the original data corresponding to the test data from the flash memory based on the firmware of the hard disk to be tested, the method comprises:
acquiring a data pointer corresponding to the target logical block address;
transmitting the target logical block address and the data pointer to firmware of the hard disk to be tested through a protocol interface;
receiving a physical address corresponding to the target logical block address sent by the firmware;
the obtaining, by the protocol interface, the original data corresponding to the test data from the flash memory based on the firmware of the hard disk to be tested includes:
transmitting the physical address and the data pointer to firmware of the hard disk to be tested through a protocol interface;
and receiving original data which is sent by the firmware and corresponds to the test data obtained from the flash memory according to the physical address and the data pointer.
4. The method for testing error correction capability according to claim 1, wherein said modifying the original data according to a preset rule to obtain modified original data comprises:
determining a target bit with a bit value of a first preset value from the original data;
determining a preset number of bits to be modified from the target bits;
and modifying the value of the bit to be modified to a second preset value to obtain modified original data.
5. The method of claim 1, wherein the protocol interface is a vector unit.
6. An error correction capability test apparatus, comprising:
the data writing module is used for writing test data in the test request into the flash memory based on a flash memory conversion layer of the hard disk to be tested according to the received flash memory error correction capability test request of the hard disk to be tested;
the data modification module is used for acquiring original data corresponding to the test data from the flash memory based on the firmware of the hard disk to be tested through a protocol interface, and modifying the original data according to a preset rule to obtain modified original data;
the command sending module is used for sending an overwriting command corresponding to the original data before modification to the firmware through a protocol interface, wherein the overwriting command comprises the original data after modification;
the test result determining module is used for reading the test data corresponding to the modified original data from the flash memory based on the flash memory conversion layer, acquiring the health information of the hard disk to be tested according to the received reading completion information, and obtaining the test result of the test request according to the health information;
writing the test data in the test request into the flash memory based on the flash memory conversion layer of the hard disk to be tested according to the received flash memory error correction capability test request of the hard disk to be tested comprises:
selecting any target logic block address from the flash memory according to the received flash memory error correction capability test request of the hard disk to be tested;
writing test data in the test request into the target logic block address of the flash memory based on a flash memory conversion layer of the hard disk to be tested;
the reading the test data corresponding to the modified original data from the flash memory based on the flash memory conversion layer comprises the following steps:
reading test data corresponding to the modified original data from the target logical block address of the flash memory based on the flash memory conversion layer;
the health information comprises a historical UNC value, a historical ECC value, a current UNC value and a current ECC value;
the obtaining the test result of the test request according to the health information comprises the following steps:
judging whether the current UNC value is larger than the historical UNC value, if so, the error correction capability of the flash memory is normal, and if not, the error correction capability of the flash memory is abnormal;
or judging whether the current ECC value is larger than the historical ECC value, if so, the error correction capability of the flash memory is normal, and if not, the error correction capability of the flash memory is abnormal.
7. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of a method for testing error correction capability according to any one of claims 1 to 5.
8. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the steps of a method for testing error correction capability according to any one of claims 1 to 5 when the computer program is executed by the processor.
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| CN114822677B (en) * | 2022-05-20 | 2023-05-09 | 深圳市金胜电子科技有限公司 | Information recording method and device of NAND flash memory chip, electronic equipment and medium |
| CN114822669B (en) * | 2022-06-29 | 2022-09-02 | 北京得瑞领新科技有限公司 | Flash memory error injection system, solid-state storage device and test system |
| CN114999559B (en) * | 2022-08-03 | 2022-11-29 | 合肥康芯威存储技术有限公司 | Method and system for testing memory chip and storage medium |
| CN116364163B (en) * | 2023-04-17 | 2023-11-10 | 武汉喻芯半导体有限公司 | Error correction method and system based on NAND flash memory controller |
| CN116884469B (en) * | 2023-06-08 | 2024-05-07 | 珠海妙存科技有限公司 | Flash memory performance detection method, device, equipment and medium |
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