JP4572859B2 - Cache memory control device, method and program, and disk array device - Google Patents

Description

  The present invention relates to a cache memory control device for controlling a cache memory in a disk array device.

  As a cache memory of a disk array device, an inexpensive and large-capacity volatile memory (DRAM) is used. As a means for detecting and correcting a data error when a soft error occurs, an error correction code ECC (Error Checking) is generally used. and Correcting Code). The ECC generates a check bit from a data bit using a Hamming code, writes the data bit and the check bit into the DRAM, and generates a syndrome from the read data bit and the check bit when the memory is read. Bit error correction and 2-bit error detection are performed.

  When a DRAM is used, burst transfer (burst write or burst read), which is a function of the DRAM and continuously inputs and outputs a certain number of data, is used. In burst transfer, the length of continuous transfer (burst length) must be set in the DRAM mode register after the power and clock are supplied to the DRAM. Once set, the set value (burst length) is held until the setting is performed again or the power is turned off. Therefore, in general, access to the DRAM is always performed with a fixed burst length.

  In the prior art, before the data is transferred to the cache memory, the cache memory data initialization process is performed in which padding data for setting the DRAM internal data and its ECC are written to the entire area of the cache memory. . The reason for this is that the cache memory of this type of disk array device is composed of a volatile memory, so in the cache memory employing the error correction code ECC, the DRAM internal data at power-on is an indeterminate value. This is because an access less than the burst length set in the DRAM occurs during normal cache memory access.

Japanese Patent Laid-Open No. 10-269150

  The first problem is that the initialization process of the cache memory must be performed whenever the power is turned on or the failure is recovered. Generally, the DRAM used in the cache memory of the disk array device has an indeterminate value inside the DRAM when the power is turned on, and the partial transfer that does not satisfy the data width of the cache memory during normal memory access Since data transfer that does not meet the burst length set in the DRAM occurs, initialization processing is required to perform burst write of the padding data and its ECC to the entire cache memory area before data transfer to the cache memory. It was.

  The second problem is that the initialization process of the cache memory is proportional to the amount of cache memory installed and the processing time is long. In recent years, the cache memory of a disk array device has been increased in capacity, and it takes a lot of time to write padding data to the entire area of the cache memory, which is the initialization process of DRAM data. Even in a state of being mounted on a system, there is a period during which it cannot be used for data transfer.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a cache memory control device and the like that do not require time for cache memory initialization processing and can immediately start read transfer or write transfer to the cache memory.

  A cache memory control device according to the present invention controls a cache memory provided in a disk array device, and includes a management table, table control means, and burst control means. The management table divides the address space of the cache memory into a plurality of divided address spaces, and manages a completion flag indicating completion or incomplete of data initialization for each divided address space. The table control means reads from the management table the divided address space including the transfer address and the completion flag thereof among the transfer address and transfer data output from the host computer side. When the completion flag read by the table control means indicates incomplete, the burst control means changes the transfer address and the transfer data so that the data is written in the entire divided address space corresponding to the completion flag. Generated) and output to the cache memory and when the completion flag is instructed to be rewritten, and the completion flag read by the table control means indicates completion, the transfer address and the transfer data remain unchanged. Instructs output to cache memory.

  The cache memory control method according to the present invention captures the operation of the cache memory control device according to the present invention as a method invention. The cache memory control program according to the present invention is for causing a computer to function each means of the cache memory control device according to the present invention. The disk array device according to the present invention includes the cache memory control device according to the present invention.

  In the prior art, data initialization is performed for the entire area of the address space of the cache memory. On the other hand, in the present invention, a management table or the like is used instead of not performing the data initialization. In the management table, a completion flag indicating completion or incomplete of data initialization is managed for each divided address space. If the completion flag of the divided address space including the transfer address is incomplete, writing the transfer address and transfer data as it is into the divided address space leaves a data area with an indeterminate value in part of the divided address space. It will be. Therefore, by changing the transfer address and transfer data, the data is written in the entire divided address space. As a result, it is not necessary to initialize the data in the address space of the cache memory, so that data can be immediately transferred to the cache memory at the time of startup or the like.

  The present invention can also be configured as follows.

  The present invention includes a management table, table control means, burst control means, address conversion means, padding means and the like. The management table manages a burst address space obtained by dividing the address space of the mounted cache memory by the burst length of the DRAM, and a completion flag indicating completion / uncompletion of initialization processing of DRAM data in units of the burst address space. . The table control means indexes the management table from the transfer address indicated by the transfer address holding means, and performs read control of the burst address space corresponding to the transfer address and its completion flag. Based on the completion flag read from the management table and the transfer request information held in the transfer address holding means, the transfer length holding means, and the transfer command holding means, the burst control means uses the address and data at the time of DRAM access. Instructs conversion to and generation. The address conversion unit converts and generates the transfer address indicated by the transfer address holding unit into a transfer address to the DRAM in accordance with an instruction from the burst control unit. The padding means adds padding data to the transfer write data indicated by the transfer data holding means.

  Next, the operation of the present invention will be described. When the table control unit detects a transfer request to the cache memory (DRAM), the table control unit indexes entries in the management table based on the transfer address in the transfer address holding unit, and determines the burst address space including the transfer address. Search for. When the burst address space is detected, a completion flag corresponding to the burst address space is read. The burst control means refers to the completion flag read from the management table and the transfer command in the transfer command holding means, determines whether or not the initialization processing of the burst address space including the transfer address is completed, Instructions are given to the address conversion means and padding means to convert and generate each information of the transfer request into transfer address / length / data in accordance with the burst length of the DRAM. If the completion flag indicates that the initialization is not completed, the burst control means, when the data write operation (= initialization) to the burst address space that has not been initialized is completed, the burst in the management table The table control means is instructed to change the completion flag corresponding to the address space from “incomplete” to “completed”.

  In the present invention, based on the address requested to be transferred to the cache memory, the initialization completion or uncompleted status of the burst address space including the address is read from the management table. The address, length, and write data adjusted to the burst length are generated and transferred to the DRAM. This eliminates the need for initialization time for the cache memory when the disk array device is powered on or when a failure of the cache memory is recovered, so that read transfer or write transfer to the cache memory is immediately possible. In addition to providing a highly reliable memory access method for a disk array device, it is also possible to provide a memory access method for a disk array device having a short mean time to repair (MTTR).

  According to the present invention, when the disk array device is turned on or when the failure of the cache memory is recovered, the time for performing the initialization process of the cache memory is not required, so that read transfer or write transfer to the cache memory is immediately performed. It becomes possible.

  FIG. 1 is a block diagram showing a first embodiment of a cache memory control device according to the present invention. FIG. 2 is a chart showing an example of the management table in FIG. Hereinafter, description will be given based on these drawings.

  The cache memory control device 10 of this embodiment includes a management table 16, table control means 15, burst control means 18, address conversion means 17, padding means 19 and the like.

  The management table 16 manages a burst address space obtained by dividing an address space of the mounted cache memory by a DRAM burst length, and a completion flag indicating completion or incomplete of initialization processing of DRAM data in units of the burst address space. To do. The table control means 15 indexes the management table 16 from the transfer address indicated by the transfer address holding means 11, and performs read control of the burst address space corresponding to the transfer address and its completion flag. The burst control unit 18 accesses the DRAM based on each information of the completion flag read from the management table 16 and the transfer request held in the transfer address holding unit 11, the transfer length holding unit 12 and the transfer command holding unit 13. Instructs the conversion or generation to the time address and data. The address conversion unit 17 converts or generates a transfer address indicated by the transfer address holding unit 11 from a transfer address to the DRAM according to an instruction from the burst control unit 18. The padding means 19 adds padding data to the transfer write data indicated by the transfer data holding means 14.

  The table control means 15 operates as follows. When a transfer request to the cache memory (DRAM) is detected, the entries in the management table 16 are indexed based on the transfer address in the transfer address holding means 11 to search the burst address space containing the transfer address. When the burst address space is detected, a completion flag corresponding to the burst address space is read.

  The burst control means 18 operates as follows. With reference to the completion flag read from the management table 16 and the transfer command in the transfer command holding means 13, it is determined whether or not the initialization processing of the burst address space including the transfer address is completed, and each transfer request is determined. Instructions are given to the address conversion means 17 and the padding means 19 so that the information is converted or generated into transfer address / length / data matching the burst length of the DRAM. Further, when the completion flag indicates that the initialization is not completed, when the data write operation (= initialization) to the burst address space that has not been initialized is completed, the burst address space in the management table 16 is completed. The table control means 15 is instructed to change the completion flag corresponding to “incomplete” from “incomplete” to “completed”.

  Next, each component of the cache memory control device 10 will be described in more detail.

  The transfer address holding means 11, the transfer length holding means 12, the transfer command holding means 13 and the transfer data holding means 14 hold the address, length, command and data, which are each information of the transfer request to the cache memory. The transfer address holding means 11 indicates address designation indicating a DRAM area to which data is transferred. The transfer command holding means 13 indicates read, write, etc., which are types of transfer to the DRAM. The transfer length holding unit 12 indicates the length of the read / write request specified by the transfer command holding unit 13 and the transfer data specified by the transfer address specified by the transfer address holding unit 11. The management table 16 manages a burst address space obtained by dividing the mounted cache memory space by the burst length of the DRAM, and a completion flag indicating whether or not an initialization operation for the burst address space has been performed. When the table control means 15 detects a transfer request (transfer address or the like), it indexes the management table 16 from the transfer address and reads the corresponding burst address space and completion flag.

  The burst control means 18 operates as follows. Simultaneously with reference to the completion flag from the management table 16, the type of the transfer command held by the transfer command holding means 13 is determined, and initialization of DRAM data in the address space targeted for the transfer address requested for transfer is performed. It is determined whether or not it has been completed. Based on the determination result, it instructs the address converting means 17 and the padding means 19 to convert or generate each transfer requested information into a transfer address / length / data matching the burst length of the DRAM. When the completion flag indicates initialization / incomplete, when the data write operation (initialization) to the incomplete address space is completed, the completion flag corresponding to the corresponding burst address space in the management table 16 is set to “ The table control means 15 is instructed to change from “incomplete” to “completed”.

  As shown in FIG. 2, in the management table 16, a burst address space obtained by dividing the mounted cache memory space by the burst length of the DRAM and initialization (burst write) processing to the burst address space are performed. And a completion flag indicating whether or not. The completion flag is managed in one-to-one correspondence with the burst address space. If burst write (initialization of DRAM data) is performed even once for the corresponding burst address space, “complete” to “complete” Status is changed to Further, the completion flag of the burst address space at the time of power-on or at the time of unburst write (uninitialization) indicates a status of “incomplete”. In principle, the status is not changed from the “completed” status to the “incomplete” status.

  Next, the overall operation of the cache memory control device 10 will be described in more detail.

  When a transfer request to the cache memory is generated, the transfer address holding means 11, the transfer length holding means 12, the transfer command holding means 13 and the transfer data holding means 14 are respectively an address which is each information of the transfer request to the cache memory, Holds length, command and data.

  The table control means 15 operates as follows. When a transfer request is detected, the entries in the management table 16 are indexed based on the transfer address in the transfer address holding means 11, and a burst address space including the transfer address is searched. Then, after detecting the burst address space including the transfer address, the completion flag is read from the entry of the burst address space.

  The burst control means 18 operates as follows. With reference to the completion flag read from the management table 16, when the completion flag is “incomplete” and the transfer command in the transfer command holding means 13 is a write transfer, the transfer address holding means 11 and the transfer length holding means 12 The address conversion unit 17 and the padding unit 19 are instructed to convert or generate each information in the transfer command holding unit 13 and the transfer data holding unit 14 into a transfer address / length / data corresponding to the burst length of the DRAM. . The transfer boundary is determined by the burst length of the DRAM. The transfer length is expanded and converted to a length that is a constant multiple of the burst length of the DRAM. At the same time, it instructs the padding means 19 to add and convert the padding data to the write data at the time of the transfer request so as to satisfy the expanded length.

  The padding means 19 adds the padding data to the write data of the transfer request in response to an instruction from the burst control means 18 and expands and converts the data to the burst length data size. The address conversion means 17 also generates an address at the time of DRAM access based on the address boundary determined by the DRAM burst length by the same instruction from the burst control means 18. The address, length, data, and command converted or generated by each means become DRAM access information, and data transfer to the DRAM (cache memory) is performed.

  When the completion flag is “incomplete”, the burst control means 18 changes the completion flag corresponding to the burst address space from “incomplete” to “completed” when performing data transfer (initialization operation) to the burst address space. The table control means 15 is notified to change to "". On the other hand, when the completion flag indicates “complete”, initialization of DRAM data in the corresponding burst address space is completed. Therefore, even if a transfer request for the transfer address included in the burst address space is subsequently generated, the burst control means 18 does not perform address conversion or data padding, and transfers the requested address, length, and data to the cache memory. Perform data transfer.

  FIG. 3 is a block diagram for explaining the operation of the cache memory control device 10. FIG. 4 is a chart showing the management table 161 used in the operation shown in FIG. Hereinafter, the overall operation of the cache memory control device 10 will be described more specifically.

  3 and 4 show a case where a transfer request to the cache memory is generated when the DRAM burst length is set to 8 bytes × 32 cycles of 4 cycles. At this time, it is assumed that the transfer address is the 512th byte, the transfer length is 16 bytes, the transfer command is write, and the data initialization of the cache memory is not performed in all areas.

A transfer address 21, a transfer length 22, and a transfer command 23 are received as a transfer request 20 to the cache memory, and the write data 24 receives 16 bytes corresponding to the length. The table control unit 15 indexes the entry of the management table 161 based on the transfer address 21 when the transfer request 20 is received. Since the transfer address 21 is a 512-byte address, the burst address space in the management table 161 is included in the entry 1 address space. The completion flag is read based on the matched burst address space entry (entry 1). Since the cache memory has not been initialized, the completion flag is “incomplete = 0”.

  The burst control means 18 operates as follows. The read completion flag, transfer command 23, transfer address 21, and transfer length 22 are referred to. When the completion flag is “incomplete” and the transfer command 23 is a write, a conversion instruction is output to the address conversion unit 17 and the padding unit 19 in order to convert the transfer address 21 and the transfer length 22. At this time, the address conversion means 17 converts the address (no conversion in this example) and the transfer length 22 from 16 bytes to 32 bytes so as to match the burst setting of the DRAM. The write data 24 also instructs the padding means 19 to add padding data of “32 bytes-16 bytes” to 16 bytes of data. As a result, transfer information of the DRAM address 31, burst length 32, transfer command 33, and write data 34 to the DRAM is generated and written to the DRAM.

In the above description, the completion flag is assumed to be “incomplete” as a result of the indexing of the management table 161. However, when the completion flag is “completed” at this time, the burst control means 18 uses the address conversion means 17 or the padding means 19. Does not instruct the conversion of each transfer information. Therefore, the transfer address 21, the write data 24, and the transfer length 22 instructed by the transfer request 20 are not converted but become DRAM access information 30, and a write operation to the DRAM is performed.

  As described above, in this embodiment, the transfer address to the cache memory is referred to, the management table is indexed from the transfer address, the completion flag is read, and then referred to, and the burst address space of the requested transfer address is referred to. If it is not initialized, the address and length are expanded and converted so that the transfer request matches the DRAM burst setting, and the write data is also expanded. Burst address space in which the data value in the DRAM is not fixed (uninitialized) by padding the length of the data with the number of insufficient data, preparing the data as DRAM access information, and writing the data to the cache memory (DRAM). Can be transferred at the same time as normal write transfer, and DRAM data initialization is not required. That.

  Furthermore, in this embodiment, since a completion flag is provided for each burst address space obtained by dividing the entire area of the cache memory by the burst length of the DRAM, DRAM data initialization processing is not required regardless of the capacity of the cache memory. Therefore, the average recovery time can be shortened during the cache memory recovery operation.

  In addition, although the table control means and management table of this embodiment showed the example comprised by the hardware, you may manage and control by firmware etc. Further, the address conversion means and the padding means can also be configured by firmware.

  FIG. 5 is a flowchart showing an embodiment of the cache memory control method according to the present invention. Hereinafter, description will be given based on this drawing.

  The cache memory control method of the present embodiment corresponds to the operation in the first embodiment of the cache memory control device. First, create a plurality of burst address spaces by dividing the address space of the cache memory by the burst length of the DRAM, and a management table that manages a completion flag indicating completion or incomplete of data initialization for each burst address space Prepare (step 41). Subsequently, out of the transfer address and transfer data output from the host computer side, the burst address space including the transfer address and its completion flag are read from the management table (step 42). Subsequently, when the read completion flag indicates incompletion (step 43), the transfer address and the transfer data are changed so that the data is written in the entire burst address space corresponding to the completion flag and transferred to the cache memory. Instruct to output (step 44) and instruct to rewrite the completion flag to complete (step 45). On the other hand, when the read completion flag indicates completion (step 43), an instruction is given to output the transfer address and transfer data to the cache memory as they are (step 46).

  In the prior art, data initialization is performed for the entire area of the address space of the cache memory. On the other hand, in this embodiment, a management table is used instead of performing the data initialization. The management table manages a completion flag indicating completion or incomplete of data initialization for each burst address space. If the completion flag of the burst address space including the transfer address is incomplete, writing the transfer address and transfer data as it is to the burst address space leaves an undefined value data area in the burst address space. Become. Therefore, by changing the transfer address and transfer data, the data is written in the entire burst address space. As a result, it is not necessary to initialize the data in the address space of the cache memory, so that data can be immediately transferred to the cache memory at the time of startup or the like.

  FIG. 6 is a chart showing a management table in the second embodiment of the cache memory control apparatus according to the present invention. Hereinafter, description will be given based on this drawing.

  In the present embodiment, the basic configuration is the same as in the first embodiment, but the management table 50 is further devised. In the management table 50, for the entry 51, a read violation flag 53 is added to the burst address space 52 and the completion flag 54 to register a total of three elements. The functions related to the burst address space 52 and the completion flag 54 are the same as those in the first embodiment.

  When the table management means detects the transfer request, it indexes the entry 51 of the management table 50 from the transfer address, searches the entry 51 of the burst address space 52 including the transfer address, and completes corresponding to the detected burst address space 52 The flag 54 is read. At this time, if the transfer command is a read request and the read completion flag is “incomplete”, the burst control means is a space (burst address space) where initialization of DRAM data in the cache memory is not completed. The read violation flag is changed from “0” to “1”.

  In the case of a cache memory in which error correction code ECC is added to the cache memory (DRAM data) and error correction / detection is performed, an uncorrectable error occurs if read transfer is executed to an address for which DRAM data has not been initialized. End up. Therefore, in normal cache memory transfer, read transfer is not performed to an uninitialized address space. Such a read request for a burst address space that has not been initialized is limited to when there is a problem with the transfer control firmware or when a control circuit failure occurs.

  As described above, in this embodiment, when a read request to the cache memory is generated, the management table is indexed and the completion flag is read, so that the target memory space of the transfer address requested to read is initialized to DRAM data. It is determined whether or not the space is an uncompleted space (burst address space). As a result, it is possible to detect a malfunction in the control farm area and a failure in the control circuit at an early stage, and to obtain an effect of obtaining high reliability.

  It is a block diagram which shows 3rd embodiment of the cache memory control apparatus which concerns on this invention. Hereinafter, description will be given based on this drawing. However, the same parts as those in FIG.

  The cache memory control device 60 of this embodiment is provided with a diagnostic command holding means 61 for identifying a transfer command that is a transfer request to the cache memory. The diagnostic command holding means 61 has a function of detecting a diagnostic command that is one of transfer requests to the cache memory. A diagnostic command is a command for testing whether or not a soft error has occurred in a DRAM, unlike normal read / write transfer, and is transferred while being mixed with normal read / write transfer. It is used as.

  First, the operation when a diagnostic command is received when there is no diagnostic command holding means 61 will be described. The transfer address is also detected at the same time as the diagnosis command is detected, and the data and ECC are read from the cache memory (DRAM) based on each information of the diagnosis command request, and the consistency between the read data and the ECC is checked. Is done. When a correctable error is detected in the consistency check between the read data and the ECC, the read data or ECC is corrected, and the corrected data and ECC are written in the cache memory again. If an uncorrectable error is detected, rewriting is not performed.

  As described above, when the diagnosis command is detected, it is necessary to once read data from the DRAM. Therefore, the DRAM in the address space subject to the diagnosis request (command) must be initialized. There is. In addition, an address that is a target of a diagnostic command is selected as a diagnostic target regardless of whether it is used in normal read / write transfer. For this reason, a diagnostic command may be issued to an address space in which only initialization transfer of DRAM data is performed.

  Next, the operation when the diagnostic command holding means 61 is employed will be described. The operations from the detection of the transfer request to the reading of the completion flag are basically the same as the operation of the first embodiment described above. The burst control means 18 checks whether or not there is a diagnostic command in the diagnostic command holding means 61 when the completion flag of the burst address space including the transfer address is read.

  If there is a diagnostic command, diagnostic transfer to the DRAM is performed based on the status of the completion flag “completed” or “incomplete”. When the completion flag indicates “completed”, initialization of the data in the DRAM of the transfer address to be diagnosed has already been completed, and therefore normal diagnosis operation (consistency check after data and ECC reading) is performed. .

  On the other hand, when the completion flag indicates “incomplete”, the burst control means 18 adjusts the transfer address held by the transfer address holding means 11 to the DRAM burst length, and then once writes the data to the DRAM. . At the time of diagnosis command, the transfer request does not accompany the write data. Therefore, the padding means 19 generates write data (dummy data) corresponding to the burst length of the DRAM and performs write transfer. The burst control means 18 performs read transfer of the same address immediately after the dummy data write operation is completed, reads the data and ECC written immediately before, and performs consistency check. The operation after the consistency check is not different from the above-described operation.

  As described above, in this embodiment, normal read / write commands and diagnosis commands are discriminated, the management table is also referred to at the time of diagnosis commands, the completion flag is read, and then the initialization status of the target address space of the diagnosis commands By recognizing this, there is an effect that a diagnostic operation can be performed even for an uninitialized address space. This is because the diagnosis operation can be performed simultaneously with the initialization operation for the uninitialized address space, and normal read / write transfer and diagnosis transfer (command) are mixed, and normal data transfer is performed in parallel. Thus, the initialization process can be performed.

  FIG. 8 is a block diagram showing a first embodiment of the disk array device according to the present invention. Hereinafter, description will be given based on this drawing.

The disk array device 70 of this embodiment includes a host adapter 71, a cache memory controller 72, a cache memory 73, a disk adapter 74, a hard disk group 75, and the like, and is connected to a host computer group 80. The cache memory controller 72 is mounted with the above-described cache memory control device 10 as one function.

According to the disk array device 70 , since the cache memory control device 10 is provided, it is not necessary to initialize the data in the address space of the cache memory 73, so that data can be immediately transferred to the cache memory 73 at the time of startup or the like. Become.

The other functions of the disk array device 70 and the cache memory controller 72 other than the cache memory control device 10 are the same as those of the prior art, and thus description thereof is omitted.

1 is a block diagram showing a first embodiment of a cache memory control device according to the present invention. FIG. 4 is a chart showing an example of a management table in the cache memory control device of FIG. 1. FIG. 2 is a block diagram for explaining the operation of the cache memory control device of FIG. 1. 4 is a chart showing a management table used in the operation of the cache memory control device of FIG. 3. It is a flowchart which shows 1st embodiment of the cache memory control method which concerns on this invention. It is a chart which shows the management table in 2nd embodiment of the cache memory control apparatus which concerns on this invention. It is a block diagram which shows 3rd embodiment of the cache memory control apparatus which concerns on this invention. 1 is a block diagram showing a first embodiment of a disk array device according to the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10,60 Cache memory control apparatus 11 Transfer address holding means 12 Transfer length holding means 13 Transfer command holding means 14 Transfer data holding means 15 Table control means 16, 161, 50 Management table 17 Address conversion means 18 Burst control means 19 Padding means 20 Transfer request 21 Transfer address 22 Transfer length 23 Transfer command 24 Write data 30 DRAM access information 31 DRAM address 32 Burst length 33 Transfer command 34 Write data, padding data 51 Entry 52 Burst address space 53 Read violation flag 54 Completion flag 61 Diagnostic command holding Means 70 Disk array device

Claims (6)

In a cache memory control device that controls a cache memory provided in a disk array device,
A management table that divides the address space of the cache memory into a plurality of divided address spaces, and manages a completion flag indicating completion or incomplete of data initialization for each divided address space;
Of the transfer address and transfer data output from the host computer side, table control means for reading the division address space including the transfer address and the completion flag from the management table;
When the completion flag read by the table control means indicates incomplete, the cache address is changed by changing the transfer address and the transfer data so that data is written in the entire divided address space corresponding to the completion flag. An instruction to output to the memory and an instruction to rewrite the completion flag to completion, and when the completion flag read by the table control means indicates completion, the transfer address and the transfer data are used as they are in the cache memory. Burst control means for instructing to output to,
Address conversion means for converting or generating the transfer address according to an instruction output from the burst control means when the completion flag indicates incomplete;
Padding means for adding padding data to the transfer data according to an instruction output from the burst control means when the completion flag indicates incomplete;
A cache memory control device comprising: The divided address space is a burst address space obtained by dividing the address space of the cache memory by a burst length.
The cache memory control device according to claim 1 . The cache memory comprises DRAM;
3. The cache memory control device according to claim 1, wherein the cache memory control device is a cache memory control device.
In a cache memory control method for controlling a cache memory provided in a disk array device,
Dividing the address space of the cache memory into a plurality of divided address spaces, preparing a management table for managing a completion flag indicating completion or incomplete of data initialization for each divided address space,
Among the transfer address and transfer data output from the host computer side, the division address space including the transfer address and the completion flag are read from the management table,
When the read completion flag indicates incomplete, the transfer address and the transfer data are changed and output to the cache memory so that data is written to the entire divided address space corresponding to the completion flag. And instructing the completion flag to be rewritten to completion,
When read the completion flag has been indicated completion, to an instruction to output the transfer address and the transfer data directly to the cache memory,
According to the instruction output when the completion flag indicates incomplete, the transfer address is converted or generated,
A cache memory control method , wherein padding data is added to the transfer data according to the instruction output when the completion flag indicates incomplete .
In a cache memory control program for controlling a cache memory provided in a disk array device,
Dividing the address space of the cache memory into a plurality of divided address spaces, and using a management table for managing a completion flag indicating completion or incomplete of data initialization for each divided address space,
Of the transfer address and transfer data output from the host computer side, table control means for reading out the divided address space including the transfer address and the completion flag from the management table ,
When the completion flag read by the table control means indicates incomplete, the cache address is changed by changing the transfer address and the transfer data so that data is written in the entire divided address space corresponding to the completion flag. An instruction to output to the memory and an instruction to rewrite the completion flag to completion, and when the completion flag read by the table control means indicates completion, the transfer address and the transfer data are used as they are in the cache memory. Burst control means for instructing to output to
Address conversion means for converting or generating the transfer address according to an instruction output from the burst control means when the completion flag indicates incomplete, and
Padding means for adding padding data to the transfer data according to an instruction output from the burst control means when the completion flag indicates incomplete;
A cache memory control program for causing a computer to function as:
The cache memory control device according to any one of claims 1 to 3 ,
A disk array device comprising the disk array device.

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