CN113268263A - Read-back refreshing method and system for FPGA - Google Patents
Read-back refreshing method and system for FPGA Download PDFInfo
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- CN113268263A CN113268263A CN202110659507.8A CN202110659507A CN113268263A CN 113268263 A CN113268263 A CN 113268263A CN 202110659507 A CN202110659507 A CN 202110659507A CN 113268263 A CN113268263 A CN 113268263A
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Abstract
The invention discloses a read-back refreshing method and a read-back refreshing system for an FPGA (field programmable gate array), and relates to the field of fault tolerance of a satellite-borne FPGA. The method comprises the following steps: respectively setting communication states of a preset data transmission interface and the FPGA; sending a read-back instruction to the set FPGA through a preset data transmission interface to acquire a read-back file in the FPGA configuration memory; reading a bit file stored in an external memory, comparing the bit file with a read-back file, judging whether the FPGA has errors according to a comparison result, if so, writing a corresponding correct data packet into a configuration memory of the FPGA, replacing the wrong data packet, and finishing the real-time online configuration and refreshing of the FPGA. The method has the advantages that the real-time work of the FPGA is not influenced, meanwhile, the FPGA configuration state is automatically detected, the configuration error is repaired, the fault tolerance performance of the satellite-borne FPGA system is improved, the influence of the space radiation environment is restrained, and the working stability of the satellite-borne FPGA is improved.
Description
Technical Field
The invention relates to the field of fault tolerance of satellite-borne FPGA, in particular to a read-back refreshing method and a read-back refreshing system of FPGA.
Background
The FPGA has the characteristics of repeated programming, rich logic resources and high integration level; in existing partial satellite-borne systems, FPGAs have been used as system controllers, data processors, and communication interface devices; however, the satellite-borne system works in a space radiation environment, the influence of space radiation particles on the total dose effect, the single particle effect and the like generated by an electronic circuit is one of the causes of circuit faults, and particularly for a circuit system with high integration level, such as an FPGA (field programmable gate array), the faults of single particle upset and the like are easy to occur in the space radiation environment to generate logic errors;
in the FPGA circuit system, a timing reset method can be used for controlling the FPGA to carry out periodic reset and reloading the configuration file so as to repair the logic errors of the FPGA. The method has simple principle and is easy to realize; however, because the FPGA is in an idle state during the reset period of the FPGA, the method is not suitable for application scenarios with high real-time requirements, such as state monitoring, data transmission, and the like.
Disclosure of Invention
The invention aims to solve the technical problem of the prior art and provides a method and a system for refreshing the read-back of an FPGA.
The technical scheme for solving the technical problems is as follows:
a read-back refreshing method of an FPGA comprises the following steps:
s1, setting the communication states of the preset data transmission interface and the FPGA respectively;
s2, sending a read-back instruction to the set FPGA through a preset data transmission interface, and acquiring a read-back file in the FPGA configuration memory;
s3, reading the bit file stored in the external memory, comparing the bit file with the read-back file, if the bit file is different from the read-back file, the FPGA generates an error;
s4, acquiring a first data packet with errors in the read-back file according to the comparison result, and searching a correct second data packet corresponding to the first data packet in the bit file;
and S5, writing the second data packet into a configuration memory of the FPGA through the preset data transmission interface according to a preset refreshing logic, and completing the real-time online configuration refreshing of the FPGA.
The invention has the beneficial effects that: according to the scheme, the read-back file in the FPGA configuration memory is obtained through the preset data transmission interface, the read-back file is compared with the bit file stored in the external memory, whether the FPGA is wrong or not is judged according to the comparison result, if the FPGA is wrong, the corresponding correct data packet is written into the FPGA configuration memory, the wrong data packet is replaced, the FPGA configuration state is automatically detected and the configuration error is repaired while the real-time work of the FPGA is not influenced, the fault tolerance performance of the satellite-borne FPGA system is improved, the influence of the space radiation environment is restrained, and the working stability of the satellite-borne FPGA is improved. The scheme can be applied to scenes with high real-time requirements, such as state monitoring and data transmission.
The aim of automatically detecting and repairing the configuration error of the FPGA is fulfilled. The method solves the problem of configuration errors caused by factors such as total dose effect and single event effect of the FPGA in a space radiation environment, and the FPGA circuit system can automatically detect and repair the configuration errors of the FPGA while working in real time, thereby improving the fault tolerance of the satellite-borne FPGA.
Further, before the S1, the method further includes: and writing the configuration file in the configuration manager into a configuration memory of the FPGA for an external device to read the read-back file.
The beneficial effect of adopting the further scheme is that: according to the scheme, the FPGA writes bit stream data into a configuration memory inside the FPGA from a configuration manager according to control logic, generates an internal circuit structure and realizes a program function.
Further, the S3 is preceded by:
s31, reading the value of the read-back status register of the FPGA through the preset data transmission interface;
s32, judging the value of the readback status register, if the status register is abnormal, resetting the FPGA, reloading the configuration file, and then executing the step S31; if the status register is normal, step S3 is performed.
The beneficial effect of adopting the further scheme is that: according to the scheme, if the abnormal state value is read, the FPGA needs to be reset, the bit stream data is reloaded, and the read-back operation and the generated read-back file are ensured to be normal.
Further, the S3 further includes: if the bit file is the same as the read-back file, no error occurs in the FPGA, and the step S2 is executed in return.
The beneficial effect of adopting the further scheme is that: the scheme realizes real-time online monitoring of whether the FPGA has errors, and prevents the FPGA from being influenced by configuration errors caused by factors such as total dose effect and single event effect in a space radiation environment.
Further, the preset refresh logic sequentially includes: command header data refresh, data partial refresh, and command tail data refresh.
The beneficial effect of adopting the further scheme is that: the scheme can realize online refreshing, and the FPGA chip does not need to be reset and reconfigured globally.
The read-back and refresh operations of the FPGA1 are realized, so that the aim of automatically detecting and repairing configuration errors of the FPGA1 is fulfilled.
Another technical solution of the present invention for solving the above technical problems is as follows:
a read-back refresh system for an FPGA, comprising: the device comprises a state setting module, a read-back module, a comparison module, a searching module and a refreshing module;
the state setting module is used for respectively setting the communication states of the preset data transmission interface and the FPGA;
the read-back module is used for sending a read-back instruction to the set FPGA through the preset data transmission interface to acquire a read-back file in the FPGA configuration memory;
the comparison module is used for reading the bit file stored in the external memory, comparing the bit file with the read-back file, and if the bit file is different from the read-back file, the FPGA generates an error;
the search module is used for acquiring a first data packet with an error in the read-back file according to a comparison result, and searching a correct second data packet corresponding to the first data packet in the bit file;
and the refreshing module is used for writing the second data packet into a configuration memory of the FPGA through the preset data transmission interface according to a preset refreshing logic so as to complete the real-time online configuration refreshing of the FPGA.
The invention has the beneficial effects that: according to the scheme, the read-back file in the FPGA configuration memory is obtained through the preset data transmission interface, the read-back file is compared with the bit file stored in the external memory, whether the FPGA is wrong or not is judged according to the comparison result, if the FPGA is wrong, the corresponding correct data packet is written into the FPGA configuration memory, the wrong data packet is replaced, the FPGA configuration state is automatically detected and the configuration error is repaired while the real-time work of the FPGA is not influenced, the fault tolerance performance of the satellite-borne FPGA system is improved, the influence of the space radiation environment is restrained, and the working stability of the satellite-borne FPGA is improved. The scheme can be applied to scenes with high real-time requirements, such as state monitoring and data transmission.
The aim of automatically detecting and repairing the configuration error of the FPGA is fulfilled. The method solves the problem of configuration errors caused by factors such as total dose effect and single event effect of the FPGA in a space radiation environment, and the FPGA circuit system can automatically detect and repair the configuration errors of the FPGA while working in real time, thereby improving the fault tolerance of the satellite-borne FPGA.
Further, still include: and the loading module is used for writing the configuration file in the configuration manager into a configuration memory of the FPGA for an external device to read the read-back file.
The beneficial effect of adopting the further scheme is that: according to the scheme, the FPGA writes bit stream data into a configuration memory inside the FPGA from a configuration manager according to control logic, generates an internal circuit structure and realizes a program function.
Further, still include: the register judgment module is used for reading the value of a read-back status register of the FPGA through the preset data transmission interface;
judging the value of the read-back status register, if the status register is abnormal, resetting the FPGA, reloading the configuration file, and then continuously reading the value of the read-back status register of the FPGA; and if the state register is normal, comparing the bit file with the read-back file.
The beneficial effect of adopting the further scheme is that: according to the scheme, if the abnormal state value is read, the FPGA needs to be reset, the bit stream data is reloaded, and the read-back operation and the generated read-back file are ensured to be normal.
Further, the comparison module is further configured to return to continuously read the read-back file if the bit file is the same as the read-back file and no error occurs in the FPGA.
The beneficial effect of adopting the further scheme is that: the scheme realizes real-time online monitoring of whether the FPGA generates errors, and prevents the FPGA from being influenced by configuration errors caused by factors such as total dose effect and single event effect in a space radiation environment.
Further, the preset refresh logic sequentially includes: command header data refresh, data partial refresh, and command tail data refresh.
The beneficial effect of adopting the further scheme is that: the scheme can realize online refreshing, and the FPGA chip does not need to be reset and reconfigured globally.
Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
Fig. 1 is a schematic flowchart of a read-back refreshing method for an FPGA according to an embodiment of the present invention;
fig. 2 is a block diagram of a read-back refresh system of an FPGA according to an embodiment of the present invention;
fig. 3 is a schematic block diagram of a fault tolerant circuit according to another embodiment of the present invention.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, which are set forth to illustrate, but are not to be construed to limit the scope of the invention.
As shown in fig. 1, a method for refreshing a read back of an FPGA according to an embodiment of the present invention includes:
s1, setting the communication states of the preset data transmission interface and the FPGA1 respectively; the preset data transmission interface can be a specific SelectMap data transmission interface functional module in the FPGA1, the part does not conflict with other functional modules, and the FPGA1 still works normally in the read-back process. In addition, the SelectMap data transmission interface is a bidirectional interface, and data flow directions can be set by respectively reading and writing the registers of the FPGA1 during read-back and refreshing.
It should be noted that, in a certain embodiment, during the working process of the FPGA1, the external refresher 3 may perform a read-back operation at intervals, and in each read-back cycle, the external refresher 3 may send a control instruction to the FPGA1 through the data transmission interface, set the FPGA1 in a read-back state, and set the data transmission interface in a readable state;
in a certain embodiment, S1 may further include, before: building a fault tolerant circuit, the circuit comprising: an FPGA1, a configuration manager 2, an external refresher 3, an external FLASH memory 4; the configuration manager 2 is used for writing the bit stream data into a configuration memory of the FPGA1 after the system is powered on, generating an FPGA1 circuit structure, and completing configuration of the FPGA 1; the external refresher 3 is used for controlling the read-back and refresh operations of the FPGA 1; the external FLASH memory 4 is used for storing a bit file, and when the FPGA1 has an error, the bit file can be used for refreshing the FPGA 1;
in one embodiment, after the FPGA1 software development is complete, a "curing" operation can be performed in the development environment, e.g., Vivado, to create a. jic file using the compiled software, and download it to the configuration manager 2, i.e., the SPI interface FLASH chip. The jic files stored in the configuration manager 2 may be written to the configuration memory of the FPGA1 after the system is powered on in the form of a plurality of data packets, which are collectively referred to as bitstream data. The FPGA1 may generate internal circuit structures from the bitstream data to implement the functionality of the software design. The bit stream data is a program file which needs to be loaded after the FPGA1 is powered on, and after the loading is completed, the FPGA1 can realize an expected function.
It should be noted that, in one embodiment, the content of the bit file and the content of the bit stream data are the same, and both are the. jic file stored in the FLASH memory. The bit file is a static file stored in FLASH, and the bit stream data is a general name of a plurality of data packets.
In a certain embodiment, a functional block diagram of the fault-tolerant circuit may be as shown in fig. 3, in the fault-tolerant circuit, the configuration manager 2 may be a FLASH chip of an SPI interface, the external FLASH memory 4 is also a FLASH chip, and the two devices may select different specifications of products of multiple brands according to the storage capacity requirement; the FPGA1 provided by the invention is mainly a 7Series FPGA chip produced by Xilinx company, can comprise products with various specifications of three sub-Series of A7, K7 and Z7, and can be selected according to actual requirements without specific limitation. The external refresher 3 mentioned in the invention refers to a JFMRS01RH read-back refresh circuit of a compound microelectronic company, but other manufacturers including corresponding products of foreign manufacturers can also realize corresponding external functions, and the specific limitation of the model is not made. The invention designs and verifies based on a Xilinx K7FPGA + JFMRS01RH hardware platform, focuses more on the principle read-back refreshing method of the fault-tolerant circuit, is not limited to a certain specific hardware platform, and can also be a fault-tolerant circuit of other platforms.
S2, sending a read-back instruction to the set FPGA1 through a preset data transmission interface, and acquiring a read-back file in the memory configured by the FPGA 1;
in one embodiment, the external refresher 3 may periodically read back the FPGA 1; in each read-back cycle, the external refresher 3 sends a control instruction to the FPGA1 through the data transmission interface, sets the FPGA1 to a read-back state, and sets the data transmission interface to a readable state; after the setting is finished, the external refresher 3 sends a read-back instruction, reads the data in the memory configured by the FPGA1 according to the address sequence, generates bit stream data, and generates a read-back file according to the bit stream data; it should be noted that the read back of the FPGA1 by the external refresher 3 is controlled by reading and writing registers. The bit stream data is a data stream when the FPGA1 loads the configuration file into the configuration memory, and the read-back operation is to restore another data stream from the configuration memory to the external refresher 3 to generate a read-back file.
S3, reading the bit file stored in the external memory, comparing the bit file with the read-back file, if the bit file is different from the read-back file, generating an error in the FPGA 1;
in a certain embodiment, the bit file stored in the external FLASH memory 4 is the same as the configuration file solidified in the configuration manager 2, that is, the bit stream data of both are the same, and both are composed of a packet with a format of packet header + packet body. The external refresher 3 finishes the read-back operation, reads the bit file stored in the external FLASH memory 4 after obtaining the read-back file, and compares the bit file with the read-back file; if the bit file is the same as the read-back file, the FPGA1 is proved to have no error, and the operation can be continued; if the bit file is different from the read-back file, the FPGA1 is wrong, and the FPGA1 needs to be configured and refreshed;
it should be noted that, in a certain embodiment, the relationship between the bit file, the configuration file, and the read-back file may be: in content, three files are generated by the development environment, the jic file. The bit file and configuration file are downloaded directly into FLASH the. jic file. Wherein, the bit file is the. jic file stored in the external FLASH memory 4, and the configuration file is the. jic file stored in the configuration manager 2; the read-back file is a file restored from the configuration memory of the FPGA1 by the external refresher 3 reading back the FPGA 1. If no configuration error occurs with the FPGA1, the contents of the readback file should be the same as. jic. This is the principle of comparing the read-back file with the bit file.
S4, acquiring a first data packet with errors in the read-back file according to the comparison result, and searching a correct second data packet corresponding to the first data packet in the bit file;
and S5, writing the second data packet into a configuration memory of the FPGA1 through a preset data transmission interface according to a preset refreshing logic, and completing the real-time online configuration refreshing of the FPGA 1.
It should be noted that, in a certain embodiment, when the read-back file is different from the bit file stored in the external FLASH memory 4, the external refresher 3 will refresh the FPGA 1; the external refresher 3 reads the packet header information of the data packet with errors in the read-back file according to the comparison condition of the bit file and the read-back file, performs reading operation on the external FLASH memory 4 according to the packet header information, searches the corresponding data packet in the bit file and reads the data packet into the data buffer area; after reading the bit file data packet, sending a refresh command to the FPGA1 through a data transmission interface, and writing the data packet into a configuration memory of the FPGA1 according to a preset refresh logic to complete refresh operation;
in a certain embodiment, the buffer may be a buffer of the external refresher 3. The external refresher 3 can locate the position where the read-back file has an error, then find the corresponding content, one or a plurality of data packets in the external FLASH memory 4, store the data packets into a buffer area, then the external refresher 3 needs to pack the data, write the data into the configuration memory of the FPGA1 according to the set time sequence, and finish refreshing;
wherein the preset refresh logic may include: the first part is the command header data, which is automatically generated by the external refresher 3, and includes AA995566 sync words, write CMD register, write WCFG commands, write FDRI register, amount of data written;
the second part is a data part, and data is stored in the buffer area; the third part is the command trailer, which is automatically generated by the external refresher 3.
During the refresh process, the external refresher 3 writes data into the FPGA1 through a SelectMap interface, which is a standard interface and the transmission timing of which is fixed.
According to the scheme, the read-back file in the FPGA1 configuration memory is obtained through the preset data transmission interface, the read-back file is compared with the bit file stored in the external memory, whether an error occurs in the FPGA1 is judged according to the comparison result, if the error occurs, the corresponding correct data packet is written into the configuration memory of the FPGA1, the erroneous data packet is replaced, the configuration state of the FPGA1 is automatically detected and the configuration error is repaired while the real-time work of the FPGA1 is not influenced, the fault tolerance performance of the satellite-borne FPGA1 system is improved, the influence of the space radiation environment is restrained, and the working stability of the satellite-borne FPGA1 is improved. The scheme can be applied to scenes with high real-time requirements, such as state monitoring, data transmission and the like.
The aim of automatically detecting and repairing the configuration error of the FPGA1 is fulfilled. By the method, the problem of configuration errors caused by factors such as total dose effect and single event effect of the FPGA1 in a space radiation environment is solved, the FPGA1 circuit system can automatically detect and repair the configuration errors of the FPGA1 while working in real time, and the fault-tolerant capability of the satellite-borne FPGA1 is improved.
Preferably, in any of the above embodiments, before S1, the method further includes: and writing the configuration file in the configuration manager 2 into the configuration memory of the FPGA1 for the external device to read back the read-back file. Wherein the external device may be an external refresher.
In one embodiment, after the FPGA1 program is compiled by the development environment, a configuration file can be generated and stored in the configuration manager 2 in a solidified manner; after the system is powered on, the FPGA1 loads a configuration file from the configuration manager 2, the configuration file stores bit stream data, the bit stream data is composed of a plurality of data packets with the format of packet header and packet body, wherein the packet header corresponds to an address of an internal configuration memory of the FPGA1, and the packet body corresponds to a specific configuration instruction; according to the control logic, the FPGA1 writes the bit stream data from the configuration manager 2 device into the configuration memory inside the FPGA1, generates an internal circuit structure, realizes a program function, and starts to work after the configuration is completed, in the FPGA 1.
It should be noted that in one embodiment, the configuration file may be the aforementioned. jic file, and the configuration command may be the contents of the FPGA1 software design, because the bitstream data includes a plurality of packets, each of which is included as part of the FPGA1 software content. This process of subcontracting loads is done automatically by the FPGA1 and does not require the involvement of the designer.
It should be noted that in one embodiment, FPGA1 is a programmable logic device, and there are a large number of logic gates inside the device. The FPGA1 software can be analogized to the wires connecting these logic gates. I design FPGA1 program, and connect the resources in FPGA1 to obtain a circuit with specific function. The connection work is completed in a development environment, i only need to design a program, the program can be automatically connected after being compiled, the generated bit stream file can also be understood as a circuit diagram, and the FPGA1 carries out internal connection according to the bit stream file to generate an internal circuit structure. This internal circuit configuration is implemented within the FPGA1 chip, for example, when a serial transceiver is designed using a development environment, it is fixed in the FPGA 1. Therefore, the internal circuit structure of the FPGA1 is a serial port circuit structure, and the function of serial port receiving and sending can be realized.
According to the scheme, the FPGA1 writes bit stream data into a configuration memory in the FPGA1 from the configuration manager 2 according to a control logic, generates an internal circuit structure and realizes a program function.
Preferably, in any of the above embodiments, S3 may be preceded by:
s31, reading the value of the read-back status register of the FPGA1 through a preset data transmission interface;
s32, judging the value of the readback status register, if the status register is abnormal, resetting the FPGA1, reloading the configuration file, and then executing the step S31; if the status register is normal, step S3 is performed.
In one embodiment, the external refresher 3 performing status monitoring on the FPGA1 may include:
the read-back operation of the external refresher 3 does not affect the working state of the FPGA1, the external refresher 3 can read the value of the FPGA1 read-back state register through the data transmission interface in the process of controlling the FPGA1 to read back, and if the value of the read-back state register is correct, the read-back operation and the generated read-back file are normal;
it should be noted that, in a certain embodiment, the working state that does not affect the FPGA1 may be: the on-line refresh can be realized without global reset and reconfiguration of the FPGA1 chip. The specific process is as follows:
the external refresher 3 supports an error positioning function, can identify the error position in the bit stream data, extracts the corresponding data packet from the bit file, and writes the data packet into the FPGA1 through the data transmission interface to configure the memory. In other words, if the program module 1 is incorrectly configured, only the program module 1 needs to be reconfigured, and the other program modules do not need to be reconfigured.
It should be noted that the read-back refresh method has less impact on FPGA1 than the global reset reconfiguration scheme for FPGA1, but still has an impact on real-time functionality, which is unavoidable. For example, the time for resetting and reloading the FPGA1 is 500ms, the real-time functional failure time is 500ms, the refresh time is 50ms, and the real-time functional failure time is only 50ms, so that the influence of the refresh time is negligible, which is equivalent to no influence on the normal operation of the FPGA 1.
It should be noted that the determination of whether to contend for the value of the register may be: the invention is designed and verified based on a Xilinx K7FPGA + JFMRS01RH hardware platform. The data transmission interface under the platform is a SelectMap interface, a read-back refreshing chip firstly writes 0XEC8300 into an FAR register of the FPGA, then reads the value of the FAR register, if the read value is 0XEC8300, read-back can be normally carried out, if the read value is abnormal, the FPGA needs to be reset, and bit stream data is reloaded; in the read-back stage, the value of the STAT status register is read through a SelectMap interface, wherein 1 is normal, 0 is abnormal, if the abnormal status value is read, the reset is needed, and the bit stream data is reloaded.
In a certain embodiment, the method further comprises the following steps: in the read-back stage, the value of the STAT status register is read through the SelectMap interface, and if an abnormal status value is read, the FPGA1 needs to be reset, and the bit stream data needs to be reloaded.
According to the scheme, if the abnormal state value is read, the FPGA1 needs to be reset, the bit stream data is reloaded, and the read-back operation and the generated read-back file are ensured to be normal.
Preferably, in any of the above embodiments, S3 further includes: if the bit file is the same as the read-back file, the FPGA1 has no error, and the process returns to execute the step S2.
By the scheme, whether the FPGA1 is wrong or not is monitored online in real time, and the FPGA1 is prevented from being influenced by configuration errors caused by factors such as total dose effect and single event effect in a space radiation environment.
Preferably, in any of the above embodiments, the preset refresh logic sequentially comprises: command header data refresh, data partial refresh, and command tail data refresh.
The scheme can realize online refreshing, and the FPGA1 chip does not need to be reset and reconfigured globally.
The read-back and refresh operations of the FPGA1 are realized, so that the aim of automatically detecting and repairing configuration errors of the FPGA1 is fulfilled.
In one embodiment, as shown in fig. 2, a read-back refresh system of an FPGA includes: a state setting module 110, a read-back module 120, a comparison module 130, a search module 140 and a refresh module 150;
the state setting module 110 is configured to set communication states of the preset data transmission interface and the FPGA1 respectively;
the read-back module 120 is configured to send a read-back instruction to the set FPGA1 through a preset data transmission interface, and obtain a read-back file in the memory configured by the FPGA 1;
the comparison module 130 is configured to read a bit file stored in the external memory, compare the bit file with the read-back file, and if the bit file is different from the read-back file, the FPGA1 is in error;
the search module 140 is configured to obtain a first data packet with an error in the read-back file according to the comparison result, and search for a correct second data packet corresponding to the first data packet in the bit file;
the refresh module 150 is configured to write the second data packet into the configuration memory of the FPGA1 through the preset data transmission interface according to the preset refresh logic, so as to complete real-time online configuration refresh of the FPGA 1.
According to the scheme, the read-back file in the FPGA1 configuration memory is obtained through the preset data transmission interface, the read-back file is compared with the bit file stored in the external memory, whether an error occurs in the FPGA1 is judged according to the comparison result, if the error occurs, the corresponding correct data packet is written into the configuration memory of the FPGA1, the erroneous data packet is replaced, the configuration state of the FPGA1 is automatically detected and the configuration error is repaired while the real-time work of the FPGA1 is not influenced, the fault tolerance performance of the satellite-borne FPGA1 system is improved, the influence of the space radiation environment is restrained, and the working stability of the satellite-borne FPGA1 is improved. The scheme can be applied to scenes with high real-time requirements, such as state monitoring and data transmission.
The aim of automatically detecting and repairing the configuration error of the FPGA1 is fulfilled. By the method, the problem of configuration errors caused by factors such as total dose effect and single event effect of the FPGA1 in a space radiation environment is solved, the FPGA1 circuit system can automatically detect and repair the configuration errors of the FPGA1 while working in real time, and the fault-tolerant capability of the satellite-borne FPGA1 is improved.
Preferably, in any of the above embodiments, further comprising: and the loading module is used for writing the configuration file in the configuration manager 2 into the configuration memory of the FPGA 1.
According to the scheme, the FPGA1 writes bit stream data into a configuration memory in the FPGA1 from the configuration manager 2 according to a control logic, generates an internal circuit structure and realizes a program function.
Preferably, in any of the above embodiments, further comprising: the register judgment module is used for reading the value of the read-back status register of the FPGA1 through a preset data transmission interface;
judging the value of the read-back status register, if the status register is abnormal, resetting the FPGA1, reloading the configuration file, and then continuously reading the value of the read-back status register of the FPGA 1; and if the status register is normal, comparing the bit file with the read-back file.
According to the scheme, if the abnormal state value is read, the FPGA1 needs to be reset, the bit stream data is reloaded, and the read-back operation and the generated read-back file are ensured to be normal.
Preferably, in any of the above embodiments, the comparison module 130 is further configured to return to continue reading the read-back file if the bit file is the same as the read-back file and no error occurs in the FPGA 1.
The scheme realizes real-time online monitoring on whether the FPGA1 has errors, and prevents the FPGA1 from being influenced by configuration errors caused by factors such as total dose effect and single event effect in a space radiation environment.
Preferably, in any of the above embodiments, the preset refresh logic sequentially comprises: command header data refresh, data partial refresh, and command tail data refresh.
The scheme can realize online refreshing, and the FPGA1 chip does not need to be reset and reconfigured globally.
It is understood that some or all of the alternative embodiments described above may be included in some embodiments.
It should be noted that the above embodiments are product embodiments corresponding to the previous method embodiments, and for the description of each optional implementation in the product embodiments, reference may be made to corresponding descriptions in the above method embodiments, and details are not described here again.
The reader should understand that in the description of this specification, reference to the description of the terms "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed.
Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment of the present invention.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention essentially or partially contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-only memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
While the invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A read-back refreshing method of an FPGA is characterized by comprising the following steps:
s1, setting the communication states of the preset data transmission interface and the FPGA respectively;
s2, sending a read-back instruction to the set FPGA through the preset data transmission interface, and acquiring a read-back file in the FPGA configuration memory;
s3, reading a bit file stored in an external memory, comparing the bit file with the read-back file, and if the bit file is different from the read-back file, generating an error in the FPGA;
s4, acquiring a first data packet with errors in the read-back file according to the comparison result, and searching a correct second data packet corresponding to the first data packet in the bit file;
and S5, writing the second data packet into a configuration memory of the FPGA through the preset data transmission interface according to a preset refreshing logic, and completing the real-time online configuration refreshing of the FPGA.
2. The method of claim 1, further comprising, before the step S1: and writing the configuration file in the configuration manager into a configuration memory of the FPGA for an external device to read the read-back file.
3. The method according to claim 2, wherein the S3 is preceded by:
s31, reading the value of the read-back status register of the FPGA through the preset data transmission interface;
s32, judging the value of the readback status register, if the status register is abnormal, resetting the FPGA, reloading the configuration file, and then executing the step S31; if the status register is normal, step S3 is performed.
4. The method according to claim 1, wherein the S3 further comprises: if the bit file is the same as the read-back file, the FPGA does not generate an error, and the step of S2 is executed in a returning way.
5. The method according to any one of claims 1 to 4, wherein the preset refresh logic sequentially comprises: command header data refresh, data partial refresh, and command tail data refresh.
6. A read-back refresh system for an FPGA, comprising: the device comprises a state setting module, a read-back module, a comparison module, a searching module and a refreshing module;
the state setting module is used for respectively setting the communication states of the preset data transmission interface and the FPGA;
the read-back module is used for sending a read-back instruction to the set FPGA through the preset data transmission interface to acquire a read-back file in the FPGA configuration memory;
the comparison module is used for reading a bit file stored in an external memory, comparing the bit file with the read-back file, and if the bit file is different from the read-back file, the FPGA generates an error;
the search module is used for acquiring a first data packet with an error in the read-back file according to a comparison result, and searching a correct second data packet corresponding to the first data packet in the bit file;
and the refreshing module is used for writing the second data packet into a configuration memory of the FPGA through the preset data transmission interface according to a preset refreshing logic so as to complete the real-time online configuration refreshing of the FPGA.
7. The read-back refresh system of an FPGA of claim 6, further comprising: and the loading module is used for writing the configuration file in the configuration manager into a configuration memory of the FPGA for an external device to read the read-back file.
8. The read-back refresh system of an FPGA of claim 7, further comprising: the register judgment module is used for reading the value of a read-back status register of the FPGA through the preset data transmission interface;
judging the value of the read-back status register, if the status register is abnormal, resetting the FPGA, reloading the configuration file, and then continuously reading the value of the read-back status register of the FPGA; and if the status register is normal, comparing the bit file with the read-back file.
9. The system according to claim 6, wherein the comparison module is further configured to return to continue reading the read-back file if the bit file is the same as the read-back file and no error occurs in the FPGA.
10. The read-back refresh system of an FPGA of any one of claims 6-9, wherein said preset refresh logic comprises, in order: command header data refresh, data partial refresh, and command tail data refresh.
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