CN109213632B - Spaceborne electronic system with anti-radiation reinforcement design and reinforcement method - Google Patents

Spaceborne electronic system with anti-radiation reinforcement design and reinforcement method Download PDF

Info

Publication number
CN109213632B
CN109213632B CN201810965871.5A CN201810965871A CN109213632B CN 109213632 B CN109213632 B CN 109213632B CN 201810965871 A CN201810965871 A CN 201810965871A CN 109213632 B CN109213632 B CN 109213632B
Authority
CN
China
Prior art keywords
omap
gate array
programmable logic
logic gate
monitoring module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810965871.5A
Other languages
Chinese (zh)
Other versions
CN109213632A (en
Inventor
杨艳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Space Tube Technology Ltd Of Hunan China
Original Assignee
Space Tube Technology Ltd Of Hunan China
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Space Tube Technology Ltd Of Hunan China filed Critical Space Tube Technology Ltd Of Hunan China
Priority to CN201810965871.5A priority Critical patent/CN109213632B/en
Publication of CN109213632A publication Critical patent/CN109213632A/en
Application granted granted Critical
Publication of CN109213632B publication Critical patent/CN109213632B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14Error detection or correction of the data by redundancy in operation
    • G06F11/1479Generic software techniques for error detection or fault masking

Abstract

The invention provides a spaceborne electronic system with an anti-radiation reinforcement design. The satellite-borne electronic system comprises a system monitoring module, a nonvolatile memory, a programmable logic gate array and an OMAP (open unified application protocol), wherein the system monitoring module is responsible for monitoring whether the programmable logic gate array and the OMAP generate single event upset or not, the programmable logic gate array is responsible for monitoring the state of the OMAP and guiding power-on reset of the OMAP, and the nonvolatile memory is responsible for redundantly storing programs and data of the programmable logic gate array and the OMAP. The satellite-borne electronic system can be timely recovered after a fault occurs, the configuration bit stream of the programmable logic gate array and the program and data of the OMAP can be updated, the program and data of a chip in the system are stored in a nonvolatile memory, and the program and data have high reliability. Through power-on reset and system monitoring, the single event effect of the electronic system can be repaired, and the radiation resistance and reliability of the whole satellite-borne electronic system are improved.

Description

Spaceborne electronic system with anti-radiation reinforcement design and reinforcement method
Technical Field
The invention provides a satellite-borne electronic system with an anti-radiation reinforcement design, belongs to the field of satellite reliability, and can be used for the anti-radiation reinforcement design of the satellite-borne electronic system.
Background
The single event effect mainly includes SEU (single event upset), SET (single event transient), SEL (single event locked latch), and the like, wherein the SEU is the most prominent expression form. For the SRAM type programmable logic gate array, due to the SRAM process adopted by the SRAM type programmable logic gate array, the single event effect, particularly the single event upset, is easy to occur. From the aspect of the single event upset ratio, the configuration memory occupies the largest proportion, and then is an LUT-type RAM, a block-type RAM and a trigger, the proportion of other single event effects such as SET and SEFI is smaller, and SEU of the configuration memory is the most main expression form of the single event effect fault of the programmable logic gate array.
The satellite-borne electronic system is responsible for satellite operation management, signal transceiving, demodulation and de-spreading, operation packaging, acquisition tracking and the like, and is the most core component on the satellite. The system is mainly built by chips such as an FPGA (Field Programmable gate array), a DSP (digital signal processor), an ADC (analog to digital converter), a DAC (digital to analog converter) and the like as main components. However, these large scale integrated circuit devices, especially SRAM (Static RAM) type FPGAs and DSPs, are very susceptible to the effect of space SEE (single event effect).
An FPGA + DSP architecture satellite-borne electronic system has been applied to satellites for many years and is a very classic architecture, but with the emergence of new application requirements of the Internet of things, short data distribution and the like, a new architecture is needed to better capture, track and process a large number of user-side signals, so that a new FPGA + OMAP system architecture is proposed. The ARM core has strong transaction management capability and is responsible for tracking and demodulating received signals, task scheduling, ARM system management and state monitoring. The DSP core realizes rapid capture algorithm, DSP system management and state monitoring, and the dual cores realize communication through the integrated shared memory in the chip without additional external circuits, thereby simplifying the design of peripheral circuits of the chip. The operation of the OMAP requires a program in the program area and also requires data in the data area. Booting of OMAP requires rebooting OMAP programs and data. The ARM of the OMAP is responsible for system management and task scheduling, the DSP is used for signal processing, the programmable logic gate array is responsible for system monitoring, partial digital signal processing and communication functions, and the whole system is low in power consumption, low in cost and high in integration level. However, the system still operates in the outer space with a severe radiation environment, and the satellite-borne electronic system has single-particle sensitive devices such as an FPGA, a DSP, an ARM and the like, so that a new method is needed for reinforcing the system against radiation for improving the reliability of the system. The patent name is 'satellite-borne processing platform with single event effect resistance', and the patent application numbers are as follows: the invention patent of CN200910043422.6 discloses a satellite-borne processing platform with single event effect resistance, which comprises a high-reliability monitoring unit, a nonvolatile memory, a field programmable logic gate array and more than one DSP, wherein the high-reliability monitoring unit is interconnected with other parts by adopting a local bus, and the field programmable logic gate array is interconnected with the DSP by adopting a high-speed bus; the high-reliability monitoring unit is used for detecting and repairing single event upset in the field programmable logic gate array and the DSP. Although the invention provides the satellite-borne processing platform which is simple in structure principle and convenient to operate, the platform has the problems of poor stability and the like. Due to the fact that multiple functions and multiple working modes are involved, the satellite-borne electronic system needs to receive data from the user terminal at any time, and the reliability of the satellite-borne electronic system is related to success or failure of the whole satellite. How to monitor the state of the core device of the satellite-borne electronic system and timely process the faults is an essential function of the satellite-borne electronic system.
Disclosure of Invention
The invention provides a space-borne electronic system with an anti-radiation reinforcement design. The invention aims at the latest FPGA + OMAP satellite-borne electronic system architecture to carry out radiation resistance reinforcement. The system has the capability of resisting the single event effect, and the system can repair the single event effect without influencing the normal work of the satellite-borne electronic system.
The invention provides a satellite-borne electronic system based on anti-radiation reinforcement design, which is characterized in that: the method comprises the following steps: the system comprises a system monitoring module, a nonvolatile memory, a field programmable logic gate array and more than one OMAP; wherein:
the system monitoring module is respectively connected with the nonvolatile memory, the state monitoring module of the field programmable gate array, the OMAP loading module and the OMAP; the method is used for configuration management of the field programmable gate array and the OMAP, and realizes state monitoring, configuration bit stream refreshing and OMAP resetting of the field programmable gate array and the OMAP;
the nonvolatile memory is used for storing original configuration data of the field programmable logic gate array and OMAP programs and data;
the field programmable gate array comprises an OMAP loading module and a state monitoring module, wherein the OMAP loading module is connected with the system monitoring module and the OMAP, and the OMAP loading module is used for reading an OMAP program and data of the nonvolatile memory through the system monitoring module to perform guide loading on the OMAP and monitoring the reconfiguration state of the programmable gate array; the state monitoring module is connected with the OMAP and the system monitoring module, and is responsible for monitoring the running state of the programmable logic gate array and the running state of the OMAP and then sending the running state into the system monitoring module.
The non-volatile memory is capable of making triple modular redundancy for the original configuration bit stream of the programmable logic gate array and the OMAP program and data.
Further, the nonvolatile memory is a Flash memory.
Further, the FPGA can conduct boot loading on the program area and the data area of the OMAP through an HPI or EMIF interface.
The invention also provides a radiation-resistant adding method of the satellite-borne electronic system, which is characterized by comprising the following steps of:
step 1, a system monitoring module starts to configure a programmable logic gate array;
step 2, the system monitoring module reads the original configuration bit stream of the programmable logic gate array stored in the nonvolatile memory, and writes the original configuration bit stream into the programmable logic gate array through a parallel bus or a contact action test group interface after the trimodal redundancy of the original configuration bit stream is judged;
step 3, after the configuration bit stream is completely written into the programmable logic gate array, the OMAP guide module sends a signal to a system monitoring module to confirm that the configuration of the programmable logic gate array is completed, and the step 4 is entered; if the OMAP guiding module does not send the signal, continuing the step 2;
step 4, the system monitoring module starts to reset the OMAP of the satellite-borne electronic system;
and 5, after all OMAP reset is completed, the satellite-borne electronic system restarts normal work.
Further, in step 4, the specific steps of resetting one or more OMAPs are as follows:
step 4.1, the system monitoring module reads the program and data of the first OMAP stored in the nonvolatile memory and places the program and data in a data bus of the programmable logic gate array;
step 4.2, the programmable logic gate array reads the DSP program and data of the first OMAP and writes the DSP program and data into the DSP of the first OMAP through the HPI or EMIF bus;
4.3, after the system monitoring module receives the DSP program of the first OMAP and a signal of finishing data writing, starting to control the programmable logic gate array to read ARM configuration data of the first OMAP and write the ARM configuration data into the ARM of the first OMAP through the HPI bus; otherwise, repeating the step 4.3;
step 4.4, after the system monitoring module receives a signal that writing of ARM configuration data of the first OMAP is completed, if the number of the OMAPs is 1, resetting of the OMAPs is completed, and if the number of the OMAPs is more than 1, the step 4.5 is carried out;
and 4.5, repeating the steps 4.1-4.5 until all OMAPs are completely reset.
Further, the signals monitored by the state monitoring module of the array of programmable logic gates are watchdog signals of the ARM and DSP of the OMAP and the state of the array of programmable logic gates.
The invention has the beneficial effects that:
(1) when the system is powered on, the system monitoring module guides the whole system to operate;
(2) the satellite-borne electronic system is timely discovered and recovered after a fault occurs;
(3) the program and data of the configuration bit stream and the OMAP of the programmable logic gate array can be updated;
(4) the programs and data of the chip (programmable logic gate array, OMAP) of the satellite-borne electronic system are stored in the nonvolatile memory, and the programs and the data have high reliability;
(5) the radiation resistance and the operation reliability of the whole satellite-borne electronic system are improved.
Drawings
FIG. 1 is a structure and signal flow direction of a satellite-borne electronic system with a radiation-resistant and reinforced design;
FIG. 2 is a flow of reboot configuration of a spaceborne electronic system of radiation hardening resistant design;
fig. 3 is a flow diagram of resetting one or more OMAPs.
Detailed Description
The invention will be described in further detail below with reference to the accompanying figures 1-2 and specific examples.
As shown in fig. 1, this embodiment provides a satellite-borne electronic system based on a radiation-hardening resistant design, where the satellite-borne electronic system after the radiation-hardening resistant design includes: the system comprises a system monitoring module, a nonvolatile memory, a field programmable logic gate array and more than one OMAP; wherein:
the system monitoring module is respectively connected with the nonvolatile memory, the state monitoring module of the field programmable gate array, the OMAP loading module and the OMAP; the method is used for configuration management of the field programmable gate array and the OMAP, and realizes state monitoring, configuration bit stream refreshing and OMAP resetting of the field programmable gate array and the OMAP;
the nonvolatile memory is used for storing original configuration data of the field programmable logic gate array and OMAP programs and data;
the field programmable gate array comprises an OMAP loading module and a state monitoring module, wherein the OMAP loading module is connected with the system monitoring module and the OMAP, and the OMAP loading module is used for reading an OMAP program and data of the nonvolatile memory through the system monitoring module to perform guide loading on the OMAP and monitoring the reconfiguration state of the programmable gate array; the state monitoring module is connected with the OMAP and the system monitoring module, and the state monitoring module is responsible for monitoring the running state of the programmable logic gate array and the running state of the OMAP and then sending the running state into the system monitoring module.
The non-volatile memory is capable of making triple modular redundancy for the original configuration bit stream of the programmable logic gate array and the OMAP program and data.
The non-volatile memory is preferably a Flash memory.
The field programmable gate array can conduct guide loading on a program area and a data area of the OMAP through an HPI (host interface) or EMIF (external memory interface external memory extension interface) interface.
When the satellite-borne electronic system works, the working states of the DSP and ARM of the programmable logic gate array and the OMAP are continuously monitored, if the DSP and ARM of the programmable logic gate array and the OMAP are found to be abnormal, the system is subjected to reboot configuration, and the reboot configuration is a radiation-resistant reinforcing process.
The embodiment also provides a radiation-resistant adding method of the satellite-borne electronic system, which specifically comprises the following steps:
step 1, a system monitoring module starts to configure a programmable logic gate array;
step 2, the system monitoring module reads the original configuration bit stream of the programmable logic gate array stored in the nonvolatile memory, and writes the original configuration bit stream into the programmable logic gate array through a SelectMap (parallel bus)/JTAG (contact action test group) interface after the triple modular redundancy of the original configuration bit stream is judged;
step 3, after the configuration bit stream is completely written into the programmable logic gate array, the OMAP guide module sends a signal to a system monitoring module to confirm that the configuration of the programmable logic gate array is completed, and the step 4 is entered; if the OMAP guiding module does not send the signal, continuing the step 2;
step 4, the system monitoring module starts to reset the OMAP of the satellite-borne electronic system;
as shown in fig. 3, the specific steps of resetting one or more OMAPs in step 4 are as follows:
step 4.1, the system monitoring module reads the program and data of the first OMAP stored in the nonvolatile memory and places the program and data in a data bus of the programmable logic gate array;
step 4.2, the programmable logic gate array reads the DSP program and data of the first OMAP and writes the DSP program and data into the DSP of the first OMAP through the HPI or EMIF bus;
4.3, after the system monitoring module receives the DSP program of the first OMAP and a signal of finishing data writing, starting to control the programmable logic gate array to read ARM configuration data of the first OMAP and write the ARM configuration data into the ARM of the first OMAP through the HPI bus; otherwise, repeating the step 4.3;
and 4.4, after the system monitoring module receives a signal that the writing of the ARM configuration data of the first OMAP is finished, if the number of the OMAPs is 1, the resetting of the OMAP is finished. If the number of OMAPs is greater than 1, go to step 4.5;
and 4.5, repeating the steps 4.1-4.5 until all OMAPs are completely reset.
And 5, after all OMAP reset is completed, the satellite-borne electronic system restarts normal work.
After the system is powered on, the system is also subjected to initial boot configuration, namely, the steps 1 to 5 are executed.
In this embodiment, the signals monitored by the status monitoring module of the array of programmable logic gates are watchdog signals of the ARM and DSP of the OMAP and the status of the array of programmable logic gates.
The state monitoring module monitors the programmable logic gate array, once the programmable logic gate array finds the abnormality, the programmable logic gate array stops sending the watchdog signal, and then the system monitoring module considers that the system is abnormal, namely the system is rebooted and configured.
And the ARM and the DSP of the OMAP periodically perform itinerant detection on the execution conditions of the ARM and the DSP programs, if the execution conditions are abnormal, the watchdog feeding pulse is stopped, an SEU state signal is sent to the system monitoring module, and then the system monitoring module considers that the system is abnormal, namely the system is rebooted and configured.
The method for monitoring and recovering the running state of the OMAP comprises the steps of accumulating and verifying program areas in the ARM program and the DSP program at regular intervals without a communication process of the OMAP, comparing and calculating a calculated result with a known result, stopping ARM and DSP watchdog signals if the calculated result is incorrect, interrupting the watchdog signals sent to the system monitoring module if the watchdog signals are not received by the state monitoring module of the programmable logic gate array, and then, the system monitoring module considers that the system is abnormal, namely, the system is redirected and configured.
The system monitoring module has a reset signal to the OMAP, and after receiving the reset signal, the OMAP reloads programs and data of the ARM and the DSP in the OMAP through the OMAP loading module to reset the OMAP.
Although the present invention has been described in terms of the preferred embodiment, it is not intended that the invention be limited to the embodiment. Any equivalent changes or modifications made without departing from the spirit and scope of the present invention also belong to the protection scope of the present invention. The scope of the invention should therefore be determined with reference to the appended claims.

Claims (3)

1. The utility model provides a satellite-borne electronic system based on anti-radiation reinforcement design which characterized in that: the method comprises the following steps: the system comprises a system monitoring module, a nonvolatile memory, a field programmable logic gate array and more than one OMAP; wherein:
the system monitoring module is respectively connected with the nonvolatile memory, the state monitoring module of the field programmable gate array, the OMAP loading module and the OMAP; the method is used for configuration management of the field programmable gate array and the OMAP, and realizes state monitoring, configuration bit stream refreshing and OMAP resetting of the field programmable gate array and the OMAP;
the nonvolatile memory is used for storing original configuration data of the field programmable logic gate array and OMAP programs and data;
the field programmable gate array comprises an OMAP loading module and a state monitoring module, wherein the OMAP loading module is connected with the system monitoring module and the OMAP, and the OMAP loading module is used for reading an OMAP program and data of the nonvolatile memory through the system monitoring module to perform guide loading on the OMAP and monitoring the reconfiguration state of the programmable gate array; the state monitoring module is connected with the OMAP and the system monitoring module, and is responsible for monitoring the running state of the programmable logic gate array and the running state of the OMAP and then sending the running state into the system monitoring module;
the nonvolatile memory can carry out triple modular redundancy on the original configuration bit stream of the programmable logic gate array, the OMAP program and the data;
the nonvolatile memory is a Flash memory;
the field programmable gate array can conduct boot loading on a program area and a data area of the OMAP through an HPI or EMIF interface.
2. A radiation-resistant adding method for a satellite-borne electronic system is characterized by comprising the following steps:
step 1, a system monitoring module starts to configure a programmable logic gate array;
step 2, the system monitoring module reads the original configuration bit stream of the programmable logic gate array stored in the nonvolatile memory, and writes the original configuration bit stream into the programmable logic gate array through a parallel bus or a contact action test group interface after the trimodal redundancy of the original configuration bit stream is judged;
step 3, after the configuration bit stream is completely written into the programmable logic gate array, the OMAP guide module sends a signal to a system monitoring module to confirm that the configuration of the programmable logic gate array is completed, and the step 4 is entered; if the OMAP guiding module does not send the signal, continuing the step 2;
step 4, the system monitoring module starts to reset the OMAP of the satellite-borne electronic system;
step 4.1, the system monitoring module reads the program and data of the first OMAP stored in the nonvolatile memory and places the program and data in a data bus of the programmable logic gate array;
step 4.2, the programmable logic gate array reads the DSP program and data of the first OMAP and writes the DSP program and data into the DSP of the first OMAP through the HPI or EMIF bus;
4.3, after the system monitoring module receives the DSP program of the first OMAP and a signal of finishing data writing, starting to control the programmable logic gate array to read ARM configuration data of the first OMAP and write the ARM configuration data into the ARM of the first OMAP through the HPI bus; otherwise, repeating the step 4.3;
step 4.4, after the system monitoring module receives a signal that writing of ARM configuration data of the first OMAP is completed, if the number of the OMAPs is 1, resetting of the OMAPs is completed, and if the number of the OMAPs is more than 1, the step 4.5 is carried out;
step 4.5, repeating the step 4.1 to the step 4.5 until all OMAPs are completely reset;
and 5, after all OMAP reset is completed, the satellite-borne electronic system restarts normal work.
3. The method for adding radiation resistance to the satellite-borne electronic system according to claim 2, characterized in that: the signals monitored by the state monitoring module of the programmable logic gate array are watchdog signals of an ARM and a DSP of the OMAP and the state of the programmable logic gate array.
CN201810965871.5A 2018-08-23 2018-08-23 Spaceborne electronic system with anti-radiation reinforcement design and reinforcement method Active CN109213632B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810965871.5A CN109213632B (en) 2018-08-23 2018-08-23 Spaceborne electronic system with anti-radiation reinforcement design and reinforcement method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810965871.5A CN109213632B (en) 2018-08-23 2018-08-23 Spaceborne electronic system with anti-radiation reinforcement design and reinforcement method

Publications (2)

Publication Number Publication Date
CN109213632A CN109213632A (en) 2019-01-15
CN109213632B true CN109213632B (en) 2022-06-17

Family

ID=64989055

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810965871.5A Active CN109213632B (en) 2018-08-23 2018-08-23 Spaceborne electronic system with anti-radiation reinforcement design and reinforcement method

Country Status (1)

Country Link
CN (1) CN109213632B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110427338A (en) * 2019-07-05 2019-11-08 中国科学院电子学研究所 Spaceborne field programmable gate array and its reliability reinforcement means

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101551763A (en) * 2009-05-15 2009-10-07 中国人民解放军国防科学技术大学 Method and device for repairing single event upset in field programmable logic gate array
CN101551762A (en) * 2009-05-15 2009-10-07 中国人民解放军国防科学技术大学 Spaceborne processing platform resisting single event effect
CN101561477A (en) * 2009-05-15 2009-10-21 中国人民解放军国防科学技术大学 Method and device for testing single event upset in in-field programmable logic gate array
CN103971732A (en) * 2014-04-30 2014-08-06 浙江大学 Method and system for monitoring single event upset effect of FPGA (field programmable gate array) and correcting reloading
US20160274816A1 (en) * 2015-03-17 2016-09-22 Gowin Semiconductor Corporation, Ltd. Programmable Logic Device With On-Chip User Non-Volatile Memory
CN106557346A (en) * 2016-11-24 2017-04-05 中国科学院国家空间科学中心 A kind of primary particle inversion resistant star-carried data processing system and method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101551763A (en) * 2009-05-15 2009-10-07 中国人民解放军国防科学技术大学 Method and device for repairing single event upset in field programmable logic gate array
CN101551762A (en) * 2009-05-15 2009-10-07 中国人民解放军国防科学技术大学 Spaceborne processing platform resisting single event effect
CN101561477A (en) * 2009-05-15 2009-10-21 中国人民解放军国防科学技术大学 Method and device for testing single event upset in in-field programmable logic gate array
CN103971732A (en) * 2014-04-30 2014-08-06 浙江大学 Method and system for monitoring single event upset effect of FPGA (field programmable gate array) and correcting reloading
US20160274816A1 (en) * 2015-03-17 2016-09-22 Gowin Semiconductor Corporation, Ltd. Programmable Logic Device With On-Chip User Non-Volatile Memory
CN106557346A (en) * 2016-11-24 2017-04-05 中国科学院国家空间科学中心 A kind of primary particle inversion resistant star-carried data processing system and method

Also Published As

Publication number Publication date
CN109213632A (en) 2019-01-15

Similar Documents

Publication Publication Date Title
Gaisler A portable and fault-tolerant microprocessor based on the SPARC v8 architecture
CN102779079B (en) Configuration method and system used for satellite-bone SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) working on track for long time
US10761925B2 (en) Multi-channel network-on-a-chip
US20180111626A1 (en) Method and device for handling safety critical errors
CN103971732A (en) Method and system for monitoring single event upset effect of FPGA (field programmable gate array) and correcting reloading
CN106716843B (en) Programmable IC with secure subsystem
Carmichael et al. Correcting single-event upsets in Virtex-4 FPGA configuration memory
CN104932954A (en) FPGA (Field Programmable Gate Array) key data protection method for microsatellite
CN110413456B (en) Triple redundant data step-by-step voting system and method
Sturesson et al. Radiation characterization of a dual core LEON3-FT processor
CN111176908A (en) Program on-orbit loading and refreshing method based on triple modular redundancy
WO2015111176A1 (en) Programmable device, error-storage system, and electronic system device
Anderson et al. Neutron radiation beam results for the Xilinx UltraScale+ MPSoC
US11586496B2 (en) Electronic circuit with integrated SEU monitor
WO2015119950A1 (en) Diagnostic systems and methods of finite state machines
CN109213632B (en) Spaceborne electronic system with anti-radiation reinforcement design and reinforcement method
US9495239B1 (en) User-configurable error handling
Fuchs et al. A fault-tolerant MPSoC for CubeSats
CN103389921A (en) Signal processing circuit and testing device employing the signal processing circuit
US8230286B1 (en) Processor reliability improvement using automatic hardware disablement
Carmichael et al. Correcting single-event upsets in virtex-4 platform FPGA configuration memory
Cherezova et al. Understanding fault-tolerance vulnerabilities in advanced SoC FPGAs for critical applications
CN111785310A (en) FPGA (field programmable Gate array) reinforcement system and method for resisting single event upset
Beningo A review of watchdog architectures and their application to Cubesats
Acle et al. Implementing a safe embedded computing system in SRAM-based FPGAs using IP cores: A case study based on the Altera NIOS-II soft processor

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant