CN105354048A - System-level reinforcement method for ASIC spatial application - Google Patents
System-level reinforcement method for ASIC spatial application Download PDFInfo
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- CN105354048A CN105354048A CN201510622226.XA CN201510622226A CN105354048A CN 105354048 A CN105354048 A CN 105354048A CN 201510622226 A CN201510622226 A CN 201510622226A CN 105354048 A CN105354048 A CN 105354048A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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Abstract
The invention discloses a system-level reinforcement method for an ASIC spatial application. The method comprises the steps of: S1: establishing a parameter configuration list; S2: performing reinforcement setting on the parameter configuration list, and performing reliability reinforcement on defined to-be-configured parameters; S3: setting a real-time checking and periodic refreshing mechanism; S4: setting a chip system-level dynamic refreshing mechanism, and performing register cache mode setting on parameters required to be configured; S5: setting a chip parameter re-configuration protection mechanism to ensure the correctness of a re-configuration process; S6: storing reinforced chip configuration parameters; S7: reading external configuration parameters to finish initial configuration; S8: after the initial configuration is finished, starting to perform real-time checking on configuration parameters working in a chip; S9: re-configuring the time according to the set parameters; and S10: performing dynamic refreshing. The method has the advantages of easiness for realization, high reliability, wide application range and the like.
Description
Technical field
The present invention is mainly concerned with Department of Electronics's irrespective of size reliability reinforcement technique field, refers in particular to a kind of system-level reinforcement means for the application of ASIC space
Background technology
Integrated circuit (IC) chip in electronic system runs in space radiation environment, by the impact of Energetic particle irradiation, very easily produces single particle effect.Single particle effect will cause integrated circuit itself to damage or function operation exception, thus cause whole electronic system dysfunction, will make electronic system function complete failure under serious conditions.What use in space electronic system along with large scale integrated circuit gets more and more, and single particle effect can make integrated circuit occurrence logic state turnover, the instantaneous abnormal or interruption of logic function, and along with the decline of CMOS (ComplementaryMetalOxideSemiconductors) technique, the threshold voltage of PN junction reduces, as scale programmable logic device (hereinafter referred to as FPGAFieldProgrammableGateArray), processors etc. face single particle effect and threaten increasingly severe, and chip stops the impact of single particle effect on chip functions completely also not have a kind of chip production mode to ensure at present.
FPGA is strong because have processing power, and the advantages such as function is able to programme are widely used in space electronic system, and the feature due to FPGA self causes it to be subject to single particle effect causing dysfunction.Large-scale application-specific integrated circuit (ApplicationSpecificIntegratedCircuit is hereinafter referred to as ASIC) possesses stronger anti-single particle overturn and the ability of accumulated dose, is widely used in the space exploration tasks such as reliability requirement height and longevity of service.
In order to improve the anti-single particle effect capability of asic chip, most of practitioner is many carries out Design of Reinforcement from chip makes physical design level, and this way does not have good solution to the single event function interrupt that single particle effect causes.Usually reduce single event function interrupt etc. by the design of redundancy, but this measure is by sacrificing the area of asic chip and power consumption is the function-stable that cost exchanges for.Show on different space orbits according to current research, the impact of single particle effect is different, if do single reinforcement measure, possibly cannot make special chip work optimization, waste unnecessary power consumption and chip area.
As from the foregoing, the ASIC device of existing space-oriented application is mainly from the measure that chip design stage uses redundancy or physical Design to reinforce, such design increases power consumption or area is cost, strengthen the reliability of ASIC device space application, this method cannot solve ASIC device and be subject to the system single event function interrupt that Space Radiation Effects causes.Therefore, how improve the anti-single particle function interrupt capabilities of asic chip from system level, and then the ability improving asic chip and even entire system anti-single particle effect is that application needs problem demanding prompt solution to asic chip in space.
Summary of the invention
The technical problem to be solved in the present invention is just: the technical matters existed for prior art, the invention provides a kind of easy realization, good reliability, the system-level reinforcement means for the application of ASIC space applied widely.
For solving the problems of the technologies described above, the present invention by the following technical solutions:
For a system-level reinforcement means for ASIC space application, the steps include:
S1: set up configuration parameter list, according to function definition and the demand of chip, defines the parameter needing configuration;
S2: the reinforcing of parameter configuration list is arranged, does reliability to the parameter to be configured of definition and reinforces;
S3: verification in real time and periodic refreshing mechanism are set;
S4: arrange and system-level dynamic refresh mechanism is carried out to chip, do register cache mode to needing the parameter of configuration to arrange, the i.e. input signal of each configuration parameter using the form of static register as each functional module, these input signals in chip course of normal operation without the need to change;
S5: arrange chip parameter and reshuffle protection mechanism, guarantees the correctness of reconfiguration course;
S6: store the chip configuration parameter after reinforcing;
S7: read exterior arrangement parameter, complete initial configuration;
S8: after completing initial configuration, start to verify in real time work configuration parameter in the chips, if check results is wrong, carry out a dynamic refresh to configuration parameter, during parameter refreshes, chip normally works;
S9: the parameter reconfiguration according to arranging puts the time, if reach setup time, then carries out a dynamic refresh to all configuration parameters;
S10: dynamic refresh, consistent with initial parameter configuration effort flow process, in dynamic refresh process, chip begins normally to work, by the impact that dynamic state of parameters refreshes.
As a further improvement on the present invention: the idiographic flow carrying out real-time verifying work is:
S101: the initial configuration completing chip;
S102: according to the order of parameter configuration, the configuration parameter be configured in each functional module of sampling successively, calculates the CRC32 check results of the configuration parameter that current chip runs;
S103: again read the configuration parameter being stored in chip exterior, this reads the CRC32 check results prestored in configuration parameter;
S104: the chip internal configuration parameter CRC32 check results that contrast conting obtains with deposit the CRC32 check results comprised in the space of parameter;
S105: if result is consistent, then repeated execution of steps S102, S103, S104 again; If result is inconsistent, then chip need reconfigure, and enters chip Reconfiguration Procedure.
As a further improvement on the present invention: the detailed process carrying out parameter configuration is as follows:
S201: before chip is started working, after reading the configuration data of exterior storage, carry out the data decimation operation of one-out-three, if in three data, any two data read are identical, then select this identical data as the data used; Otherwise, then assert that this time is read data and occurred mistake, restart to read data;
S202: be stored in parameter configuration management module as register to the configuration parameter after choosing;
S203: after having read all configuration parameters, carries out clock zone process to all parameters, under namely enabling configuration parameter be operated in the clock zone of actual use in functional module to parameter by the mode of sampling;
S204: after completing the clock zone process of configuration parameter, release configuration settling signal, starts the enable signal of normal work as System on Chip/SoC, and configuration settling signal only after the power-up in initial configuration effectively, after completing initial configuration process, this signal is in release conditions all the time.
As a further improvement on the present invention: carry out as follows with the detailed process of timing system work in real time:
S301: determine whether the timing reconfiguration time reaching initial configuration, if reach gate time, perform step S304, otherwise perform step S302;
S302: according to the order of parameter configuration, the configuration parameter be configured in each functional module of sampling successively, calculates the CRC32 check results of the configuration parameter that current chip runs;
S303: the CRC32 check results prestored in the CRC32 check results calculated in step S302 and exterior arrangement parameter is compared, if consistent, repeated execution of steps S302; Otherwise perform step S304;
S304: again read configuration parameter from exterior storage, namely completes primary parameter dynamic refresh again, and without the need to carrying out reset operation to the functional module in chip in refresh process, this process only determines the parameter signal that configuration parameter administration module exports.
As a further improvement on the present invention: in described step S3, after chip normally works, chip repeats the verification to configuration parameter; According to different space applied environments, i.e. satellite orbit parameter and the register upset probability at this rail conditions, the interval time of setting periodic refreshing, interval time leaves in configuration parameter list as configuration parameter, consistent with other parameters, do unified consolidation process.
Compared with prior art, the invention has the advantages that:
1, the system-level reinforcement means for the application of ASIC space of the present invention, refreshed by dynamic state of parameters and based on ASIC framework in-orbit without interruption recovery technique, improve the single-particle interrupt capabilities of chip, shown by the test of ground high energy particle at present: adopt the single event function interrupt ability of the asic chip of this invention technology to be: single-particle inversion threshold value:>=37MeVcm2/mg or≤1x10
-10mistake/position, sky, is in top standard in the industry, can meet the demand of all kinds of space exploration task.
2, the system-level reinforcement means for the application of ASIC space of the present invention, devises the parameter refresh time computing method based on ASIC first, is associated by the key parameters such as refresh time with orbit parameter, can guarantee the applicability that chip is applied at different track.
3, of the present invention for ASIC space application system-level reinforcement means, devise based on ASIC parameter without interruption method for refreshing, can in the reparation not interrupting completing chip normally works chip operation exception.
Accompanying drawing explanation
Fig. 1 is schematic flow sheet of the present invention.
Fig. 2 is the schematic flow sheet that the present invention carries out real-time verifying work in embody rule example.
Fig. 3 is the schematic flow sheet that the present invention carries out parameter configuration in embody rule example.
Fig. 4 is that the present invention carries out in real time and the schematic flow sheet of regularly system work in embody rule example.
Embodiment
Below with reference to Figure of description and specific embodiment, the present invention is described in further details.
As shown in Figure 1, a kind of system-level reinforcement means for the application of ASIC space of the present invention, the steps include:
S1: set up configuration parameter list, according to function definition and the demand of chip, defines the parameter needing configuration;
S2: the Design of Reinforcement of parameter configuration list, does reliability Design of Reinforcement to the parameter to be configured of definition;
S3: design verification in real time and periodic refreshing mechanism, namely after chip normally works, chip repeats the verification to configuration parameter; According to different space applied environments, i.e. satellite orbit parameter and the register upset probability at this rail conditions, the interval time of setting periodic refreshing, interval time leaves in configuration parameter list as configuration parameter, consistent with other parameters, do unified consolidation process;
S4: design chip being carried out to system-level dynamic refresh mechanism, the design of register cache mode is done to needing the parameter of configuration, the i.e. input signal of each configuration parameter using the form of static register as each functional module, these input signals in chip course of normal operation without the need to change;
S5: design chips parameter reconfiguration puts protection mechanism, guarantees the correctness of reconfiguration course;
S6: store the chip configuration parameter after reinforcing;
S7: read exterior arrangement parameter, complete initial configuration;
S8: after completing initial configuration, start to verify in real time work configuration parameter in the chips, if check results is wrong, carry out a dynamic refresh to configuration parameter, during parameter refreshes, chip normally works;
S9: the parameter reconfiguration according to design puts the time, if reach setup time, then carries out a dynamic refresh to all configuration parameters;
S10: dynamic refresh, consistent with initial parameter configuration effort flow process, in dynamic refresh process, chip begins normally to work, by the impact that dynamic state of parameters refreshes.
As shown in Figure 2, in embody rule example, the idiographic flow that the present invention carries out real-time verifying work is:
S101: the initial configuration completing chip;
S102: according to the order of parameter configuration, the configuration parameter be configured in each functional module of sampling successively, calculates the CRC32 check results of the configuration parameter that current chip runs;
S103: again read the configuration parameter being stored in chip exterior, this reads the CRC32 check results prestored in configuration parameter;
S104: the chip internal configuration parameter CRC32 check results that contrast conting obtains with deposit the CRC32 check results comprised in the space of parameter;
S105: if result is consistent, then repeated execution of steps S102, S103, S104 again; If result is inconsistent, then chip need reconfigure, and enters chip Reconfiguration Procedure.
As shown in Figure 3, in embody rule example, the detailed process that the present invention carries out parameter configuration is as follows:
S201: before chip is started working, after reading the configuration data of exterior storage, carry out the data decimation operation of one-out-three, if in three data, any two data read are identical, then select this identical data as the data used; Otherwise, then assert that this time is read data and occurred mistake, need restart to read data;
S202: be stored in parameter configuration management module as register to the configuration parameter after choosing;
S203: after having read all configuration parameters, carries out clock zone process to all parameters, under namely enabling configuration parameter be operated in the clock zone of actual use in functional module to parameter by the mode of sampling;
S204: after completing the clock zone process of configuration parameter, release configuration settling signal, starts the enable signal of normal work as System on Chip/SoC, and configuration settling signal only after the power-up in initial configuration effectively, after completing initial configuration process, this signal is in release conditions all the time.
As shown in Figure 4, in embody rule example, the present invention carries out as follows with the detailed process of timing system work in real time:
S301: determine whether the timing reconfiguration time reaching initial configuration, if reach gate time, perform step S304, otherwise perform step S302;
S302: according to the order of parameter configuration, the configuration parameter be configured in each functional module of sampling successively, calculates the CRC32 check results of the configuration parameter that current chip runs;
S303: the CRC32 check results prestored in the CRC32 check results calculated in step S302 and exterior arrangement parameter is compared, if consistent, repeated execution of steps S302; Otherwise perform step S304;
S304: again read configuration parameter from exterior storage, namely completes primary parameter dynamic refresh again, and without the need to carrying out the operations such as reset to the functional module in chip in refresh process, this process only determines the parameter signal that configuration parameter administration module exports.
Below be only the preferred embodiment of the present invention, protection scope of the present invention be not only confined to above-described embodiment, all technical schemes belonged under thinking of the present invention all belong to protection scope of the present invention.It should be pointed out that for those skilled in the art, some improvements and modifications without departing from the principles of the present invention, should be considered as protection scope of the present invention.
Claims (5)
1., for a system-level reinforcement means for ASIC space application, it is characterized in that, step is:
S1: set up configuration parameter list, according to function definition and the demand of chip, defines the parameter needing configuration;
S2: the reinforcing of parameter configuration list is arranged, does reliability to the parameter to be configured of definition and reinforces;
S3: verification in real time and periodic refreshing mechanism are set;
S4: arrange and system-level dynamic refresh mechanism is carried out to chip, do register cache mode to needing the parameter of configuration to arrange, the i.e. input signal of each configuration parameter using the form of static register as each functional module, these input signals in chip course of normal operation without the need to change;
S5: arrange chip parameter and reshuffle protection mechanism, guarantees the correctness of reconfiguration course;
S6: store the chip configuration parameter after reinforcing;
S7: read exterior arrangement parameter, complete initial configuration;
S8: after completing initial configuration, start to verify in real time work configuration parameter in the chips, if check results is wrong, carry out a dynamic refresh to configuration parameter, during parameter refreshes, chip normally works;
S9: the parameter reconfiguration according to arranging puts the time, if reach setup time, then carries out a dynamic refresh to all configuration parameters;
S10: dynamic refresh, consistent with initial parameter configuration effort flow process, in dynamic refresh process, chip begins normally to work, by the impact that dynamic state of parameters refreshes.
2. the system-level reinforcement means for the application of ASIC space according to claim 1, it is characterized in that, the idiographic flow carrying out real-time verifying work is:
S101: the initial configuration completing chip;
S102: according to the order of parameter configuration, the configuration parameter be configured in each functional module of sampling successively, calculates the CRC32 check results of the configuration parameter that current chip runs;
S103: again read the configuration parameter being stored in chip exterior, this reads the CRC32 check results prestored in configuration parameter;
S104: the chip internal configuration parameter CRC32 check results that contrast conting obtains with deposit the CRC32 check results comprised in the space of parameter;
S105: if result is consistent, then repeated execution of steps S102, S103, S104 again; If result is inconsistent, then chip need reconfigure, and enters chip Reconfiguration Procedure.
3. the system-level reinforcement means for the application of ASIC space according to claim 1, it is characterized in that, the detailed process carrying out parameter configuration is as follows:
S201: before chip is started working, after reading the configuration data of exterior storage, carry out the data decimation operation of one-out-three, if in three data, any two data read are identical, then select this identical data as the data used; Otherwise, then assert that this time is read data and occurred mistake, restart to read data;
S202: be stored in parameter configuration management module as register to the configuration parameter after choosing;
S203: after having read all configuration parameters, carries out clock zone process to all parameters, under namely enabling configuration parameter be operated in the clock zone of actual use in functional module to parameter by the mode of sampling;
S204: after completing the clock zone process of configuration parameter, release configuration settling signal, starts the enable signal of normal work as System on Chip/SoC, and configuration settling signal only after the power-up in initial configuration effectively, after completing initial configuration process, this signal is in release conditions all the time.
4. the system-level reinforcement means for the application of ASIC space according to claim 1, is characterized in that, carries out as follows with the detailed process of timing system work in real time:
S301: determine whether the timing reconfiguration time reaching initial configuration, if reach gate time, perform step S304, otherwise perform step S302;
S302: according to the order of parameter configuration, the configuration parameter be configured in each functional module of sampling successively, calculates the CRC32 check results of the configuration parameter that current chip runs;
S303: the CRC32 check results prestored in the CRC32 check results calculated in step S302 and exterior arrangement parameter is compared, if consistent, repeated execution of steps S302; Otherwise perform step S304;
S304: again read configuration parameter from exterior storage, namely completes primary parameter dynamic refresh again, and without the need to carrying out reset operation to the functional module in chip in refresh process, this process only determines the parameter signal that configuration parameter administration module exports.
5. the system-level reinforcement means for the application of ASIC space according to claim 1 or 2 or 3 or 4, it is characterized in that, in described step S3, after chip normally works, chip repeats the verification to configuration parameter; According to different space applied environments, i.e. satellite orbit parameter and the register upset probability at this rail conditions, the interval time of setting periodic refreshing, interval time leaves in configuration parameter list as configuration parameter, consistent with other parameters, do unified consolidation process.
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| CN109408111A (en) * | 2018-11-06 | 2019-03-01 | 上海航天测控通信研究所 | A kind of highly reliable A SIC chip parameter configuration method for space application |
| CN109407986A (en) * | 2018-10-17 | 2019-03-01 | 深圳市硅格半导体有限公司 | Method, system, server and the storage medium of real-time update equipment operating parameter |
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