CN105354048B - A kind of system-level reinforcement means for ASIC space applications - Google Patents
A kind of system-level reinforcement means for ASIC space applications Download PDFInfo
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Abstract
A kind of system-level reinforcement means for ASIC space applications, its step is：S1：Set up configuration parameter list；S2：The reinforcing of parameter configuration list is set, and the parameter to be configured to definition does reliability reinforcing；S3：Verification in real time and periodic refreshing mechanism are set；S4：Set and system-level dynamic refresh mechanism is carried out to chip, doing register cache pattern to the parameter for needing to configure is set；S5：Chip parameter is set to reconfigure protection mechanism, it is ensured that the correctness of reconfiguration course；S6：Chip configuration parameter after storage reinforcing；S7：Exterior arrangement parameter is read, initial configuration is completed；S8：Complete after initial configuration, start to verify the configuration parameter of work in the chips in real time；S9：Time is put according to the parameter reconfiguration of setting；S10：Dynamic refresh.The present invention has the advantages that easily realization, good reliability, applied widely.
Description
Technical field
Present invention relates generally to Department of Electronics's irrespective of size reliability reinforcement technique field, refer in particular to a kind of for ASIC space applications
System-level reinforcement means
Background technology
IC chip in electronic system is run in space radiation environment, the shadow irradiated by Energetic particle
Ring, easily produce single particle effect.Single particle effect will cause integrated circuit to damage in itself or function operation exception, so as to cause
Under whole electronic system dysfunction, serious conditions electronic system function will be made entirely ineffective.As large scale integrated circuit exists
What is used in space electronic system is more and more, and single particle effect can make integrated circuit occur logic state upset, logic
The instantaneous abnormal or interruption of function, and with CMOS (Complementary Metal Oxide Semiconductors) work
The decline of skill, the threshold voltage reduction of PN junction, such as scale programmable logic device (hereinafter referred to as FPGA Field
Programmable Gate Array), processor etc. face single particle effect and threaten increasingly severe, and there is presently no one kind
Chip production mode can ensure that chip prevents influence of the single particle effect to chip functions completely.
FPGA is because strong with disposal ability, and the advantages of function is programmable has obtained widely should in space electronic system
With causing it easily to be caused dysfunction by single particle effect the characteristics of due to FPGA itself.Large-scale application-specific integrated circuit
(Application Specific Integrated Circuit hereinafter referred to as ASIC) possess stronger anti-single particle upset and
The ability of accumulated dose, is widely used in the space exploration task such as reliability requirement height and longevity of service.
In order to improve the anti-single particle effect capability of asic chip, most of practitioner is more to enter from chip makes physical design level
Row Design of Reinforcement, this way does not have good solution to the single event function interrupt that single particle effect triggers.It is generally logical
The design of redundancy is crossed to reduce single event function interrupt etc., but the measure is by sacrificing the area and power consumption of asic chip for generation
The function-stable that valency is exchanged for.Shown according to current research on different space orbits, the influence of single particle effect is different
, if doing single reinforcement measure, special chip work optimization, the unnecessary power consumption of waste and chip face possibly can not be caused
Product.
From the foregoing, it will be observed that the ASIC device of existing space-oriented application is mainly set from chip design stage using redundancy or physics
The measure reinforced is counted, such design is to strengthen the reliability of ASIC device space application to increase power consumption or area as cost,
This method can not solve ASIC device by system single event function interrupt caused by Space Radiation Effects.Therefore, how from
System level improves the anti-single particle function interrupt capabilities of asic chip, and then improves asic chip or even system integrally anti-list
The ability of particle effect is that asic chip needs urgent problem to be solved in space application.
The content of the invention
The technical problem to be solved in the present invention is that：The technical problem existed for prior art, the present invention provides one
Plant easily realization, good reliability, the system-level reinforcement means for ASIC space applications applied widely.
In order to solve the above technical problems, the present invention uses following technical scheme：
A kind of system-level reinforcement means for ASIC space applications, its step is：
S1：Configuration parameter list is set up, according to the definition of the function of chip and demand, the parameter for needing to configure is defined；
S2：The reinforcing of parameter configuration list is set, and the parameter to be configured to definition does reliability reinforcing；
S3：Verification in real time and periodic refreshing mechanism are set；
S4：Set and system-level dynamic refresh mechanism is carried out to chip, register cache pattern is done to the parameter for needing to configure
Set, i.e., each configuration parameter using in the form of static register as each functional module input signal, these input signals are in core
Without changing in piece course of normal operation；
S5：Chip parameter is set to reconfigure protection mechanism, it is ensured that the correctness of reconfiguration course；
S6：Chip configuration parameter after storage reinforcing；
S7：Exterior arrangement parameter is read, initial configuration is completed；
S8：Complete after initial configuration, start to verify the configuration parameter of work in the chips in real time, if check results
It is wrong that a dynamic refresh, chip normal work during parameter refreshing are then carried out to configuration parameter；
S9：Time is put according to the parameter reconfiguration of setting, if reaching setup time, all configuration parameters once moved
State refreshes；
S10：Dynamic refresh, it is consistent with initial parameter configuration work flow, during dynamic refresh, chip beginning normal work
Make, not refreshed by dynamic state of parameters is influenceed.
As a further improvement on the present invention：The idiographic flow for carrying out real-time verifying work is：
S101：Complete the initial configuration of chip；
S102：According to the order of parameter configuration, sampling successively is configured to the configuration parameter in each functional module, calculates and work as
The CRC32 check results of the configuration parameter of preceding chip operation；
S103：The configuration parameter for being stored in chip exterior is re-read, this reads what is prestored in configuration parameter
CRC32 check results；
S104：The space Zhong Bao of the chip internal configuration parameter CRC32 check results that contrast conting is obtained and storage parameter
The CRC32 check results contained；
S105：If result is consistent, execution step S102, S103, S104 are repeated；If result is inconsistent, chip is needed
Reconfigure, into chip Reconfiguration Procedure.
As a further improvement on the present invention：The detailed process for carrying out parameter configuration is as follows：
S201：Before chip is started working, read after the configuration data of external storage, carry out the data decimation behaviour of one-out-three
Make, if in three data, the data that any two is read are identical, be then used as the data used from the identical data；Otherwise,
Then assert that this time reads data and mistake occur, restart to read data；
S202：Configuration parameter after selection is stored in parameter configuration management module as register；
S203：After all configuration parameters have been read, clock zone processing is carried out to all parameters, i.e., to parameter by adopting
The mode of sample enables configuration parameter to be operated under clock zone actually used in functional module；
S204：After the clock zone processing for completing configuration parameter, release configuration completes signal, starts normally as System on Chip/SoC
The enable signal of work, and configuration complete signal only after the power-up in initial configuration effectively, complete after initial configuration process, the letter
Number all the time release conditions are in.
As a further improvement on the present invention：The detailed process worked in real time with timing system is as follows：
S301：Determine whether to reach the timing reconfiguration time of initial configuration, step is performed if gate time is reached
S304, otherwise performs step S302；
S302：According to the order of parameter configuration, sampling successively is configured to the configuration parameter in each functional module, calculates and work as
The CRC32 check results of the configuration parameter of preceding chip operation；
S303：The CRC32 schools that obtained CRC32 check results will be calculated in step S302 with are prestored in exterior arrangement parameter
Test result to be compared, step S302 is repeated if consistent；Otherwise step S304 is performed；
S304：Again configuration parameter is read from external storage, i.e., completes primary parameter dynamic refresh again, was refreshing
Without carrying out reset operation to the functional module in chip in journey, the process only determines the parameter of configuration parameter management module output
Signal.
As a further improvement on the present invention：In the step S3, after chip normal work, chip repeat to
Put the verification of parameter；Turned over according to different space application environment, i.e. satellite orbit parameter and the register in this rail conditions
Turn probability, set the interval time of periodic refreshing, interval time is stored in configuration parameter list as configuration parameter, with other
Parameter is consistent, does unified consolidation process.
Compared with prior art, the advantage of the invention is that：
1st, the system-level reinforcement means for ASIC space applications of the invention, is refreshed by dynamic state of parameters and based on ASIC
Framework it is in-orbit without interrupt recovery technique, improve the single-particle interrupt capabilities of chip, tested at present by ground high energy particle
Show：Use the inventive technique asic chip single event function interrupt ability for：Single-particle inversion threshold value：≥37MeV·
Cm2/mg or≤1x10-10Mistake/day position, in top standard in the industry, can meet the demand of all kinds of space exploration tasks.
2nd, the system-level reinforcement means for ASIC space applications of the invention, devises the parameter brush based on ASIC first
New Time Calculation method, the key parameters such as refresh time is associated with orbit parameter, it can be ensured that chip is in different track applications
Applicability.
3rd, the system-level reinforcement means for ASIC space applications of the invention, devises the parameter based on ASIC without interruption
Method for refreshing, can be completed in the case where not interrupting chip normal work to the abnormal reparation of chip operation.
Brief description of the drawings
Fig. 1 is the schematic flow sheet of the present invention.
Fig. 2 is the schematic flow sheet that the present invention carries out real-time verifying work in concrete application example.
Fig. 3 is the schematic flow sheet that the present invention carries out parameter configuration in concrete application example.
Fig. 4 is the schematic flow sheet that the present invention is carried out working with timing system in real time in concrete application example.
Embodiment
The present invention is described in further details below with reference to Figure of description and specific embodiment.
As shown in figure 1, a kind of system-level reinforcement means for ASIC space applications of the present invention, its step is：
S1：Configuration parameter list is set up, according to the definition of the function of chip and demand, the parameter for needing to configure is defined；
S2：The Design of Reinforcement of parameter configuration list, the parameter to be configured to definition does reliability Design of Reinforcement；
S3：Design verification in real time and periodic refreshing mechanism, i.e., after chip normal work, chip repeats to configuration ginseng
Several verifications；It is according to different space application environment, i.e. satellite orbit parameter and general in the register upset of this rail conditions
Rate, sets the interval time of periodic refreshing, interval time is stored in configuration parameter list as configuration parameter, with other specification
Unanimously, unified consolidation process is done；
S4：The design of system-level dynamic refresh mechanism is carried out to chip, register cache mould is done to the parameter for needing to configure
Formula is designed, i.e., each configuration parameter using in the form of static register as each functional module input signal, these input signals exist
Without changing in chip course of normal operation；
S5：Design chips parameter reconfiguration puts protection mechanism, it is ensured that the correctness of reconfiguration course；
S6：Chip configuration parameter after storage reinforcing；
S7：Exterior arrangement parameter is read, initial configuration is completed；
S8：Complete after initial configuration, start to verify the configuration parameter of work in the chips in real time, if check results
It is wrong that a dynamic refresh, chip normal work during parameter refreshing are then carried out to configuration parameter；
S9：Time is put according to the parameter reconfiguration of design, if reaching setup time, all configuration parameters once moved
State refreshes；
S10：Dynamic refresh, it is consistent with initial parameter configuration work flow, during dynamic refresh, chip beginning normal work
Make, not refreshed by dynamic state of parameters is influenceed.
As shown in Fig. 2 in concrete application example, the idiographic flow that the present invention carries out real-time verifying work is：
S101：Complete the initial configuration of chip；
S102：According to the order of parameter configuration, sampling successively is configured to the configuration parameter in each functional module, calculates and work as
The CRC32 check results of the configuration parameter of preceding chip operation；
S103：The configuration parameter for being stored in chip exterior is re-read, this reads what is prestored in configuration parameter
CRC32 check results；
S104：The space Zhong Bao of the chip internal configuration parameter CRC32 check results that contrast conting is obtained and storage parameter
The CRC32 check results contained；
S105：If result is consistent, execution step S102, S103, S104 are repeated；If result is inconsistent, chip is needed
Reconfigure, into chip Reconfiguration Procedure.
As shown in figure 3, in concrete application example, the detailed process that the present invention carries out parameter configuration is as follows：
S201：Before chip is started working, read after the configuration data of external storage, carry out the data decimation behaviour of one-out-three
Make, if in three data, the data that any two is read are identical, be then used as the data used from the identical data；Otherwise,
Then assert that this time reads data and mistake occur, need to restart to read data；
S202：Configuration parameter after selection is stored in parameter configuration management module as register；
S203：After all configuration parameters have been read, clock zone processing is carried out to all parameters, i.e., to parameter by adopting
The mode of sample enables configuration parameter to be operated under clock zone actually used in functional module；
S204：After the clock zone processing for completing configuration parameter, release configuration completes signal, starts normally as System on Chip/SoC
The enable signal of work, and configuration complete signal only after the power-up in initial configuration effectively, complete after initial configuration process, the letter
Number all the time release conditions are in.
As shown in figure 4, in concrete application example, the present invention carries out the detailed process worked in real time with timing system such as
Under：
S301：Determine whether to reach the timing reconfiguration time of initial configuration, step is performed if gate time is reached
S304, otherwise performs step S302；
S302：According to the order of parameter configuration, sampling successively is configured to the configuration parameter in each functional module, calculates and work as
The CRC32 check results of the configuration parameter of preceding chip operation；
S303：The CRC32 schools that obtained CRC32 check results will be calculated in step S302 with are prestored in exterior arrangement parameter
Test result to be compared, step S302 is repeated if consistent；Otherwise step S304 is performed；
S304：Again configuration parameter is read from external storage, i.e., completes primary parameter dynamic refresh again, was refreshing
The operation such as reset without being carried out to the functional module in chip in journey, the process only determines the ginseng of configuration parameter management module output
Number signal.
It the above is only the preferred embodiment of the present invention, protection scope of the present invention is not limited merely to above-described embodiment,
All technical schemes belonged under thinking of the present invention belong to protection scope of the present invention.It should be pointed out that for the art
For those of ordinary skill, some improvements and modifications without departing from the principles of the present invention should be regarded as the protection of the present invention
Scope.
Claims (5)
1. a kind of system-level reinforcement means for ASIC space applications, it is characterised in that step is：
S1：Parameter configuration list cell is set up, according to the definition of the function of chip and demand, the parameter for needing to configure is defined；
S2：The reinforcing of parameter configuration list cell is set, to definition the need for the parameter that configures do reliability reinforcing；
S3：Verification in real time and periodic refreshing mechanism are set；
S4：Set and system-level dynamic refresh mechanism carried out to chip, doing register cache pattern to the parameter for needing to configure is set,
I.e. each configuration parameter using in the form of static register as each functional module input signal, these input signals are normal in chip
Without changing in the course of work；
S5：Chip parameter is set to reconfigure protection mechanism, it is ensured that the correctness of reconfiguration course；
S6：The parameter of chip configuration after storage reinforcing；
S7：The parameter of exterior arrangement is read, initial configuration is completed；
S8：Complete after initial configuration, start to verify the parameter that work is configured in the chips in real time, if check results are wrong
A dynamic refresh, chip normal work during parameter refreshing are then carried out to the parameter configured in chip；
S9：Time is put according to the parameter reconfiguration of setting, if reaching setup time, one is carried out to the parameter configured in all chips
Secondary dynamic refresh；
S10：Dynamic refresh, consistent with initial parameter configuration work flow, during dynamic refresh, chip is normal work,
Not refreshed by dynamic state of parameters is influenceed.
2. the system-level reinforcement means according to claim 1 for ASIC space applications, it is characterised in that carry out real-time
The idiographic flow of verifying work is：
S101：Complete the initial configuration of chip；
S102：According to the order of parameter configuration, sampling successively is configured to the configuration parameter in each functional module, calculates current core
The CRC32 check results of the configuration parameter of piece operation；
S103：The configuration parameter for being stored in chip exterior is re-read, this reads the CRC32 prestored in configuration parameter
Check results；
S104：Prestored in chip internal configuration parameter CRC32 check results and configuration parameter that contrast conting is obtained
CRC32 check results；
S105：If result is consistent, execution step S102, S103, S104 are repeated；If result is inconsistent, chip is needed again
Configuration, into chip Reconfiguration Procedure.
3. the system-level reinforcement means according to claim 1 for ASIC space applications, it is characterised in that carry out parameter
The detailed process of configuration is as follows：
S201：Before chip is started working, read after the configuration data of external storage, carry out the data decimation operation of one-out-three,
If in three data, the data that any two is read are identical, then the data used are used as from the identical data；Otherwise, then
Assert that this time reads data and mistake occur, restart to read data；
S202：Configuration parameter after selection is stored in parameter configuration management module as register；
S203：After all configuration parameters have been read, clock zone processing is carried out to all parameters, i.e., sampling is passed through to parameter
Mode enables configuration parameter to be operated under clock zone actually used in functional module；
S204：After the clock zone processing for completing configuration parameter, release configuration completes signal, and normal work is started as System on Chip/SoC
Enable signal, and configuration complete signal only after the power-up in initial configuration effectively, complete after initial configuration process, the signal begins
Release conditions are in eventually.
4. the system-level reinforcement means according to claim 1 for ASIC space applications, it is characterised in that carry out real-time
The detailed process worked with timing system is as follows：
S301：Determine whether to reach the timing reconfiguration time of initial configuration, step S304 is performed if gate time is reached, it is no
Then perform step S302；
S302：According to the order of parameter configuration, sampling successively is configured to the configuration parameter in each functional module, calculates current core
The CRC32 check results of the configuration parameter of piece operation；
S303：CRC32 of the obtained CRC32 check results with being prestored in exterior arrangement parameter will be calculated in step S302 and will verify knot
Fruit is compared, and step S302 is repeated if consistent；Otherwise step S304 is performed；
S304：Again configuration parameter is read from external storage, i.e., primary parameter dynamic refresh is completed again, in refresh process
Without carrying out reset operation to the functional module in chip, the process only determines the parameter letter exported during configuration parameter management
Number.
5. the system-level reinforcement means for ASIC space applications according to claim 1 or 2 or 3 or 4, its feature exists
In in the step S3, after chip normal work, chip repeats the verification to configuration parameter；According to different spaces
Applied environment, i.e. satellite orbit parameter and the register upset probability in this rail conditions, when setting the interval of periodic refreshing
Between, interval time is stored in parameter configuration list cell as configuration parameter, consistent with other specification, is done at unified reinforcing
Reason.
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| CN109408111A (en) * | 2018-11-06 | 2019-03-01 | 上海航天测控通信研究所 | A kind of highly reliable A SIC chip parameter configuration method for space application |
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| CN103218272B (en) * | 2013-04-25 | 2015-09-23 | 西安空间无线电技术研究所 | A kind of spaceborne digital signal processor upset reinforcement means |
| CN104239090B (en) * | 2014-07-15 | 2017-12-22 | 上海微小卫星工程中心 | A kind of in-orbit reconfiguration system of satellite house keeping computer and method based on FPGA |
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