CN109408111A - A kind of highly reliable A SIC chip parameter configuration method for space application - Google Patents
A kind of highly reliable A SIC chip parameter configuration method for space application Download PDFInfo
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- CN109408111A CN109408111A CN201811313290.XA CN201811313290A CN109408111A CN 109408111 A CN109408111 A CN 109408111A CN 201811313290 A CN201811313290 A CN 201811313290A CN 109408111 A CN109408111 A CN 109408111A
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- asic
- parameter configuration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/70—Software maintenance or management
- G06F8/71—Version control; Configuration management
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Abstract
The invention discloses a kind of highly reliable A SIC chip parameter configuration methods for space application, the following steps are included: 1) divide the programmable storage region of a part in the chip interior of FPGA, parameter configuration data is stored wherein, and function logic, parameter value, timing interface carry out unification design according to PROM interface requirement；2) on FPGA witness plate, multiple parameter is carried out to ASIC for PROM and reads verification verifying；3) after the completion of the parameter configuration pre-authentication for completing to carry out on the basis of FPGA, the parameter region in the programmable storage region marked on FPGA is burned onto PROM chip, program area carries out ASIC flow work other than parameter region.The present invention realizes the configuration of highly reliable A SIC chip parameter, prevents asic chip SRAM single-particle inversion in space environment.
Description
Technical field
The present invention relates to field of aerospace technology more particularly to a kind of highly reliable A SIC chip ginsengs for space application
Number configuration method.
Background technique
As the mankind further investigate the outer space, the avionics equipment radiation environment to be faced is also more complicated.For
For integrated circuit in spacecraft, memory occupies extremely important status, and the height of the radiation resistance of memory is direct
Influence the stability of space equipment.When single particle enters transmit-receive radio road, the data that may result in storage unit change,
That is single-particle inversion.With the continuous reduction of process, circuit level is stepped up, harm of the single particle to memory
It gets worse.Traditional reinforcement technique, such as: SOI technology, at high cost and itself parasitic effect are to the harm of circuit bring
Very important, and the circuit-level reinforcement technique by increasing redundant storage node needs additional area overhead, while circuit
The raising of integrated level causes this design philosophy to face failure.
Summary of the invention
In order to solve the problems, such as that asic chip parameter configuration part SRAM single-particle inversion, the present invention mention in space environment
A kind of highly reliable A SIC chip parameter configuration method for space application is gone out.
The technical scheme adopted by the invention is that:
A kind of highly reliable A SIC chip parameter configuration method for space application, comprising the following steps:
1) the programmable storage region of a part is divided in the chip interior of FPGA, stores parameter configuration data wherein,
Function logic, parameter value, timing interface carry out unification design according to PROM interface requirement；
2) on FPGA witness plate, multiple parameter is carried out to ASIC for PROM and reads verification verifying；
3) it after the completion of completing the parameter configuration pre-authentication that carries out on the basis of FPGA, programmable is deposited what is marked on FPGA
Parameter region in storage area domain is burned onto PROM chip, and program area carries out ASIC flow work other than parameter region.
Further, step 2) includes following procedure:
Asic chip continuously reads cubic parametric configuration item, when cubic parametric configuration item data is identical, it is believed that
Parameter verification success, then asic chip uses the configuration；When wherein exist certain primary parameter configuration item and another or it is two another
When parameter configuration item data difference, it is believed that parameter verification is unsuccessful, then asic chip re-reads cubic parametric configuration item, until
Until cubic parametric configuration item data is identical.
Compared with prior art, the present invention is had many advantages, such as using FPGA verifying ASIC, comprising:
Verifying speed is fast；
The comprehensive system level verification of ASIC function can be realized in system；
Effectively shorten the ASIC design period；
FPGA witness plate may be reused, save the cost.
Detailed description of the invention
Fig. 1 is the method for parameter configuration flow chart that the present invention is directed to space application；
Fig. 2 is to transplant after the present invention is proved to be successful on the basis of FPGA for the method for parameter configuration of space application to ASIC
Flow diagram.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to each reality of the invention
The mode of applying is explained in detail.
As shown in Figure 1, portion marks off a part of programmable storage region to FPGA in the chip, storage is joined wherein
Number configuration data, function logic, parameter value, timing interface carry out unification design according to PROM (17V16) interface requirement.
After chip powers on and after determining that chip interior work clock is stablized, FPGA opens parameter configuration process, starts every
One group of read work three times is carried out to the storage region every a period of time, by the parameter configuration module inside FPGA to reading
Every group of cubic parametric configuration data carries out correct sex determination: if the cubic parametric configuration data read is consistent, being determined as parameter
Configuration data is correct, and FPGA then carries out parameter configuration according to the data；If existing in the cubic parametric configuration data read primary
Data from it is different twice, then determine that this group of data are incorrect, chip will not carry out parameter configuration according to this group of data, restart
One group of new parameter configuration data is read, until the cubic parametric configuration data of reading is consistent.Fpga chip is according to setting
Time carries out one group of parameter configuration data read work three times every the set time.
After the completion of the highly reliable parameter configuration pre-authentication for completing to carry out on the basis of FPGA, compiled what is marked on FPGA
Program area carries out ASIC flow work, the programmable storage region that will be marked on FPGA other than parameter region in journey storage region
In parameter region be burned onto PROM chip, the height to ASIC is completed in the final refresh work for realizing PROM chip to asic chip
Reliable parameter configuration.
The process that Fig. 2 is transplanted after being proved to be successful on the basis of FPGA for the method for parameter configuration for space application to ASIC
Block diagram.
It need to be designed in strict accordance with chip interface timing requirements in migration process, while consider that the circuit design of hardware is poor
Different to may cause hardware time order anxiety, chip, which is designed as sampling instant, can configure, and select rising edge or failing edge sample mode.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by anyone skilled in the art,
It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with scope of protection of the claims
Subject to.
Claims (2)
1. a kind of highly reliable A SIC chip parameter configuration method for space application, which comprises the following steps:
1) the programmable storage region of a part is divided in the chip interior of FPGA, stores parameter configuration data, function wherein
Logic, parameter value, timing interface carry out unification design according to PROM interface requirement；
2) on FPGA witness plate, multiple parameter is carried out to ASIC for PROM and reads verification verifying；
3) after the completion of completing the parameter configuration pre-authentication that carries out on the basis of FPGA, programmable memory block that will be marked on FPGA
Parameter region in domain is burned onto PROM chip, and program area carries out ASIC flow work other than parameter region.
2. the highly reliable A SIC chip parameter configuration method according to claim 1 for space application, which is characterized in that
Step 2) includes following procedure:
Asic chip continuously reads cubic parametric configuration item, when cubic parametric configuration item data is identical, it is believed that parameter
It verifies successfully, then asic chip uses the configuration；When wherein in the presence of certain primary parameter configuration item and another or another two parameters
When configuring item data difference, it is believed that parameter verification is unsuccessful, then asic chip re-reads cubic parametric configuration item, until three times
Until parameter configuration item data is identical.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201811313290.XA CN109408111A (en) | 2018-11-06 | 2018-11-06 | A kind of highly reliable A SIC chip parameter configuration method for space application |
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| CN201811313290.XA CN109408111A (en) | 2018-11-06 | 2018-11-06 | A kind of highly reliable A SIC chip parameter configuration method for space application |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113805044A (en) * | 2021-11-16 | 2021-12-17 | 北京智芯微电子科技有限公司 | Chip reliability assessment method and device and chip |
| CN117194319A (en) * | 2023-11-03 | 2023-12-08 | 南通清浪智能科技有限公司 | High-reliability chip parameter configuration method and system based on ASIC method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113805044A (en) * | 2021-11-16 | 2021-12-17 | 北京智芯微电子科技有限公司 | Chip reliability assessment method and device and chip |
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| CN117194319B (en) * | 2023-11-03 | 2024-01-26 | 南通清浪智能科技有限公司 | High-reliability chip parameter configuration method and system based on ASIC method |
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