CN102332307B - SRAM type FPGA single particle effect test system and method - Google Patents
SRAM type FPGA single particle effect test system and method Download PDFInfo
- Publication number
- CN102332307B CN102332307B CN201110214108.7A CN201110214108A CN102332307B CN 102332307 B CN102332307 B CN 102332307B CN 201110214108 A CN201110214108 A CN 201110214108A CN 102332307 B CN102332307 B CN 102332307B
- Authority
- CN
- China
- Prior art keywords
- fpga
- configuration
- tested
- test
- processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
SRAM type FPGA single particle effect test system and method comprises: processor of single chip computer, RS232 interface circuit, usb circuit, test FPGA and storage unit, may be used for the config memory of SRAM type FPGA and the direct fault location test of BRAM, the single event function interrupt realizing SRAM type FPGA detects, locking single particle detects and single-particle inversion detects, and comprises configuration store district, the single-particle inversion of BRAM and trigger detects.The present invention have simple to operate, detect comprehensively, accuracy is high, real-time good, the advantage of highly versatile.
Description
Technical field
The present invention relates to a kind of SRAM type FPGA single particle effect test system and method.
Background technology
FPGA is reconfigurable new device, uses FPGA, can accelerate the Development Schedule of satellite, shorten the lead time, improve the performance of satellite simultaneously in satellite development.Satellite operation is in space radiation environment, and radiation effect can cause FPGA performance degradation even to lose efficacy, and the FPGA performance degradation that single-particle radiation effect causes is particularly evident.Before satellite uses FPGA, must carry out single particle effect detection to FPGA, by test, assessment single particle effect susceptibility, selects device and system to carry out radiation tolerance design for model and provides foundation.
Domestic single particle experiment mainly concentrates on the fixed function device of each quasi-tradition, as microprocessor, storer, DLC (digital logic circuit), A/D, D/A converter etc., and FPGA has the difference of essence in 26S Proteasome Structure and Function principle with the device studied in the past, the function realized in systems in which and interconnector are determined by configuration file, and configuration file is stored in the SRAM district of single-particle sensitivity, therefore the device can not being regarded as fixed logic function on Cleaning Principle carries out single-particle simulation test, but need to design brand-new detection system for its design feature and carry out single particle effect detection.
The domestic unit being engaged in the research of SRAM type FPGA single particle effect detection is mainly the National University of Defense Technology at present.The detection method of single-particle inversion and device in the field programmable gate array of the National University of Defense technology, only for the detection of SRAM type FPGA single particle upset effect, adopt retaking of a year or grade configuration frame and original configuration frame to carry out the detection mode of direct byte comparison.There is the data redundancy of some in the retaking of a year or grade configuration frame due to SRAM type FPGA, adopts retaking of a year or grade configuration frame and original configuration frame to carry out the detection mode of direct byte comparison, do not get rid of the redundant data of retaking of a year or grade configuration frame, can affect detection efficiency; In addition, the meeting of single event function interrupt to single-particle inversion result precision causes certain influence, adopts retaking of a year or grade configuration frame and original configuration frame to carry out the single detection mode of direct byte comparison, the single-particle inversion testing result obtained, likely inaccurate.
Under SRAM type FPGA single particle effect direct fault location is mainly used in non-radiation environment, the Single event upset effecf of simulation SRAM type FPGA configuration store district and BRAM, carries out the influence research of Single event upset effecf.The domestic unit being engaged in the research of SRAM type FPGA single particle effect direct fault location is mainly Shanghai Engineering Center for Microsatellites and Beijing Times Minxin Technology Co., Ltd at present.The automatic intelligent single-particle fault injector of Shanghai Engineering Center for Microsatellites, the main software emulation mode that adopts is carried out, and no longer experimental study carried out by actual hardware platform.The fault injection system of Beijing Times Minxin Technology Co., Ltd and method thereof need, by making trouble unit module, the gate leve HDL code of modifying target circuit, to generate faulty circuit, and the required professional ability of operation is higher, and process is complicated.
The report being engaged in single particle effect experimental study abroad mainly contains XILINX company of the U.S. and European SAAB testing laboratory, XILINX company of the U.S. is the Production design side of FPGA, grasp the core technology of such device completely, have employed custom-designed check-out console, upper computer detection software and IP kernel, can complete more all sidedly and the single particle effect of tested FPGA internal resource is detected and direct fault location, but the FPGA internal resource detection technique of test application is also unexposed, a large amount of technology is domestic cannot be obtained, and its detection method is that tested FPGA is configured to fixed logic function, device universal internal resource is detected by special software by outer computer, its detection scheme is not for the application specific logic of device, Europe SAAB testing laboratory cooperates with Xilinx company, and have employed custom-designed check-out console, upper computer detection software and IP kernel and carry out single particle effect detection and direct fault location, its detection technique details is unexposed, domesticly cannot obtain.
Summary of the invention
The technical matters that the present invention solves is: overcome the deficiencies in the prior art, provide simple to operate, detect comprehensively, accuracy is high, real-time good, the SRAM type FPGA single particle effect test system and method for highly versatile.
Technical solution of the present invention is: SRAM type FPGA single particle effect test system comprises: processor of single chip computer, RS232 interface, USB interface, test FPGA and storage unit, wherein:
Processor of single chip computer: receive the configuration data and control command that transmit outside, and data and order are delivered to test FPGA; According to external control order, arrange that test FPGA is configuration operation state, refresh operation state, direct fault location state, single-particle inversion and function interrupt detecting mode of operation and trigger overturns and detects mode of operation; Receive control command feedback signal and testing result from test FPGA, and externally export;
Test FPGA: carry out initialization to storage unit according to the order that processor of single chip computer transmits, receives the configuration data that processor of single chip computer transmits, and deposits to storage unit, enter corresponding mode of operation according to the order that processor of single chip computer transmits, described mode of operation comprises configuration operation state, refresh operation state, direct fault location state, single-particle inversion and function to interrupt detecting mode of operation and trigger and overturns and detect mode of operation, when configuration operation state, test FPGA reads configuration data from storage unit, is configured operation to tested FPGA, and to processor of single chip computer feedback configuration operating result, during refresh operation state, operation is configured to tested FPGA, and to processor of single chip computer feedback configuration operating result, during direct fault location state, after test FPGA receives the direct fault location operational order of processor of single chip computer, receive therefore drop data information from host computer via USB interface, by the series arrangement mouth of tested FPGA, part reprovision is carried out to tested FPGA, in the configuration bit Write fault data of assigned address, described part reprovision is only modified for the segment of FPGA configuration file, thus complete and carry out direct fault location to tested FPGA, when single-particle inversion and function interrupt detecting mode of operation, from the configuration data that tested FPGA retaking of a year or grade is current, by carrying out single-particle inversion detection with comparing of original configuration data, single event function interrupt detection is carried out by reading and writing tested FPGA configuration address register and detecting DONE pin, when confirmation FPGA does not have to have no progeny in generating function, synch command and configuration data read-backward command is sent successively to tested FPGA, and detect the BUSY pin of tested FPGA, when BUSY pin is invalid, the corresponding positions of the original configuration data significance bit of the configuration data of retaking of a year or grade and storer stored carries out real-time comparison, statistics upset sum, and statistics is sent to processor of single chip computer, when trigger upset detects mode of operation, first test FPGA refreshes the configuration data of tested FPGA, guarantee that tested FPGA user logical link is communicated with, then user's trigger value of tested FPGA is read, compare with institute initialize, statistics upset sum, and statistics is sent to processor of single chip computer,
Storage unit: for storing the configuration data that outside is transmitted;
RS232 interface: complete host computer and send control command to processor of single chip computer, and receive control command feedback or testing result from single-chip microcomputer;
USB interface: complete host computer and send tested FPGA original configuration data to processor of single chip computer.
The course of work of described processor of single chip computer is:
First processor of single chip computer carries out initialization operation, then enters into cycling; During cycling, processor of single chip computer cycle detection RS232 interface signal inputs, and determines that next step needs the operation carried out; Interrupt detecting operational order or trigger and overturn if processor of single chip computer receives configuration operation order, refresh operation order, direct fault location order, single-particle inversion and function from RS232 interface and detect operational order, then the corresponding command is sent to test FPGA, after FPGA to be tested completes corresponding operating, receive control command feedback signal or testing result from test FPGA, externally transmit through RS232 interface.Processor of single chip computer, completing all after dates of a command operation, reenters cycling, waits for Next Command.
The course of work that described configuration data receives is:
First test FPGA carries out initialization operation, then enters into cycling; During cycling, the signal input of test FPGA cycle detection USB interface, if test FPGA receives configuration data download command from USB interface, then stops other operations, receive the original configuration data of tested FPGA continuously from USB interface, and transfer to test FPGA to store.
The configuration operation process of described test FPGA is:
After receiving the configuration operation order of processor of single chip computer, the configuration of enable tested FPGA controls pin CS, WRITE and PROGRAM, and ensure that PROGRAM signal keeps low level at least 300ns, then the INIT pin that tested FPGA exports is detected, read configuration data when INIT pin is effective from the first address of config memory and write tested FPGA, detect the BUSY pin of tested FPGA simultaneously, when BUSY pin is invalid, represent that these address configuration data have been written into tested FPGA, by the cyclic address change of config memory, repeat write operation, until the whole configuration datas in config memory are sent, then detect the DONE pin that tested FPGA exports, when DONE pin is effective, represent the configuration successful of tested FPGA, after tested FPGA configuration successful, test FPGA starts to carry out initialization operation to user's trigger of tested FPGA, and after initialization operation completes, whole configuration operation all terminates.
The refresh operations of described test FPGA is:
After receiving the refresh operation order of processor of single chip computer, read configuration data from the first address of config memory and write tested FPGA, detect the BUSY pin of tested FPGA simultaneously, when BUSY pin is invalid, represent that these address configuration data have been written into tested FPGA, by the cyclic address change of config memory, repeat write operation, until be sent by the whole configuration datas in config memory.
SRAM type FPGA single particle effect test method, is characterized in that comprising direct fault location; Single-particle inversion detects, and comprises configuration store district, BRAM and trigger upset and detects; Single event function interrupt detects; Locking single particle detects one of four parts;
Wherein said fault filling method step is as follows:
The position of (a) host computer determination direct fault location configuration bit, and fault location information is sent to processor of single chip computer;
B fault location information is sent to test FPGA by () processor of single chip computer;
C FPGA is according to the positional information received in () test, by the series arrangement mouth of tested FPGA, carry out part reprovision to tested FPGA, and the configuration data of change corresponding configuration position, realizes direct fault location;
Described single-particle inversion detects and single event function interrupt combining data detection completes, and performing step is as follows:
(1) selective radiation source;
(2) send initialization command by outside, configuration data is delivered in storage unit, complete initialization;
(3) after initialization terminates, send configuration order by externally to processor of single chip computer, start test FPGA and operation is configured to tested FPGA;
(4) after configuration operation completes, send sense command by externally to processor of single chip computer, start the cycle detection operation of test FPGA;
(5) use radiation source to produce high energy particle and irradiate tested fpga chip surface;
(6) test configuration address register and the DONE pin that FPGA detects tested FPGA, judge whether tested FPGA single event function interrupt occurs, complete the single event function interrupt test of tested FPGA;
(7) when confirming that single event function interrupt does not occur FPGA, the configuration data of the tested FPGA of test FPGA retaking of a year or grade, the corresponding positions of the original configuration data significance bit of the configuration data of retaking of a year or grade and storer stored carries out real-time comparison, add up configuration store district and BRAM upset sum respectively, and statistics is sent to processor of single chip computer;
(8) circulation performs step (6) ~ (7), terminates until high energy particle irradiates;
(9) refresh the configuration data of tested FPGA, read user's trigger value of tested FPGA, compare with institute initialize, statistics upset sum, and statistics is sent to processor of single chip computer, complete trigger function interrupt test;
Described locking single particle detection method performing step is as follows:
(A) selective radiation source;
(B) send initialization command by outside, configuration data is delivered in storage unit, complete initialization;
(C) after initialization terminates, send configuration order by externally to processor of single chip computer, start test FPGA and operation is configured to tested FPGA;
(D) use radiation source to produce high energy particle and irradiate tested fpga chip surface;
(E) configuration data of the tested FPGA of periodic refreshing, working current when preventing tested FPGA from locking single particle not occurring is excessive;
(F) if find, tested FPGA working current becomes suddenly large, exceedes detection threshold, and after refresh configuration data, electric current is substantially unchanged, then judge that locking single particle occurs tested FPGA.
Radiation source in described step (1), (A) is cyclotron or tandem accelerator, and its high energy particle range in silicon produced is greater than 30 μm, and LET value is greater than 30MeV.cm
2/ mg.
Irradiating the condition terminated in described step (8) is: single event function interrupt occurs tested FPGA, or the fluence of radiation source irradiation particle reaches 9 × 10
4~ 10
5/ cm
2.
The present invention's advantage is compared with prior art:
(1) the present invention is simple to operate.Existing fault filling method needs, by making trouble unit module, the gate leve HDL code of modifying target circuit, to generate faulty circuit, and the required professional ability of operation is higher, and process is complicated.Fault filling method of the present invention, only needs specified fault position, just completes direct fault location by part reprovision, simple to operate.
(2) the present invention detects comprehensively.The single-particle inversion that can only detect configuration store district and BRAM that prior art has, the present invention can realize configuration store district, the single-particle inversion of BRAM and trigger detects, and single event function interrupt detects, and locking single particle detects, and detects comprehensively.
(3) single-particle inversion accuracy in detection of the present invention is high.Prior art directly by total for the difference position of retaking of a year or grade configuration data and original configuration data, as single-particle inversion sum, does not consider the impact of single event function interrupt on single-particle inversion testing result accuracy.The present invention is by considering the testing result of single-particle inversion and single event function interrupt, and assert final single-particle inversion testing result, accuracy is high.
(4) single-particle inversion detection real-time of the present invention is good.Prior art some the configuration data of retaking of a year or grade is stored as retaking of a year or grade configuration file, draw testing result by the non real-time comparison of retaking of a year or grade configuration file and original configuration file; Some allows whole retaking of a year or grade configuration datas all participate in comparison operation, and efficiency is low, poor real.The significance bit that single-particle inversion of the present invention detects extracting directly back read data carries out real-time comparison, obtains overturning testing result, and get rid of the impact of redundant data, efficiency is high, and real-time is good.
(5) the present invention by the configuration file of any function of host computer remote download to tested FPGA, can realize any applied logic function of tested FPGA, highly versatile; This Remote configuration function can be used for the FPGA single particle simulation test in space flight model, the single-particle susceptibility of effective effect card concrete configuration function, for engineer applied single-particle know the real situation test and in-orbit failure analysis there is practical significance.
Accompanying drawing explanation
Fig. 1 is the theory diagram of SRAM type FPGA single particle effect test system of the present invention;
Fig. 2 is the workflow diagram of SRAM type FPGA single particle effect test system monolithic processor of the present invention;
Fig. 3 is SRAM type FPGA single particle effect test system testing FPGA of the present invention is configured operation workflow diagram to tested FPGA;
Fig. 4 is SRAM type FPGA single particle effect test system testing FPGA of the present invention carries out refresh operation workflow diagram to tested FPGA;
Fig. 5 is SRAM type FPGA single particle effect test system testing FPGA of the present invention carries out direct fault location operation workflow diagram to tested FPGA.
Fig. 6 is that SRAM type FPGA single particle effect test system testing FPGA of the present invention carries out single-particle inversion to tested FPGA and function interrupts detecting the workflow diagram operated.
Fig. 7 is that SRAM type FPGA single particle effect test system testing FPGA of the present invention carries out to tested FPGA the workflow diagram that trigger upset detects operation.
Embodiment
As shown in Figure 1, be the composition frame chart of SRAM type FPGA single particle effect test system of the present invention, comprise processor of single chip computer, RS232 interface circuit, usb circuit, test FPGA and storage unit.The present invention is in concrete enforcement, processor of single chip computer selects the C8051F020 of Silicon Laboratories company, test FPGA selects the Cyclone III Series FPGA EP3C120F780C7 of altera corp, tested FPGA selects the Virtex Series FPGA XQV300-4CB228 of Xilinx company, the series arrangement mouth of this FPGA is JTAG mouth, and parallel deployment mouth is SelectMAP mouth.
First carry out corresponding initialization operation, after powering on, processor of single chip computer and test FPGA complete program loading and initialization automatically.The signal input of test FPGA cycle detection USB interface, if receive configurator download instruction from USB interface, then stops other operations, starts configuration data down operation, receive configuration data, write storage unit from USB interface.The signal input of processor of single chip computer cycle detection RS232 interface, if from RS232 interface to configuration operation order, refresh operation order, direct fault location order, single-particle inversion and function interrupt detecting operational order or trigger and overturn and detect operational order, then the corresponding command is sent to test FPGA.Test FPGA reads desired data from storage unit, by series arrangement mouth or the parallel deployment mouth of tested FPGA, complete corresponding operation, and control command feedback signal or testing result are sent to processor of single chip computer, sent to host computer by RS232 by processor of single chip computer.
As shown in Figure 2, be the processor of single chip computer workflow diagram of SRAM type FPGA single particle effect test system of the present invention.After system electrification, processor of single chip computer cycle detection RS232 interface has no signal to input.If no signal inputs, then continue cycle detection; If there is signal to input, then input signal is decoded, and send corresponding control command to test FPGA.After order is sent completely, FPGA is with or without control command feedback signal or testing result for the test of processor of single chip computer cycle detection.If test FPGA does not provide control command feedback signal or testing result in setting-up time, then processor of single chip computer sends time-out error signal to host computer; If the feedback signal of receiving orders or testing result, then order feedback signal or testing result are sent to host computer.After being sent completely, processor of single chip computer again cycle detection RS232 interface has no signal to input.
As shown in Figure 3, be the configuration operation workflow diagram of SRAM type FPGA single particle effect test system of the present invention.When testing FPGA and receiving configuration operation order from processor of single chip computer, start the configuration operation to tested FPGA.First configuration control signal CS, WRITE and PROGRAM of enable tested FPGA, keep PEOGRAM low level at least 300ns, then detects INIT signal.If INIT signal is ineffective in official hour, then tests FPGA and send configuration failure signal to processor of single chip computer, terminate this configuration operation; If INIT signal effectively, then, when detecting configuration data transmitting counter and BUSY signal, sends configuration data, until all configuration datas are sent completely by SelectMAP mouth to tested FPGA in official hour.After configuration data is sent completely, detect the DONE signal of tested FPGA.If DONE is ineffective in official hour, then tests FPGA and send configuration failure signal to processor of single chip computer, terminate this configuration operation; If DONE effectively, then tests FPGA to tested FPGA trigger initialize, and sends configuration successful signal to processor of single chip computer, terminate this configuration operation in official hour.
As shown in Figure 4, be the refresh operation workflow diagram of SRAM type FPGA single particle effect test system of the present invention.When testing FPGA and receiving refresh operation order from processor of single chip computer, start the refresh operation to tested FPGA.First configuration control signal CS, WRITE of enable tested FPGA, when detecting configuration data transmitting counter and BUSY signal, send configuration data, until all configuration datas are sent completely by SelectMAP mouth to tested FPGA.After configuration data is sent completely, test FPGA sends Flushing success signal to processor of single chip computer, terminates this refresh operation.When refresh operation is used for trigger upset detection, when not changing trigger storing value, refreshes the configuration data of tested FPGA, guaranteeing that tested FPGA user logical link is communicated with; When detecting for locking single particle, prevent the working current of tested FPGA when there is not locking single particle excessive.
As shown in Figure 5, be the direct fault location operation element process flow diagram of SRAM type FPGA single particle effect test system of the present invention.When testing FPGA and receiving direct fault location operational order from processor of single chip computer, start and the direct fault location of tested FPGA is operated.First test FPGA sends synchronization character by the JTAG mouth of tested FPGA to tested FPGA, when detection failure injects counter and BUSY signal, to the reprovision data of tested FPGA transmitting portion reprovision data address and appropriate address, realize direct fault location by adopting the part reprovision of fault data to tested FPGA.After all reprovision data are sent completely, test FPGA sends direct fault location pass signal to processor of single chip computer, terminates the operation of this direct fault location.
As shown in Figure 6, for the single-particle inversion of SRAM type FPGA single particle effect test system of the present invention and function interrupt detecting operation element process flow diagram.When test FPGA from processor of single chip computer receive single-particle inversion and function interrupt detecting operational order time, start to interrupt detecting to the single-particle inversion of tested FPGA and function and operate.First test FPGA detects the DONE leg signal of tested FPGA, if DONE signal is effective, then judges that tested FPGA POR function does not occur and interrupts; If DONE signal is low level, then judge that tested FPGA POR function occurs and interrupts.After POR function interruption detection terminates, test FPGA sends synchronization character by the JTAG mouth of tested FPGA to tested FPGA, read and write the special function register of tested FPGA, whether generating function interrupts to judge JTAG mouth, then sends solution synchronization character and separates synchronous with tested FPGA.After JTAG mouth function interruption detection terminates, test FPGA sends synchronization character by the SelectMAP mouth of tested FPGA to tested FPGA, reads and writes the special function register of tested FPGA, and whether generating function interrupts to judge SelectMAP mouth.After SelectMAP mouth function interruption detection terminates, test FPGA sends configuration read-backward command by the SelectMAP mouth of tested FPGA to tested FPGA, when detecting configuration data retaking of a year or grade counter and BUSY signal, by SelectMAP mouth from tested FPGA retaking of a year or grade configuration data, until all configuration data retakings of a year or grade complete.In the process of retaking of a year or grade configuration data, test FPGA real-time comparison is carried out to retaking of a year or grade configuration data and original configuration data, statistical discrepancy figure place.If before retaking of a year or grade detects, tested FPGA has been detected and has occurred that POR function is interrupted or SelectMAP mouth function is interrupted, then the difference figure place of adding up can verify that tested FPGA has occurred that corresponding function is interrupted further; If before retaking of a year or grade detects, tested FPGA is undetected occurs that POR function is interrupted or SelectMAP mouth function is interrupted, then the difference figure place of adding up is the single-particle inversion number of tested FPGA configuration data.After configuration data single-particle inversion detects and terminates, test FPGA sends BRAM read-backward command by the SelectMAP mouth of tested FPGA to tested FPGA, when detecting BRAM data readback counter and BUSY signal, by SelectMAP mouth from tested FPGA retaking of a year or grade BRAM data, until all BRAM data readbacks complete.In the process of retaking of a year or grade BRAM data, test FPGA real-time comparison is carried out, statistical discrepancy figure place to retaking of a year or grade BRAM data and original BRAM data.If before retaking of a year or grade detects, tested FPGA has been detected and has occurred that POR function is interrupted or SelectMAP mouth function is interrupted, then the difference figure place of adding up can verify that tested FPGA has occurred that corresponding function is interrupted further; If before retaking of a year or grade detects, tested FPGA is undetected occurs that POR function is interrupted or SelectMAP mouth function is interrupted, then the difference figure place of adding up is the single-particle inversion number of tested FPGA BRAM data.
As shown in Figure 7, for the trigger upset of SRAM type FPGA single particle effect test system of the present invention detects operation element process flow diagram.When testing FPGA and receiving trigger upset detection operational order from processor of single chip computer, start and operation is detected to the trigger upset of tested FPGA.First test FPGA refreshes the configuration data of tested FPGA, the trigger value of the tested FPGA of retaking of a year or grade, and compares with institute initialize, and statistical discrepancy figure place, is trigger upset number.Test FPGA sends testing result to processor of single chip computer, terminates the upset of this trigger and detects operation.
When carrying out single particle effect and detecting, method is as follows:
(1) test specimen process
Device is Xilinx company 300,000 FPGAXQV300-4CB228.Before test, adopt " ceramic surrounding flat package FPGA device is opened cap fixture and opens cap method " to open cap to sample, open cap process not damage device inner structure.
(2) radiation source
Locking single particle detects radiation source and selects Lanzhou Chinese Academy of Sciences modern physics research institute HIRFL cyclotron, and particle is Bi, tests and carries out in vacuum environment.Cyclotron produce high energy particle in vacuum environment, exposure experiment sample.The LET value of test particle and range are in table 1.
Effective LET value of table 1 test particle
Single-particle inversion and function interrupt detecting radiation source selection China Atomic Energy Science Research Institute HI-13 swindletron, and particle is Cu, tests and carries out in vacuum environment.Cyclotron produce high energy particle in vacuum environment, exposure experiment sample.The LET value of test particle and range are in table 2.
Effective LET value of table 2 test particle
(3) locking single particle detects
1) send initialization command by outside, configuration data is delivered in storage unit;
2) after initialization terminates, send configuration order by externally to processor of single chip computer, start test FPGA and operation is configured to tested FPGA;
3) use radiation source to produce high energy particle and irradiate tested fpga chip surface;
4) configuration data of the tested FPGA of periodic refreshing, working current when preventing tested FPGA from locking single particle not occurring is excessive;
5) in whole experimentation, tested FPGA working current does not find to become suddenly large, exceedes detection threshold, judges that locking single particle does not occur tested FPGA.
(4) single event function interrupt, configuration store district, BRAM and trigger upset detect
1) send initialization command by outside, configuration data is delivered in storage unit;
2) after initialization terminates, send configuration order by externally to processor of single chip computer, start test FPGA and operation is configured to tested FPGA;
3) after configuration operation completes, send it back read command by externally to processor of single chip computer, what start test FPGA loops back read operation;
4) use radiation source to produce high energy particle and irradiate tested fpga chip surface;
5) test configuration address register and the DNOE pin that FPGA detects tested FPGA, judge whether tested FPGA single event function interrupt occurs, complete the single event function interrupt test of tested FPGA;
6) when confirming that single event function interrupt does not occur FPGA, the configuration data of the tested FPGA of test FPGA retaking of a year or grade, the corresponding positions of the original configuration data significance bit of the configuration data of retaking of a year or grade and storer stored carries out real-time comparison, add up configuration store district and BRAM upset sum respectively, and statistics is sent to processor of single chip computer.
7) circulation performs step (6) ~ (7), and interrupt or the interruption of SelectMAP mouth function until there is POR function, then high energy particle irradiates and terminates.If there is not single event function interrupt, high energy particle fluence reaches 9 × 10
4~ 10
5/ cm
2time irradiate terminate.
8) refresh the configuration data of tested FPGA, read user's trigger value of tested FPGA, compare with institute initialize, statistics upset sum, and statistics is sent to processor of single chip computer, complete trigger function interrupt test.Test findings is in table 3.
Table 3 single particle effect test experience result
The content be not described in detail in instructions of the present invention belongs to the known technology of professional and technical personnel in the field.
Claims (7)
1.SRAM type FPGA single particle effect test system, its feature comprises: processor of single chip computer, test FPGA, storage unit, RS232 interface and USB interface, wherein:
Processor of single chip computer: receive the configuration data and control command that transmit outside, and described configuration data and control command are delivered to test FPGA; According to external control order, arrange that test FPGA is configuration operation state, refresh operation state, direct fault location state, single-particle inversion and function interrupt detecting mode of operation and trigger overturns and detects mode of operation; Receive control command feedback signal and testing result from test FPGA, and externally export;
Test FPGA: carry out initialization to storage unit according to the control command that processor of single chip computer transmits, receives the configuration data that processor of single chip computer transmits, and deposits to storage unit, enter corresponding mode of operation according to the control command that processor of single chip computer transmits, described mode of operation comprises configuration operation state, refresh operation state, direct fault location state, single-particle inversion and function to interrupt detecting mode of operation and trigger and overturns and detect mode of operation, when configuration operation state, test FPGA reads configuration data from storage unit, is configured operation to tested FPGA, and to processor of single chip computer feedback configuration operating result, during refresh operation state, operation is configured to tested FPGA, and to processor of single chip computer feedback configuration operating result, during direct fault location state, after test FPGA receives the direct fault location operational order of processor of single chip computer, receive fault data information via USB interface from host computer, by the series arrangement mouth of tested FPGA, part reprovision is carried out to tested FPGA, in the configuration bit Write fault data of assigned address, described part reprovision is only modified for the segment of FPGA configuration file, thus complete and carry out direct fault location to tested FPGA, when single-particle inversion and function interrupt detecting mode of operation, from the configuration data that tested FPGA retaking of a year or grade is current, by carrying out single-particle inversion detection with comparing of original configuration data, single event function interrupt detection is carried out by reading and writing tested FPGA configuration address register and detecting DONE pin, when confirmation FPGA does not have to have no progeny in generating function, synch command and configuration data read-backward command is sent successively to tested FPGA, and detect the BUSY pin of tested FPGA, when BUSY pin is invalid, the corresponding positions of the original configuration data of the significance bit of the configuration data of retaking of a year or grade and cell stores is carried out real-time comparison, statistics upset sum, and statistics is sent to processor of single chip computer, when trigger upset detects mode of operation, first test FPGA refreshes the configuration data of tested FPGA, guarantee that tested FPGA user logical link is communicated with, then user's trigger value of tested FPGA is read, compare with institute initialize, statistics upset sum, and statistics is sent to processor of single chip computer,
Storage unit: for storing the configuration data that outside is transmitted;
RS232 interface: complete host computer and send control command to processor of single chip computer, and receive control command feedback or testing result from single-chip microcomputer;
USB interface: complete host computer and send tested FPGA original configuration data to test FPGA.
2. SRAM type FPGA single particle effect test system according to claim 1, is characterized in that: the course of work of described processor of single chip computer is:
First processor of single chip computer carries out initialization operation, then enters into cycling; During cycling, processor of single chip computer cycle detection RS232 interface signal inputs, and determines that next step needs the operation carried out; Interrupt detecting operational order or trigger and overturn if processor of single chip computer receives configuration operation order, refresh operation order, direct fault location order, single-particle inversion and function from RS232 interface and detect operational order, then the corresponding command is sent to test FPGA, after FPGA to be tested completes corresponding operating, control command feedback signal or testing result is received from test FPGA, externally transmit through RS232 interface, processor of single chip computer completes all after dates of a command operation, reenter cycling, wait for Next Command.
3. SRAM type FPGA single particle effect test system according to claim 1, is characterized in that: the configuration operation process of described test FPGA is:
After receiving the configuration operation order of processor of single chip computer, the configuration of enable tested FPGA controls pin CS, WRITE and PROGRAM, and ensure that PROGRAM signal keeps low level at least 300nS, then the INIT pin that tested FPGA exports is detected, read configuration data when INIT pin is effective from the first address of storage unit and write tested FPGA, detect the BUSY pin of tested FPGA simultaneously, when BUSY pin is invalid, represent that these address configuration data have been written into tested FPGA, access unit address is added one, repeat write operation, until the whole configuration datas in storage unit are sent, then detect the DONE pin that tested FPGA exports, when DONE pin is effective, represent the configuration successful of tested FPGA, after tested FPGA configuration successful, test FPGA starts to carry out initialization operation to user's trigger of tested FPGA, and after initialization operation completes, whole configuration operation all terminates.
4. SRAM type FPGA single particle effect test system according to claim 1, is characterized in that: the refresh operations of described test FPGA is:
After receiving the refresh operation order of processor of single chip computer, read configuration data from the first address of storage unit and write tested FPGA, detect the BUSY pin of tested FPGA simultaneously, when BUSY pin is invalid, represent that these address configuration data have been written into tested FPGA, access unit address is added one, repeats write operation, until the whole configuration datas in storage unit are sent.
5.SRAM type FPGA single particle effect test method, is characterized in that comprising direct fault location; Single-particle inversion detects, and comprises configuration store district, BRAM and trigger upset and detects; Single event function interrupt detects; Locking single particle detects;
Wherein said fault filling method step is as follows:
The position of (a) host computer determination direct fault location configuration bit, and fault location information is sent to processor of single chip computer;
B fault location information is sent to test FPGA by () processor of single chip computer;
C FPGA is according to the positional information received in () test, by the series arrangement mouth of tested FPGA, carry out part reprovision to tested FPGA, and the configuration data of change corresponding configuration position, realizes direct fault location;
Described single-particle inversion detects and single event function interrupt combining data detection completes, and performing step is as follows:
(1) selective radiation source;
(2) send initialization command by outside, configuration data is delivered in storage unit, complete initialization;
(3) after initialization terminates, send configuration order by externally to processor of single chip computer, start test FPGA and operation is configured to tested FPGA;
(4) after configuration operation completes, send sense command by externally to processor of single chip computer, start the cycle detection operation of test FPGA;
(5) use radiation source to produce high energy particle and irradiate tested fpga chip surface;
(6) test configuration address register and the DONE pin that FPGA detects tested FPGA, judge whether tested FPGA single event function interrupt occurs, complete the single event function interrupt test of tested FPGA;
(7) when confirming that single event function interrupt does not occur FPGA, the configuration data of the tested FPGA of test FPGA retaking of a year or grade, the corresponding positions of the original configuration data of the significance bit of the configuration data of retaking of a year or grade and cell stores is carried out real-time comparison, add up configuration store district and BRAM upset sum respectively, and statistics is sent to processor of single chip computer;
(8) circulation performs step (6) ~ (7), terminates until high energy particle irradiates;
(9) refresh the configuration data of tested FPGA, read user's trigger value of tested FPGA, compare with institute initialize, statistics upset sum, and statistics is sent to processor of single chip computer, complete trigger function interrupt test;
Described locking single particle detection method performing step is as follows:
(A) selective radiation source;
(B) send initialization command by outside, configuration data is delivered in storage unit, complete initialization;
(C) after initialization terminates, send configuration order by externally to processor of single chip computer, start test FPGA and operation is configured to tested FPGA;
(D) use radiation source to produce high energy particle and irradiate tested fpga chip surface;
(E) configuration data of the tested FPGA of periodic refreshing, working current when preventing tested FPGA from locking single particle not occurring is excessive;
(F) if find, tested FPGA working current becomes suddenly large, exceedes detection threshold, and after refresh configuration data, electric current is substantially unchanged, then judge that locking single particle occurs tested FPGA.
6. SRAM type FPGA single particle effect test method according to claim 5, it is characterized in that: the radiation source in described step (1), (A) is cyclotron or tandem accelerator, its high energy particle range in silicon produced is greater than 30 μm, and LET value is greater than 30MeV.cm
2/ mg.
7. SRAM type FPGA single particle effect test method according to claim 5, it is characterized in that: irradiating the condition terminated in described step (8) is: single event function interrupt occurs tested FPGA, or the fluence of radiation source irradiation particle reaches 9 × 10
4~ 10
5/ cm
2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110214108.7A CN102332307B (en) | 2011-07-28 | 2011-07-28 | SRAM type FPGA single particle effect test system and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110214108.7A CN102332307B (en) | 2011-07-28 | 2011-07-28 | SRAM type FPGA single particle effect test system and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102332307A CN102332307A (en) | 2012-01-25 |
| CN102332307B true CN102332307B (en) | 2015-08-05 |
Family
ID=45484048
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110214108.7A Active CN102332307B (en) | 2011-07-28 | 2011-07-28 | SRAM type FPGA single particle effect test system and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102332307B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105185413A (en) * | 2015-09-24 | 2015-12-23 | 中国航天科技集团公司第九研究院第七七一研究所 | Automatic verification platform and method for on-chip memory management unit fault-tolerant structure |
Families Citing this family (44)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102636744B (en) * | 2012-04-24 | 2014-06-11 | 中国科学院空间科学与应用研究中心 | Device and method for detecting relationship between single event effects and time sequence characteristics of FPGA (Field Programmable Gate Array) |
| CN103529380B (en) * | 2012-07-06 | 2016-08-03 | 北京圣涛平试验工程技术研究院有限责任公司 | The monitoring system and method for SRAM type FPGA single particle functional interruption |
| CN103792487B (en) * | 2012-10-31 | 2016-08-17 | 中国科学院电子学研究所 | A kind of apparatus and method testing FPGA |
| CN103837839B (en) * | 2012-11-23 | 2016-07-06 | 北京圣涛平试验工程技术研究院有限责任公司 | Secondary power supply single particle effect test method |
| CN103063961B (en) * | 2012-12-28 | 2016-04-06 | 中国科学院微电子研究所 | Single event effect testing device and system |
| CN103033524B (en) * | 2012-12-31 | 2015-03-04 | 中国科学院微电子研究所 | Single-particle radiation effect detection method |
| EP2765528B1 (en) | 2013-02-11 | 2018-11-14 | dSPACE digital signal processing and control engineering GmbH | Unrestricted access to signal values of an FPGA during runtime |
| JP6436916B2 (en) | 2013-02-11 | 2018-12-12 | ディスペース デジタル シグナル プロセッシング アンド コントロール エンジニアリング ゲゼルシャフト ミット ベシュレンクテル ハフツングｄｓｐａｃｅ ｄｉｇｉｔａｌ ｓｉｇｎａｌ ｐｒｏｃｅｓｓｉｎｇ ａｎｄ ｃｏｎｔｒｏｌ ｅｎｇｉｎｅｅｒｉｎｇ ＧｍｂＨ | Method for changing signal value of FPGA at runtime, data processing apparatus, computer program and digital storage medium for implementing the method |
| CN103293468A (en) * | 2013-04-09 | 2013-09-11 | 北京时代民芯科技有限公司 | Fault injection system and fault injection method facilitating device fault sensitivity test |
| CN103165192B (en) * | 2013-04-16 | 2014-09-24 | 西北核技术研究所 | SRAM (Static Random Access Memory) single event latch-up effect testing system and method |
| CN103323715B (en) * | 2013-06-20 | 2015-08-05 | 中国空间技术研究院 | Particle fluence rate system of selection in large scale integrated circuit accelerator single particle experiment |
| CN103631738B (en) * | 2013-08-15 | 2016-08-10 | 中国科学院电子学研究所 | A kind of off-chip configuration and readback FPGA device |
| CN103577643B (en) * | 2013-11-06 | 2016-06-01 | 中国空间技术研究院 | A kind of SRAM type FPGA single particle upset effect emulation method |
| CN103796009B (en) * | 2014-01-14 | 2016-01-20 | 北京空间机电研究所 | A kind of FPGA quality diagnosis test macro |
| CN103809109B (en) * | 2014-02-26 | 2016-08-24 | 工业和信息化部电子第五研究所 | Integrated circuit single particle effect detection device and system |
| CN104007427B (en) * | 2014-05-20 | 2017-01-25 | 上海微小卫星工程中心 | Mean free error time assessment method and system based on irradiation test satellite-borne responder |
| CN104200846B (en) * | 2014-07-23 | 2017-05-10 | 北京空间机电研究所 | Embedded-type PROM test system and achieving method |
| CN104181421B (en) * | 2014-08-22 | 2017-03-08 | 中国科学院空间科学与应用研究中心 | FPGA single particle effect dynamic fault test device and method |
| CN105590651A (en) * | 2014-10-22 | 2016-05-18 | 北京圣涛平试验工程技术研究院有限责任公司 | DRAM (dynamic random access memory) neutron single event effect test method |
| CN105589780A (en) * | 2014-10-22 | 2016-05-18 | 北京圣涛平试验工程技术研究院有限责任公司 | Neutron single event effect testing method of CPU |
| CN105590653A (en) * | 2014-10-22 | 2016-05-18 | 北京圣涛平试验工程技术研究院有限责任公司 | Neutron single event effect testing method of a SRAM type FPGA |
| CN104483622B (en) * | 2014-11-27 | 2017-08-25 | 北京时代民芯科技有限公司 | A kind of single particle radiation test system and method based on jtag interface |
| CN104698314B (en) * | 2015-03-05 | 2018-01-02 | 中国空间技术研究院 | A kind of SRAM type FPGA device level automatic test platform and its method of testing |
| CN104851467B (en) * | 2015-05-20 | 2017-12-22 | 中国空间技术研究院 | A kind of aerospace band EDAC function SRAM memory function verification methods |
| CN105068969B (en) * | 2015-07-17 | 2018-02-09 | 西安空间无线电技术研究所 | Single particle effect guard system and method for digital signal processing platform framework |
| CN105548866A (en) * | 2015-12-08 | 2016-05-04 | 中国科学院电子学研究所 | SRAM type FPGA test method based on irradiation test environment simulation |
| CN105717443A (en) * | 2016-02-17 | 2016-06-29 | 北京时代民芯科技有限公司 | SRAM type FPGA trigger single-event upset resistance performance assessment system and method |
| CN105895163B (en) * | 2016-03-28 | 2018-09-28 | 工业和信息化部电子第五研究所 | Single particle effect detection method based on mirror back-up and system |
| CN108733552B (en) * | 2017-04-18 | 2020-12-22 | 北京大学 | FPGA remote debugging system and remote debugging method |
| CN107356864B (en) * | 2017-06-30 | 2019-07-16 | 西安电子科技大学 | PLL circuit anti-radiation performance appraisal procedure |
| CN107452426B (en) * | 2017-07-24 | 2020-04-07 | 中国空间技术研究院 | Detection circuit and detection method for storage element in FPGA chip |
| CN107678896B (en) * | 2017-09-13 | 2020-11-27 | 湖南斯北图科技有限公司 | SRAM (static random Access memory) type FPGA (field programmable Gate array) upset fault injector and fault injection method |
| CN107918097B (en) * | 2017-10-20 | 2020-03-24 | 西安空间无线电技术研究所 | Adaptive fitting method for system function interrupt section capable of realizing variable LET value |
| CN108023587B (en) * | 2017-11-07 | 2022-01-11 | 北京时代民芯科技有限公司 | Single-particle reinforced clock control circuit and control method in programmable configuration logic block |
| CN108257646A (en) * | 2018-03-29 | 2018-07-06 | 榆林学院 | SRAM read-write indirectly testing device and methods based on LabVIEW |
| CN109065087A (en) * | 2018-08-15 | 2018-12-21 | 孙雷 | A kind of device and method for the clock sources single-particle dynamic overturning detecting FPGA |
| CN109189624B (en) * | 2018-09-11 | 2022-02-01 | 西安微电子技术研究所 | Mass information processor single particle test implementation method and single particle test board |
| CN110444243A (en) * | 2019-07-31 | 2019-11-12 | 至誉科技（武汉）有限公司 | Store test method, system and the storage medium of equipment read error error correcting capability |
| CN110568347B (en) * | 2019-08-07 | 2021-11-09 | 北京空间飞行器总体设计部 | Rapid estimation method for single-particle function interruption rate of satellite-borne FPGA |
| CN112433894B (en) * | 2020-10-27 | 2022-09-13 | 深圳市紫光同创电子有限公司 | FPGA test method and test system |
| CN112447201B (en) * | 2020-10-29 | 2024-09-20 | 中国空间技术研究院 | System-level space single particle protection method suitable for SRAM (static random Access memory) type FPGA (field programmable Gate array) product |
| CN112988431B (en) * | 2021-03-18 | 2022-07-08 | 中国人民解放军国防科技大学 | Reliability evaluation method and system for different exceptions of SRAM (static random Access memory) type FPGA (field programmable Gate array) |
| CN113376514B (en) * | 2021-06-09 | 2022-04-15 | 深圳米飞泰克科技股份有限公司 | FPGA chip testing method, device, system and storage medium |
| CN115641903B (en) * | 2022-10-19 | 2024-08-09 | 深圳市紫光同创电子有限公司 | FPGA storage unit failure analysis method and device, electronic equipment and storage medium |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102135920A (en) * | 2011-01-17 | 2011-07-27 | 中国航天科技集团公司第九研究院第七七一研究所 | Fault injection system for embedded spaceborne computer and injection method thereof |
-
2011
- 2011-07-28 CN CN201110214108.7A patent/CN102332307B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102135920A (en) * | 2011-01-17 | 2011-07-27 | 中国航天科技集团公司第九研究院第七七一研究所 | Fault injection system for embedded spaceborne computer and injection method thereof |
Non-Patent Citations (1)
| Title |
|---|
| SRAM FPGA电离辐射效应试验研究;于庆奎;《航天器环境工程》;20090630;第26卷(第3期);229-231 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105185413A (en) * | 2015-09-24 | 2015-12-23 | 中国航天科技集团公司第九研究院第七七一研究所 | Automatic verification platform and method for on-chip memory management unit fault-tolerant structure |
| CN105185413B (en) * | 2015-09-24 | 2018-06-22 | 中国航天科技集团公司第九研究院第七七一研究所 | For the automatic verification platform and method of on piece MMU memory management unit fault-tolerant architecture |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102332307A (en) | 2012-01-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102332307B (en) | SRAM type FPGA single particle effect test system and method | |
| CN102332310B (en) | FPGA (Field Programmable Gate Array)-based single event effect test system for NAND FLASH device | |
| CN102332311B (en) | FPGA (Field Programmable Gate Array)-based single event effect test method for NAND FLASH device | |
| CN105760250B (en) | A kind of single-particle reinforcing FPGA configuration circuit with code stream error correction and detection function | |
| CN108710551B (en) | SPARC processor-based single event upset fault injection test method and system | |
| CN103325411B (en) | A kind of anti-single particle overturn hardened system and method thereof for FPGA | |
| CN103150228B (en) | Synthesizable pseudorandom verification method and device for high-speed buffer memory | |
| CN105185413B (en) | For the automatic verification platform and method of on piece MMU memory management unit fault-tolerant architecture | |
| CN106484581B (en) | It may be programmed SOC device single-particle inversion detection system and method under space radiation environment | |
| CN102135920B (en) | Fault injection system for embedded spaceborne computer and injection method thereof | |
| CN103021469A (en) | Universal single event effect detecting method of memory circuit | |
| CN101556551B (en) | Hardware acquisition system and method for equipment failure log | |
| CN107741559B (en) | Single event upset test system and method under space radiation environment | |
| CN108226748A (en) | For the single particle effect test method of SoC systems on chip | |
| CN105548866A (en) | SRAM type FPGA test method based on irradiation test environment simulation | |
| CN109491821A (en) | Primary particle inversion resistant hardened system and method | |
| CN103840823A (en) | Astronavigation FPGA universal refresh circuit based on JTAG interface and achieving method thereof | |
| CN112710913A (en) | Two-class multi-type COTS device single event soft error testing hardware system | |
| CN109558649A (en) | A kind of register single particle effect analog simulation method towards aerospace chip | |
| Shao et al. | Formal analysis of repairable phased-mission systems with common cause failures | |
| CN111444662A (en) | High-speed DDR single event effect evaluation system and method based on FPGA | |
| CN202443461U (en) | Single-particle error injection simulation test system | |
| CN106653091A (en) | Method for evaluating anti-radiation capability of chip, apparatus and chip | |
| CN103840822A (en) | Astronavigation FPGA universal refresh circuit based on SELECTMAP and achieving method thereof | |
| CN110007738A (en) | Operating status reconstructing method after anti-transient ionizing radiation suitable for sensitive circuit resets |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |