CN102135920B - Fault injection system for embedded spaceborne computer and injection method thereof - Google Patents
Fault injection system for embedded spaceborne computer and injection method thereof Download PDFInfo
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Abstract
The invention discloses a fault injection system for an embedded spaceborne computer and an injection method thereof, which are mainly used for software evaluation of the operation system of the spaceborne computer. The fault injection system for the embedded spaceborne computer comprises a Digital Signal Processor (DSP), a Random Access Memory (RAM), a FLASH, a Joint Test Action Group (JTAG) controller, and one or more Field Programmable Gate Arrays (FPGAs) (one of which is a fault injection FPGA) and an interface circuit, wherein the DSP processor and the fault injection FPGA are provided with boundary scanning units; the Test Compatibility Kit (TCK) and the Time-Multiplexed Switching (TMS) signal terminals of a chip are connected in parallel; the Total Domestic Output (TDO) signal terminal of a front-stage apparatus and the Transport Driver Interface (TDI) signal terminal of a rear-stage apparatus are connected in series to form a daisy chain. The device is simple and is capable of shortening evaluation time and reducing evaluation cost; a signal level is directly controlled in the computer without special external instruments; signals needing to control influence can be flexibly selected to have a relatively large fault coverage rate; therefore, the reliability and the fault-tolerant capability of the embedded spaceborne computer can be more comprehensively verified.
Description
Technical field:
The present invention is mainly used in the software fault-tolerant mechanism evaluation and test to the embedded satellite borne computer, is applicable to the embedded satellite borne computer with boundary scan interface, fpga chip.
Background technology:
Survey the development of cause along with Chinese Space, people are more and more higher to the requirement of onboard system reliability.In the NASA statistics of 1996, the satellite failure that single particle effect causes 80% of the radiation effect fault sum that takes up space.Fault-tolerant technique is to improve the important method of board computer system reliability, is the correctness of assurance fault-tolerant design and the efficient of fault tolerant mechanism, needs to adopt auxiliary technology that tolerant system is verified.Fault-tolerant checking mainly contains three kinds of methods: analytical model method, on-the-spot error data analysis method and fault filling method.Compare with front two kinds of methods, the Failure Injection Technique method does not need accurate systematic parameter, does not need to wait for for a long time data acquisition, has the advantages such as convenient, fast, real-time.Failure Injection Technique is a kind of effective ways of evaluation and test spaceborne computer fault tolerant mechanism.Monitor and analyze by the process that injection fault Post-acceleration system is broken down and lost efficacy, can obtain the evaluation result to goal systems reliability and failure tolerance.
Boundary-scan test technology is developing rapidly along with extensive, VLSI (very large scale integrated circuit), under the problems such as limit test pin that the mounting technology in the face of the difficulty of the design of complicated circuit, justifying test and surface brings, in order to improve the testability of circuit and system, combined testing action group (JTAG) has proposed a kind of new circuit board detection method---boundary scan testing in 1987, and admitted by IEEE (International Standards Organization) in nineteen ninety, formed the IEEE1149.1 standard, also referred to as the JTAG standard.This technology replaces traditional " physical probe " to improve the measurability of circuit and system with brand-new " virtual probe ".Its ultimate principle is exactly by increasing boundary scan cell (BSC) between the input and output pin of device and internal logic circuit, realizing Real-Time Monitoring and control to the chip pin state.The JTAG standard definition universal serial bus of 5 lines, with regard to addressable boundary scan register unit, can reach the purpose of test chip kernel and peripheral circuit by these 5 p-wires.Support the boundary-scan architecture of the IC chip of JTAG standard to be formed by boundary scan register (BSR), test access port (TAP), access port TAP controller, order register (IR), bypass register and some background registers etc.TAP is the test access port that is connected with 5 line serial p-wires, and all operations of JTAG standard definition is all controlled by these 5 p-wires.These 5 p-wires are respectively: clock input line (TCK), and model selection input line (TMS), Data In-Line (TDI), DOL Data Output Line (TDO), input line (TRST) in addition optionally resets.The JTAG stereotyped command of carrying out this device appointment just can provide the observation pin input that is independent of the device inside function logic and the function of controlling pin output.
At present, realize that the method that fault is injected has hardware fault injection, software fault injection and emulation fault to inject 3 kinds.It is by utilizing certain standard hardware descriptive language (as VHDL commonly used) to set up hardware simulation model for test macro, then injecting in the inner fault of inserting of model the injection that fault is realized in the unit that the emulation fault is injected.Its advantage is without any need for special hardware, can accurately monitor the fault of injecting, and deficiency is that the development amount is large, need to set up detailed realistic model.Typically the fault implantation tool based on simulation has VER IFY, MEFIS2TO-C etc.Software fault injects according to certain fault model, comes the generation of analog hardware fault by the register value of modifying target Installed System Memory unit or processor inside.Its major advantage is to need not complicated experimental provision, realizes that cost is low, can inject fault etc. when compilation phase and program operation.Main deficiency be to target program working time, taking up room etc. impacts.It is directly fault to be injected into the hardware of goal systems with physical means that hardware fault is injected, and by the effect of additional firmware to goal systems, the normal hardware environment of goal systems is affected, thereby produces fault.The research that present hard-wired fault is injected concentrates on the chip pin level mostly, and employing applies the means such as voltage, heavy-particle radiation or electromagnetic interference (EMI) fault is introduced goal systems to the pin level.The major advantage of the method be the fault injected near actual conditions, hardware fault that can simulate reality need not to develop specially the fault injection model in experimentation.Its main deficiency is that experimental provision is complicated, expense is high, to the easy injury of goal systems hardware etc.Although there is certain deficiency in hard-wired fault filling method, with respect to the importance of space spaceborne computer reliability, hardware fault is injected and is remained the necessary means that the spaceborne computer tolerant system is verified.
Summary of the invention:
The present invention is used for solving the reliability evaluating of embedded satellite borne computer, and a kind of simple, feasible fault injection device is provided.
the object of the invention is to overcome the shortcoming of above-mentioned prior art, a kind of embedded satellite-borne computer failure injected system is provided, comprise dsp processor, RAM, FLASH, jtag controller, one or more FPGA (one of them injects FPGA for fault) and interface circuit, described dsp processor and fault are injected FPGA all with boundary scan cell, and fault is injected the TCK of fpga chip, the TCK of tms signal end and dsp processor, the tms signal end is corresponding in parallel and externally draw, (the TDI signal end of the TDO of prime device and rear class device is interconnected and dsp processor is connected a fpga chip minute front and back stages device connection with fault, the TDO of the TDI of prime device and rear class device directly externally draws), form daisy chain, described boundary scan cell is arranged between digital circuit chip pin and chip internal logic, realizes the serial of chip pin state is set and read.
The ground test computing machine is connected on a jtag controller by parallel interface cable, TCK on jtag controller, TDI, TMS, four p-wires of TDO connect the jtag interface on the spaceborne computer module, on ground test, operation troubles is injected software by the jtag interface on these four p-wires connection spaceborne computer modules, jtag interface is controlled the boundary scan link of spaceborne computer inside modules chip, realize sending command functions and data, the hardware fault of injecting single-particle inversion for the spaceborne computer module, the fault-tolerant ability of observation spaceborne computer to fault.
Spaceborne computer consists of:
The embedded satellite-borne computer module is comprised of DSP (digital signal processing) processor, RAM (random access memory), FLASH (nonvolatile memory), one or more FPGA and interface circuit.Wherein DSP, RAM and FLASH consist of the minimum system of spaceborne computer, and the functions such as total line traffic control and Digital Logic realization are completed in the scheduling of mainly finishing the work, parameter clearing, most according to functions such as processing in FPGA.Minimum system is connected by data bus, address bus and control bus with FPGA.FPGA is connected with interface circuit by control signal.Its system construction drawing as shown in Figure 1.Due to the processor selected and FPGA in design all with boundary-scan function, in order to realize the fault function of injecting, we will be in parallel with processor, the TCK of fpga chip, the tms signal end of boundary-scan architecture, and the TDO of prime device and the TDI signal end of rear class device are connected, form daisy chain, as shown in Figure 2.
In the process of embedded satellite-borne computer reliability evaluation and test, need the virtual space single-particle on the impact of embedded satellite-borne computer reliability, inject the failure tolerance of fault observation embedded satellite borne computer.The high-low level that the present invention utilizes the jtag boundary scan chain to control the FPGA pin affects coherent signal, reach the purpose that fault is injected, and the bus signals, control signal and the status signal that surpass 90% in the embedded satellite-borne computer module have been introduced in FPGA, injected so can carry out fault to the signal in the embedded satellite-borne computer module by the scan chain circuit of FPGA.Embedded satellite-borne computer module technical solution of the present invention for this type of is, utilize the boundary scan link directly or indirectly to affect each signal of chip, thereby realize the injection of the various faults of embedded satellite borne computer, utilize the realization of boundary scan link to the fault effects of embedded satellite-borne computer-internal signal.
Fault Insertion Equipment consists of:
Embedded satellite-borne computer failure injected system is comprised of the parallel port jtag controller that universal grounding fault test computing machine, fault test software, company of U.S. match SEL make, and institute's evaluating object is the embedded satellite-borne computer module.
Fig. 3 is embedded satellite-borne computer module fault injection device schematic diagram.Fault test computing machine in ground is connected to by parallel interface cable on the jtag controller of a company of U.S. match SEL manufacturing, and the TCK on jtag controller, TDI, TMS, four fault test lines of TDO connect the jtag interface on the embedded satellite-borne computer modules.
The fault injecting principle:
The Fault Insertion Equipment of this design is to have utilized boundary scan technique to realize.The main thought of boundary scan mechanism is: by between digital circuit chip pin and chip internal logic, namely increase boundary scan cell on the border of chip, realize the serial of chip pin state is set and read.The boundary scan cell of shift register and latch is together in series, consist of one can serial-shift boundary scan chain.This chain is completed a series of action, as shown in Figure 4 under the control of TAP (Test Access Port, test access port) controller.
Its each IO pin of chip with boundary-scan architecture has a boundary scan register, at these boundary scan register serial links of chip internal, its state is controlled by the TAP controller, and TAP controller standard interface signal has: TMS, TCK, TDI and TDO.The workflow of TAP controller inside is controlled by 16 state machines, and the migration of state is to complete at the level of the negative edge sampling TMS of TCK.By the residing state of state machine, in the data serial immigration boundary scan register with TDI, can arrange and read each IO mouth thus.
The present invention compared to the prior art beneficial effect is:
(1) research of traditional hard-wired fault injection concentrates on the chip pin level mostly, and employing applies the means such as voltage, heavy-particle radiation or electromagnetic interference (EMI) fault is introduced goal systems to the pin level.The test battery device needs a large amount of high-end sci-tech product devices like this, purchases simultaneously these devices and incurs great expense.Compare traditional hard-wired fault and inject means, apparatus of the present invention are simple, only need the parallel port jtag controller of a company of U.S. match SEL manufacturing, general ground-based computer system and corresponding software.Complete by the four-way control bus level of embedded satellite-borne computer-internal fpga chip pin is controlled, reach the purpose that affects corresponding signal, the embedded satellite borne computer is caused fault.
(2) replace the Fault Insertion Equipments such as traditional, expensive heavy-particle radiation device, calutron, solve reliability and the fault-tolerance evaluation and test of embedded satellite borne computer.The cost of this device input is only the very little part of traditional instrument simultaneously, simplify the set-up procedure that fault is injected, can inject easily various single-particle faults for program in the development phase, saved the evaluation and test time, reduce the evaluation and test cost, shorten emerging the time of highly reliable embedded satellite borne computer.
(3) replace tradition and directly fault is injected in the hardware of goal systems with physical means, the normal hardware environment of goal systems is affected, thereby produce fault, simultaneously to the easy injury of the hardware of goal systems.This device is a kind of device that immediately injects fault in the embedded satellite borne computer, need not external instrumentation, directly in device inside control effect signal level, can make the embedded satellite borne computer carry out reliability evaluating under the condition of work of reality.Simultaneous faults can recover after injecting at any time, can not cause the hardware damage to goal systems.
(4) this device connects simple, be not subjected to extraneous physics environmental limit, by software, trigger condition is set on PC, can choose flexibly the pin and the signal that need control effect, affect inner a plurality of signal by selection, have larger fault coverage, thereby more fully verify reliability and the fault freedom of embedded satellite borne computer.
Description of drawings:
Fig. 1 is embedded satellite-borne computer system theory diagram of the present invention;
Fig. 2 is JTAG interconnection schematic diagram of the present invention;
Fig. 3 is embedded satellite-borne computer failure injected system device schematic diagram of the present invention;
Fig. 4 is boundary-scan architecture schematic diagram of the present invention.
Embodiment:
Below in conjunction with accompanying drawing, the present invention is described in further detail:
Referring to Fig. 1-4, key point of the present invention is to complete by the four-way control bus level of embedded satellite-borne computer-internal fpga chip pin is controlled, reach the purpose that affects corresponding signal, the embedded satellite borne computer is caused fault, and then reliability and the fault freedom of checking embedded satellite borne computer.
1. Fault Insertion Equipment hardware connects
The ground test computing machine is connected on the jtag controller of a company of U.S. match SEL manufacturing by parallel interface cable, TCK on jtag controller, TDI, TMS, four p-wires of TDO connect the jtag interface on the spaceborne computer module, on ground test, operation troubles is injected software by the JTAG mouth on these four p-wires connection spaceborne computer modules, it controls the boundary scan link of spaceborne computer inside modules chip, can realize sending command functions and data, inject the hardware fault of single-particle inversion for the spaceborne computer module.The fault-tolerant ability of observation spaceborne computer to fault.
2. fault is injected the software realization
According to TAP controller state machine workflow, it is following five combination of functions that fault is injected flow scheme design, and fault is injected software and called the fault function of injecting of completing appointment on these five functional blocks bases.
1. advance the command status function
No matter controller is in any state, and TMS is in into the director data state after putting (1111101100).
2. advance instruction functions
Send director data from TDI to controller, be sent completely rear TMS and put 11, instruction comes into force.
3. advance the data mode function
No matter controller is in any state, and TMS is in BS data displaced condition after putting (111110100)
4. advance data function
Move into to controller from TDI and set in advance BS cell value data corresponding to pin, N BS value serial moved into, be sent completely rear TMS and put 11, data come into force, and control the high-low level of the corresponding pin of FPGA.
Generate corresponding scale-of-two serial code stream in order to superior function, read by driving function the signal sequence that serial code realizes jtag interface TMS, TDI, TDO port under the tck clock signal.At the rising edge of TCK, the TMS port is put when several, and TDI keeps low level.At the rising edge of TCK, when sending data by the TDI port, the TMS port keeps low level.At the negative edge of TCK, during by TDO port receive data, the TMS port keeps low level.
The flow process that certain pin high-low level is set is as follows:
1. the command status function is advanced in operation, makes the TAP controller be in the instruction shift state
2. instruction functions is advanced in operation, and serial moves into EXTEST (outer test) instruction
3. the data mode function is advanced in operation, makes the TAP controller be in the data displaced condition
Data function is advanced in operation, sets in advance BS cell value corresponding to pin, and N BS value serial moved into, and comes into force after completing, and controls the high-low level of the corresponding pin of BS.
Above content is in conjunction with concrete preferred implementation further description made for the present invention; can not assert that the specific embodiment of the present invention only limits to this; for the general technical staff of the technical field of the invention; without departing from the inventive concept of the premise; can also make some simple deduction or replace, all should be considered as belonging to the present invention and determine scope of patent protection by claims of submitting to.
Claims (4)
1. embedded satellite-borne computer failure injected system, comprise dsp processor, RAM, FLASH, one or more FPGA and interface circuit, and one of them injects FPGA for fault a plurality of FPGA; It is characterized in that: described dsp processor and fault are injected FPGA all with boundary scan cell, the TCK of dsp processor, tms signal end and fault are injected the corresponding parallel connection of TCK, tms signal end of fpga chip, and the TDO of prime device and the TDI signal end of rear class device are connected, form daisy chain; The boundary scan cell of described dsp processor is arranged between the pin and dsp chip internal logic of dsp processor, the boundary scan cell that described fault is injected FPGA is arranged between the pin and fpga chip internal logic of fault injection FPGA, realizes the serial of chip pin state is set and read.
2. embedded satellite-borne computer failure injected system as claimed in claim 1, it is characterized in that: described dsp processor and fault are injected FPGA all with boundary scan cell, and fault is injected the corresponding parallel connection of TCK, tms signal end of TCK, tms signal end and the dsp processor of fpga chip and is externally drawn, connect and dsp processor is connected fpga chip minute front and back stages device with fault, form daisy chain; The boundary scan cell of described dsp processor is arranged between the pin and dsp chip internal logic of dsp processor, the boundary scan cell that described fault is injected FPGA is arranged between the pin and fpga chip internal logic of fault injection FPGA, realizes the serial of chip pin state is set and read; The signal of all possible breakdowns of embedded satellite-borne computer failure injected system is all received on the pin of fault injection FPGA in addition, injects FPGA by fault all possible fault is injected.
3. the fault filling method of an embedded satellite-borne computer failure injected system as claimed in claim 2, it is characterized in that: dsp processor is connected the TDI signal end series connection that fpga chip minute front and back stages device connection refers to TDO and the rear class device of prime device with fault, the TDO of the TDI of prime device and rear class device directly externally draws.
4. the fault filling method of embedded satellite-borne computer failure injected system as claimed in claim 3, it is characterized in that: the ground test computing machine is connected on a jtag controller by parallel interface cable, TCK on jtag controller, TDI, TMS, four p-wires of TDO connect the jtag interface on spaceborne computer, on ground test, operation troubles is injected software by the jtag interface on these four p-wires connection spaceborne computers, jtag interface is controlled the boundary scan link of spaceborne computer inside chip, realize sending command functions and data, inject the hardware fault of single-particle inversion to spaceborne computer, the fault-tolerant ability of observation spaceborne computer to fault.
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| CN102332307B (en) * | 2011-07-28 | 2015-08-05 | 中国空间技术研究院 | SRAM type FPGA single particle effect test system and method |
| CN102520629B (en) * | 2011-11-08 | 2013-11-13 | 北京航空航天大学 | Method for carrying out fault injection on two-path signal lines simultaneously |
| CN102998614B (en) * | 2012-12-14 | 2014-08-06 | 中船重工（武汉）凌久电子有限责任公司 | System capable of achieving digital signal processor (DSP) single-plate or multi-plate joint test action group (JTAG) debugging and debugging method |
| CN103246771B (en) * | 2013-05-10 | 2017-02-22 | 北京航空航天大学 | Fault-tolerant circuit fault effect analytical method based on simulation |
| CN103840823B (en) * | 2014-02-14 | 2017-09-05 | 北京时代民芯科技有限公司 | The implementation method of the general refresh circuits of aerospace FPGA based on jtag interface |
| CN104166119B (en) * | 2014-09-01 | 2017-03-08 | 国家电网公司 | A kind of intelligent electric energy meter program Detection of Stability system based on error injection |
| CN104657247B (en) * | 2015-02-10 | 2017-12-15 | 上海创景计算机系统有限公司 | Universal fault injection system and fault filling method are realized based on JTAG debud modes |
| CN105974905B (en) * | 2016-05-10 | 2018-08-17 | 中国民航大学 | The emulation test system and method for Aviation data/address bus single-particle inversion failure |
| CN108073479A (en) * | 2016-11-14 | 2018-05-25 | 南京理工大学 | A kind of fault filling method for spaceborne computer reliability demonstration |
| CN106777529A (en) * | 2016-11-23 | 2017-05-31 | 天津大学 | Integrated circuit fault-resistant injection attacks capability assessment method based on FPGA |
| CN110032539B (en) * | 2019-03-20 | 2020-08-25 | 广东高云半导体科技股份有限公司 | Chip pin information processing method and device, computer equipment and storage medium |
| CN110188012B (en) * | 2019-04-26 | 2020-01-03 | 华中科技大学 | FPGA register-level single-particle upset fault simulation method and system |
| CN111538262B (en) * | 2020-04-02 | 2021-05-11 | 华东计算技术研究所（中国电子科技集团公司第三十二研究所） | Carrier rocket computer self-checking system based on DSP and FPGA |
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| CN1658381A (en) * | 2004-02-21 | 2005-08-24 | 华为技术有限公司 | Method and device for implant logical fault |
| CN100371901C (en) * | 2004-08-29 | 2008-02-27 | 华为技术有限公司 | Fault filling method and apparatus based on programmable logical device |
| CN101334754A (en) * | 2008-08-05 | 2008-12-31 | 浙江大学 | Fault infusion based embedded system evaluation method |
| CN101819445B (en) * | 2010-02-05 | 2012-05-16 | 北京航空航天大学 | Embedded satellite-borne fault-tolerant temperature control system and verification method thereof |
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