CN108023587B

CN108023587B - Single-particle reinforced clock control circuit and control method in programmable configuration logic block

Info

Publication number: CN108023587B
Application number: CN201711083475.1A
Authority: CN
Inventors: 陈雷; 郭琨; 文治平; 倪劼; 孙华波; 王文锋; 孙健爽; 钱涛涛; 刘亚泽
Original assignee: Beijing Microelectronic Technology Institute; Mxtronics Corp
Current assignee: Beijing Microelectronic Technology Institute; Mxtronics Corp
Priority date: 2017-11-07
Filing date: 2017-11-07
Publication date: 2022-01-11
Anticipated expiration: 2037-11-07
Also published as: CN108023587A

Abstract

A single-particle reinforced clock control circuit and a control method in a programmable configuration logic block abandon the traditional clock control circuit, adopt a time sequence and an LAT structure to realize the latching and decoding of row, column and data signals, and realize the synchronization of an enable signal and a clock signal to generate a shift overlapping clock and control the shift of data; on the basis, the single event resistance reinforcement function of the user register is realized by adopting the reinforced SRAM and reinforced RS trigger design, and the single event upset resistance of the clock control circuit is improved. The single-particle reinforcement index in the single-particle reinforcement clock control circuit is improved by 3 orders of magnitude compared with the traditional register, so that a user has higher flexibility, better time sequence performance and extremely high single-particle reinforcement resistance index when using the programmable user register.

Description

Single-particle reinforced clock control circuit and control method in programmable configuration logic block

Technical Field

The invention relates to a single-particle reinforced clock control circuit in a programmable configuration logic block and a control method thereof, in particular to a clock control circuit in the programmable configuration logic block which is optimally designed according to the application requirements of a programmable logic device and a control method thereof, belonging to the field of integrated circuits.

Background

The programmable logic device has the advantages of high flexibility, low cost, short period and the like, can greatly shorten the development period of products and maximally reduce risks, and becomes a core component in the integrated circuit industry. The clock control read-write circuit in the programmable configuration logic block is a core circuit for realizing a user logic function in the programmable logic device, and can realize various time sequence functions according to the programming of the user. Due to the influence of the spatial single event effect, single event upset can occur to data in the programmable user register, so that errors of user stored data are caused, and if the single event upset occurs, the user function can be interrupted. The clock control circuit in the traditional programmable configuration logic block controls clock decoding and shifting operation by generating pulses to repeatedly read and write the memory cell, and has limited existing flexible programmable characteristic and single event upset resistance of a programmable logic device. At the same time, the clock control circuits in these programmable configuration logic blocks need to be able to operate at very high frequencies, and their setup/hold times need to be strictly designed. Therefore, it is necessary to ensure that the clock control in the programmable configuration logic block has flexible programmable characteristics, and simultaneously meet the design requirements of speed and time sequence of users and the extremely high single event resistance reinforcement index for the programmable logic device.

Disclosure of Invention

The technical problem solved by the invention is as follows: the clock control circuit in the programmable configuration logic block has flexible programmable characteristics, solves the problem of error of stored data caused by single event upset, solves the problem of controlling clock decoding and shifting by repeatedly reading and writing a storage unit, solves the problem that a clock control circuit cannot work at very high frequency, and meets the design requirements of users on higher speed and time sequence.

The technical scheme of the invention is as follows: a single event hardened clocking circuit in a programmable configuration logic block, comprising: the system comprises a clock input circuit, a row and column control generating circuit, a reinforced RS trigger and a reinforced SRAM;

the clock input circuit is used for inputting an external common clock signal clk into the clock input circuit when the global control signals are all effective, converting the common clock signal clk into an overlapped shifting clock signal when a shifting signal shift input by a user is received, and transmitting the overlapped shifting clock signal to the reinforced RS trigger;

the reinforced SRAM receives the overlapped shift clock signal reinforced by radiation resistance or the common clock signal reinforced by radiation resistance, and then the clock signal controls the reinforced SRAM to read and write data or shift;

the clock input circuit transmits a common clock signal clk driven by the inverter to the row and column control generating circuit, the row and column control generating circuit delays the common clock signal clk driven by the inverter when receiving the common clock signal clk driven by the inverter and then superposes the delayed common clock signal clk with the common clock signal clk to obtain a row and column data control signal, the row and column data control signal can control the row and column control generating circuit to latch data, a row signal and a column signal input to the row and column control generating circuit, the latched signal is decoded, the decoded signal is transmitted to the reinforced SRAM, and the decoded signal can select the SRAM array in the reinforced SRAM to read and write or shift data.

A global control signal comprising: a circuit effective signal ce, a write effective signal we, a global write effective signal gwe, and a global high level effective signal GHIGH; the global signal can always control the normal work of the circuit; the function of the circuit effective signal ce is a control signal for normal operation of the whole clock control circuit, the function of the write effective signal we is a control signal for normal write operation of the hardened SRAM, the function of the global write effective signal gwe is a global control signal for normal write operation of the hardened SRAM, and the function of the GHIGH is a global high-level control signal for normal write operation of the hardened SRAM.

The reinforced SRAM is provided with an SRAM array, and the SRAM specified by the decoded signal in the reinforced SRAM can be selected to read, write and shift data according to the decoded signal.

A clock input circuit comprising: an inverter K21, a multiplexer K22, a nand gate K23, an inverter K24, a Latch (LAT) K25, a buffer K26, a nand gate K27, an and gate K28, an inverter K29, a circuit valid signal input K38, a write valid signal we input K39, a global write valid signal gwe input K40, a global high-level valid signal GHIGH input K41, a shift signal shift input K42, and a common clock signal clk input K37;

the input of the inverter K21 is connected with a circuit effective ce signal input end K38, the output of the inverter K21 is connected with one input of a multiplexer K22, the other input of the multiplexer K22 is connected with a write effective signal we input end K39, the output of a multiplexer K22 is connected with one input of a NAND gate K23, the other input of the K23 is connected with a global write effective signal gwe input end K40, the output end of the K23 is connected with an input end a of a latch K25, a clock end b of the latch K25 is connected with the input of the inverter K24, a common clock signal clk and a first signal input end RN1 of a reinforced RS flip-flop, and a control end c of the latch K25 is connected with a global high-level effective signal GHIGH input end K41; the output end d of the latch K25 is connected with one input of an AND gate K28, the other input of the AND gate K28 is connected with one input of a K27 and the output of a buffer K26, and the input of a buffer K26 is connected with a shift signal shift input end K42; the other input of the NAND gate K27 is a circuit reservation control end 1, the output of the AND gate K28 is connected with a second signal input end SN of the reinforced RS trigger, the output of the NAND gate K27 is connected with the input of the inverter K29, and the output of the inverter K29 is connected with a third signal input end SN1 of the reinforced RS trigger; the output of the inverter K24 is connected to the fourth signal input RN of the hardened RS flip-flop and to the input of the rank control generation circuit.

A row-column control generation circuit comprising: an inverter K4, a nand gate K5, a nor gate K6, a nand gate K7, an inverter K8, an inverter K9, a latch K10, a latch K11, a latch K12, a data D input K31, a COLUMN signal COLUMN input K32, a ROW signal ROW input K33, an inverter K13, an inverter K14, an inverter K15, a multiplexer K16, a nor gate K17, an inverter K18, an inverter K19, a nand gate K20, a data output K36, a COLUMN signal output K35, a ROW signal output K34, an inverter K1, a nand gate K2, and a nor gate K3;

the inverter K4 is connected with the output of the inverter K24, the output of the inverter K4 is connected with one input of the NAND gate K5, the other input of the NAND gate K5 is connected with the external power supply VS, the output of the NAND gate K5 is connected with one input of the NOR gate K6, the other input of the NOR gate K6 is a circuit reservation control terminal 2, the output of the NOR gate K6 is connected with one input of the NAND gate K7, the other input of the NAND gate K7 is connected with the common clock signal clk, the output of the NAND gate K7 is connected with the input ends of the inverter K8 and the inverter K9, the inverter K8 is connected with the clock input end a of the latch K10, the output end of the inverter K9 is connected with the clock input ends a of the latch K11 and the latch K12, the data input end b of the latch K10 is connected with the data D input end K31, the data input end b of the latch K11 is connected with the COLUMN signal COLUMN input end K32, the data input end b of the latch K12 is connected with the ROW signal ROW input end K33, the output of the latch K10 is connected with the input of an inverter K13, the output of the latch K11 is connected with the input of a K14, the output of the latch K12 is connected with the input of an inverter K15, the output of the inverter K13 is connected with one input of a multiplexer K16, the other input of the multiplexer is a circuit reservation control terminal 3, the output of the inverter K14 is connected with one input of a NOR gate K17, the other input of the NOR gate K17 is a circuit reservation control terminal 4, the output of the inverter K15 is connected with one input of a NOR gate K3, the output of the multiplexer is connected with the input of an inverter K18, the output of the NOR gate K17 is connected with one input of a NAND gate K20, the other input of a NAND gate K20 is a circuit reservation control terminal 5, the output of the inverter K18 is connected with the input of an inverter K19, the output of an inverter K19 is connected with a data output terminal K36, and the data output terminal is connected with the R terminal of the reinforced SRAM, the output of the NAND gate K20 is connected with a column signal output end K35, the column signal output end K35 is connected with a reinforced SRAM and acts on a WL end, the input of the inverter K1 is connected with a common clock signal clk input end K37, the output of the inverter K1 is connected with one input of the NAND gate K2, the other input of the NAND gate K2 is a circuit reservation control end 6, the output of the NAND gate K2 is connected with the other input of the NOR gate K3, the output of the NOR gate K3 is connected with a row signal output end K34, and the row signal output end K34 is connected with a reinforced SRAM and acts on a selection input end WL.

Latch K25, comprising: a latch data input b end K113, a clock input a end K114, a clock input inverting-a end K115, a transmission gate K44, an inverter K45, a transmission gate K46, an inverter K47 and a latch data output c end K116;

the input end of the transmission gate K44 is connected with a data input b terminal K113, the control port of the transmission gate K44 is connected with a clock input a terminal K114 and an inverse a terminal K115, the output of the transmission gate K44 is connected with the input of the transmission gate K46 and the input of the inverter K45, the output of the inverter K45 is connected with a latch data output c terminal K116 and the input of the inverter K47, the control port of the transmission gate K46 is connected with a clock input a terminal K117 and a clock input inverse a terminal K118, and the output of the inverter K47 is connected with the input end of the transmission gate K46.

A ruggedized SRAM, comprising: a P-channel mos tube K50, a P-channel mos tube K51, a P-channel mos tube K52, a P-channel mos tube K53, a P-channel mos tube K48, a P-channel mos tube K49, a P-channel mos tube K54, a P-channel mos tube K55, an N-channel mos tube K59, an N-channel mos tube K58, an N-channel mos tube K57, an N-channel mos tube K56, a power input VRAM end K120, a word line selection input WL end K115, a bit line input R end K116, a bit line input inverting RN end K119, a data output Z end K117 and a data inverting output ZN end K118;

the bit line input R end K116 is connected to the source electrode of the N-channel mos tube K57 and the source electrode of the N-channel mos tube K59; the bit line input inverting RN terminal K119 is connected to the source of the N-channel mos transistor K56 and the source of the N-channel mos transistor K58; the N-channel mos tube K58 is connected with a SRAM data output Z end K117, and the drain electrode of the N-channel mos tube K59 is connected with a data inversion output ZN end K118; the word line selection input WL end K115 is connected with a grid electrode of an N-channel mos tube K59, a grid electrode of an N-channel mos tube K58, a grid electrode of an N-channel mos tube K57 and a grid electrode of an N-channel mos tube K56;

the drain electrode of the N-channel mos tube K59 is connected to the drain electrode of the P-channel mos tube K48, the drain electrode of the N-channel mos tube K58 is connected to the drain electrode of the P-channel mos tube K49, the drain electrode of the N-channel mos tube K57 is connected to the drain electrode of the P-channel mos tube K54, and the drain electrode of the N-channel mos tube K56 is connected to the drain electrode of the P-channel mos tube K55;

the grid electrode of the P-channel mos tube K48 is connected to the source electrode of the P-channel mos tube K49, the grid electrode of the P-channel mos tube K49 is connected to the source electrode of the P-channel mos tube K54, the grid electrode of the P-channel mos tube K54 is connected to the source electrode of the P-channel mos tube K55, and the grid electrode of the P-channel mos tube K55 is connected to the source electrode of the P-channel mos tube K48;

the source electrode of the P-channel mos tube K48 is connected to the drain electrode of the P-channel mos tube K50 and the grid electrode of the P-channel mos tube K51; the source electrode of the P-channel mos tube K49 is connected to the drain electrode of the P-channel mos tube K51 and the grid electrode of the P-channel mos tube K52; the source electrode of the P-channel mos tube K54 is connected to the drain electrode of the P-channel mos tube K52 and the grid electrode of the P-channel mos tube K53; the source electrode of the P-channel mos tube K55 is connected to the drain electrode of the P-channel mos tube K53 and the grid electrode of the P-channel mos tube K50;

the source electrode of the P-channel mos tube K50, the source electrode of the P-channel mos tube K51, the source electrode of the P-channel mos tube K52 and the source electrode of the P-channel mos tube K53 are connected to the power supply input VRAM end K120 in common.

A ruggedized RS flip-flop, comprising: a P-channel mos tube K60, a P-channel mos tube K61, a P-channel mos tube K62, a P-channel mos tube K66, a P-channel mos tube K67, a P-channel mos tube K68, a P-channel mos tube K72, an N-channel mos tube K72, an RN-channel mos tube K72, an N-channel input terminal power supply input terminal, an RN-terminal data input terminal SN 72, an inverted terminal SN input terminal 72, an inverted terminal SN input terminal SN 72, and an inverted terminal SN 72;

the data input SN end K86 is connected to a grid electrode of a P-channel mos tube K61, a grid electrode of an N-channel mos tube K64, a grid electrode of a P-channel mos tube K73 and a grid electrode of a P-channel mos tube K76; a data inverting input SN1 end K87 is connected to a grid electrode of a P-channel mos tube K60, a grid electrode of an N-channel mos tube K65, a grid electrode of a P-channel mos tube K74 and a grid electrode of an N-channel mos tube K77;

the clock input RN terminal K90 is connected to a grid electrode of a P-channel mos tube K67, a grid electrode of an N-channel mos tube K70, a grid electrode of a P-channel mos tube K79 and a grid electrode of an N-channel mos tube K82; a clock inverting input RN1 end K89 is connected to a grid electrode of a P-channel mos tube K68, a grid electrode of an N-channel mos tube K71, a grid electrode of a P-channel mos tube K80 and a grid electrode of an N-channel mos tube K83;

the source electrode of the P-channel mos tube K60, the source electrode of the P-channel mos tube K61 and the source electrode of the P-channel mos tube K62 are connected to a power supply Vdd input end K88; the drain electrode of the P-channel mos tube K60, the drain electrode of the P-channel mos tube K61 and the drain electrode of the P-channel mos tube K62 are connected to the drain electrode of the N-channel mos tube K63, the grid electrode of the N-channel mos tube K69, the grid electrode of the N-channel mos tube K78 and a clock output Q end K84; the source electrode of the N-channel mos tube K63 is connected to the drain electrode of the N-channel mos tube K64, the source electrode of the N-channel mos tube K64 is connected to the drain electrode of the N-channel mos tube K65, and the source electrode of the N-channel mos tube K65 is grounded;

the source electrode of the P-channel mos tube K66, the source electrode of the P-channel mos tube K67 and the source electrode of the P-channel mos tube K68 are connected to a Vdd power supply K88; the drain electrode of the P-channel mos tube K66, the drain electrode of the P-channel mos tube K67 and the drain electrode of the P-channel mos tube K68 are connected to the grid electrode of the P-channel mos tube K62, the grid electrode of the N-channel mos tube K75 and the clock inverting output QN end K85; the source electrode of the N-channel mos tube K69 is connected to the drain electrode of the N-channel mos tube K70, the source electrode of the N-channel mos tube K70 is connected to the drain electrode of the N-channel mos tube K71, and the source electrode of the N-channel mos tube K71 is grounded;

a source electrode of the P-channel mos tube K72, a source electrode of the P-channel mos tube K73 and a source electrode of the P-channel mos tube K74 are connected to a power supply Vdd input end K88; the drain electrode of the P-channel mos tube K72, the drain electrode of the P-channel mos tube K73 and the drain electrode of the P-channel mos tube K74 are connected to the drain electrode of the N-channel mos tube K75; the drain electrode of the K75 is connected to the source electrode of the N-channel mos tube K76, the source electrode of the N-channel mos tube K76 is connected to the drain electrode of the N-channel mos tube K77, and the source electrode of the N-channel mos tube K77 is connected to the ground;

the source electrode of the P-channel mos tube K78, the source electrode of the P-channel mos tube K79 and the source electrode of the P-channel mos tube K80 are connected to a power supply Vdd input end K88; the drain electrode of the P-channel mos tube K78, the drain electrode of the P-channel mos tube K79 and the drain electrode of the P-channel mos tube K80 are connected to the drain electrode of the N-channel mos tube K81; the source electrode of the N-channel mos tube K81 is connected to the drain electrode of the N-channel mos tube K82, the source electrode of the N-channel mos tube K82 is connected to the drain electrode of the N-channel mos tube K83, and the source electrode of the N-channel mos tube K83 is connected to the ground;

the global clock signal and the input signal are configured to realize that the whole circuit is in an effective working state: the circuit effective ce signal input end K38 or the write effective signal we input end K39 is high level, the global write effective signal gwe input end K40 is high level, the global high level effective signal GHIGH input end K41 is high level, the external power source VS is effective, the circuit retention control end 1 is high level, the circuit retention control end 2 is low level, the circuit retention control end 3 is low level, the circuit retention control end 4 is low level, the circuit retention control end 5 is high level, the circuit retention control end 6 is high level, at this moment, the circuit can normally work, and input of user data clocks and the like is waited.

The invention discloses a control method of a single-event reinforced clock control circuit in a programmable configuration logic block, which comprises the following steps:

(1) configuring a circuit working mode into a clock control read-write function, wherein a user inputs a set clock signal at a common clock signal clk input end K37 and provides a read-write clock signal for a reinforced SRAM after the clock signal is reinforced by a reinforced RS trigger;

(2) when the step (1) is carried out, clock signals enter a row and column control generating circuit, enter a latch clock input end after delayed superposition of a combinational logic gate, and control data D to be written in;

(3) the reinforced SRAM, the control COLUMN signal COLUMN and the ROW signal ROW are connected to the reinforced SRAM for decoding and latching; in the process of latching and decoding, the read-write operation is realized according to the following steps: if the clock is at low level, the latch latches, and the row, column and data latches, so that the read-write is effective; if the clock is a rising edge, the ROW signal ROW is invalid, and the reading and writing are invalid; if the clock is at high level, the latch is connected in series, the row, the column and the data can be changed, and the reading and the writing are effective; if the clock is a falling edge, the latch latches, and the row, column and data latches, so that the reading and writing are effective;

(4) the circuit working mode is configured to be a clock control shift function, at the moment, a shift signal shift is input by a user to be a high level to activate the clock shift function, meanwhile, a desired clock signal is input at an input end K37 of a common clock signal clk to generate two non-overlapping clocks, and the clock signals enter a reinforced SRAM after being connected with a reinforced RS trigger for reinforcement to realize shift operation.

Compared with the prior art, the invention has the advantages that:

(1) the invention realizes the latch of row, column and data signals by adopting the LAT structure, flexibly selects and decodes addresses, realizes various selections of storage units for users and can provide flexible programmability.

(2) The invention realizes the synchronization of clock, data and address by adopting the LAT structure to decode the row, column and data signals, and can meet the speed requirement required by users.

(3) According to the invention, the reinforced SRAM memory is used, the single event upset resistance of the programmable user register programmed to a state in a storage period can be greatly improved, and compared with the traditional trigger, the single event resistance index is at least improved by 3 orders of magnitude.

(4) According to the invention, the clock signal is converted into the non-overlapping clock by adopting the reinforced RS trigger structure, so that a stable clock signal can be provided for a user, and a synchronous shift function is realized.

(5) The invention realizes that the probability of decoding errors is reduced in the address decoding process by adopting a structure of combining the time sequence and the combinational logic, keeps higher time sequence and meets the requirements of users on the time sequence.

Drawings

FIG. 1 is a schematic diagram of a clock control circuit in a programmable configuration logic block of the present invention;

FIG. 2 is a schematic diagram of the LAT circuit of the present invention;

FIG. 3 is a schematic diagram of a ruggedized SRAM circuit of the present invention;

fig. 4 is a schematic diagram of a hardened RS flip-flop circuit of the present invention.

Detailed Description

The invention is described in further detail below with reference to the figures and specific embodiments.

The invention relates to a single-particle reinforced clock control circuit in a programmable configuration logic block and a control method, which abandon the traditional clock control circuit, adopt a time sequence and LAT structure to realize the latching and decoding of row, column and data signals, realize the synchronization of an enable signal and a clock signal, generate a shift overlapping clock and control the shift of data; on the basis, the reinforced SRAM and the reinforced RS trigger are designed to realize the single event resistance reinforcement function of the user register, and the single event upset resistance of the clock control circuit is improved. The single-particle reinforcement index in the single-particle reinforcement clock control circuit is improved by 3 orders of magnitude compared with the traditional register, so that a user has higher flexibility, better time sequence performance and extremely high single-particle reinforcement resistance index when using the programmable user register.

The single-event reinforced clock control circuit in the programmable configuration logic block is an important component of the configurable logic circuit, and the preferred scheme of the global clock signal and the input signal in the configurable logic circuit is as follows: circuit active ce signal input K38 (active high), write active signal we input K39 (active high), global write active signal gwe input K40 (active high), global active high signal GHIGH input K41 (active high), external power source VS, circuit retention control terminal 1 (active high), circuit retention control terminal 2 (active low), circuit retention control terminal 3 (active low), circuit retention control terminal 4 (active low), circuit retention control terminal 5 (active high), circuit retention control terminal 6 (active high).

The preferable working scheme of the single-event reinforced clock control circuit in the programmable configuration logic block is provided, so that the working state of the circuit is improved, the global clock signal and the input signal in the configurable logic circuit need to be adjusted to be in an effective working state, and the method comprises the following specific settings: the circuit effective ce signal input end K38 or the write effective signal we input end K39 is high level, the global write effective signal gwe input end K40 is high level, the global high level effective signal GHIGH input end K41 is high level, the external power source VS is effective, the circuit retention control end 1 is high level, the circuit retention control end 2 is low level, the circuit retention control end 3 is low level, the circuit retention control end 4 is low level, the circuit retention control end 5 is high level, the circuit retention control end 6 is high level, at this moment, the circuit can normally work, and input of user data clocks and the like is waited.

The single-event reinforced clock control circuit in the programmable configuration logic block can be configured into a clock control read-write function or a clock control shift function according to the processing requirements of users on the configurable logic circuit, and the specific functions are as follows:

1) if the circuit working mode is configured to be a clock control read-write function, a user can input a desired clock signal at the input end K37 of the common clock signal clk and provide a read-write clock signal for the reinforced SRAM after the clock signal is reinforced by the reinforced RS trigger; meanwhile, a clock signal enters a ROW and COLUMN control generating circuit, enters a latch clock input end after delayed superposition of the combinational logic gate to control data D to be written into the reinforced SRAM, control a COLUMN signal COLUMN and a ROW signal ROW to be connected to the reinforced SRAM for decoding and latching; in the process of latching and decoding, the read-write operation is realized according to the following steps: if the clock is at low level, the latch latches, and the row, column and data latches, so that the read-write is effective; if the clock is a rising edge, the ROW signal ROW is invalid, and the reading and writing are invalid; if the clock is at high level, the latch is connected in series, the row, the column and the data can be changed, and the reading and the writing are effective; if the clock is a falling edge, the latch latches, and the row, column and data latches, so that the reading and writing are effective;

2) if the circuit working mode is configured to be a clock control shift function, at this time, a shift signal shift input by a user is a high level to activate the clock shift function, meanwhile, a desired clock signal is input at an input end K37 of a common clock signal clk, two non-overlapping clocks are generated, and the clock signals enter a reinforced SRAM after being connected with a reinforced RS trigger for reinforcement to realize shift operation.

As shown in fig. 1, when the global control signals are all valid, an external common clock signal clk (the clock input signal adopted by the present invention is preferably a square wave) can be input into the clock input circuit, and when a shift signal shift input by a user is received, the common clock signal clk is converted into an overlapped shift clock signal and is sent to the reinforced RS flip-flop. The frequency of clk input required to be controlled to normally work is 200 MHz-1 GHz, the pulse width is at least 1ns, and the shift signal shift is required to ensure the pulse width of 1 ns.

A clock input circuit comprising: the circuit comprises an inverter K21, a multiplexer K22, an NAND gate K23, an inverter K24, a latch K25, a buffer K26, a NAND gate K27, an AND gate K28, an inverter K29, a circuit valid signal input end K38, a write valid signal we input end K39, a global write valid signal gwe input end K40, a global high-level valid signal GHIGH input end K41, a shift signal shift input end K42 and a common clock signal clk input end K37;

the input of the inverter K21 is connected with a circuit effective ce signal input end K38, the output of the inverter K21 is connected with one input of a multiplexer K22, the other input of the multiplexer K22 is connected with a write effective signal we input end K39, the output of a multiplexer K22 is connected with one input of a NAND gate K23, the other input of the K23 is connected with a global write effective signal gwe input end K40, the output end of the K23 is connected with an input end a of a latch K25, a clock end b of the latch K25 is connected with the input of the inverter K24, a common clock signal clk and a first signal input end RN1 of a reinforced RS flip-flop, and a control end c of the latch K25 is connected with a global high-level effective signal GHIGH input end K41; the output end d of the latch K25 is connected with one input of an AND gate K28, the other input of the AND gate K28 is connected with one input of a K27 and the output of a buffer K26, the buffer adopts two common inverters to be connected in series to achieve the buffering effect, and the input of the buffer K26 is connected with a shift signal shift input end K42; the other input of the NAND gate K27 is a circuit reservation control end 1, the output of the AND gate K28 is connected with a second signal input end SN of the reinforced RS trigger, the output of the NAND gate K27 is connected with the input of the inverter K29, and the output of the inverter K29 is connected with a third signal input end SN1 of the reinforced RS trigger; the output of the inverter K24 is connected to the fourth signal input RN of the hardened RS flip-flop and to the input of the rank control generation circuit.

The row and column control generating circuit, as shown in the figure, the clock input circuit sends the common clock signal clk driven by the inverter to the row and column control generating circuit, when receiving the common clock signal clk driven by the inverter, delaying the common clock signal clk driven by the inverter, and then superimposing the delayed common clock signal clk with the common clock signal clk to obtain a row-column data control signal, wherein the row-column data control signal can control the row-column control generation circuit to latch the data, the row signal (which can be input as low level or high level according to the user requirement) and the column signal (which can be input as low level or high level according to the user requirement) input to the row-column control generation circuit, and decode the latched signals, and then, sending the decoded signal to a reinforced SRAM, wherein the decoded signal can select an SRAM array in the reinforced SRAM to read and write or shift data. In the process of latching and decoding, the read-write operation is realized according to the following steps: if the clock is at low level, the latch latches, and the row, column and data latches, so that the read-write is effective; if the clock is a rising edge, the ROW signal ROW is invalid, and the reading and writing are invalid; if the clock is at high level, the latch is connected in series, the row, the column and the data can be changed, and the reading and the writing are effective; if the clock is a falling edge, the latch latches, and the row, column and data latches, so that the reading and writing are effective. By adopting a structure combining time sequence and combinational logic, the decoding error occurrence probability is reduced in the address decoding process, higher time sequence is kept, and the requirement of a user on the time sequence is met.

the inverter K4 is connected with the output of the inverter K24, the output of the inverter K4 is connected with one input of the NAND gate K5, the other input of the NAND gate K5 is connected with the external power supply VS, the output of the NAND gate K5 is connected with one input of the NOR gate K6, the other input of the NOR gate K6 is a circuit reservation control terminal 2, the output of the NOR gate K6 is connected with one input of the NAND gate K7, the other input of the NAND gate K7 is connected with the common clock signal clk, the output of the NAND gate K7 is connected with the input ends of the inverter K8 and the inverter K9, the inverter K8 is connected with the clock input end a of the latch K10, the output end of the inverter K9 is connected with the clock input ends a of the latch K11 and the latch K12, the data input end b of the latch K10 is connected with the data D input end K31, the data input end b of the latch K11 is connected with the COLUMN signal COLUMN input end K32, the data input end b of the latch K12 is connected with the ROW signal ROW input end K33, the output of the latch K10 is connected with the input of an inverter K13, the output of the latch K11 is connected with the input of a K14, the output of the latch K12 is connected with the input of an inverter K15, the output of the inverter K13 is connected with one input of a multiplexer K16, the other input of the multiplexer is a circuit reservation control terminal 3, the output of the inverter K14 is connected with one input of a NOR gate K17, the other input of the NOR gate K17 is a circuit reservation control terminal 4, the output of the inverter K15 is connected with one input of a NOR gate K3, the output of the multiplexer is connected with the input of an inverter K18, the output of the NOR gate K17 is connected with one input of a NAND gate K20, the other input of a NAND gate K20 is a circuit reservation control terminal 5, the output of the inverter K18 is connected with the input of an inverter K19, the output of an inverter K19 is connected with a data output terminal K36, and the data output terminal is connected with the R terminal of the reinforced SRAM, the output of the NAND gate K20 is connected with a column signal output end K35, the column signal output end K35 is connected with a reinforced SRAM and acts on a WL end, the input of the inverter K1 is connected with a common clock signal clk input end K37, the output of the inverter K1 is connected with one input of the NAND gate K2, the other input of the NAND gate K2 is a circuit reservation control end 6, the output of the NAND gate K2 is connected with the other input of the NOR gate K3, the output of the NOR gate K3 is connected with a row signal output end K34, the row signal output end K34 is connected with the reinforced SRAM and acts on a selection input end WL, the frequency of the clk input which is controlled to normally work is 200 MHz-1 GHz, the pulse width is preferably at least 1ns, and the pulse width of the row signal input end, the column signal input end and the data input end is at least 1 ns.

Latch (LAT) K25, shown in fig. 2, includes: a latch data input b end K113, a clock input a end K114, a clock input inverting-a end K115, a transmission gate K44, an inverter K45, a transmission gate K46, an inverter K47 and a latch data output c end K116;

the input end of a transmission gate K44 is connected with a data input b end K113, the control port of the transmission gate K44 is connected with a clock input a end K114 and an inverse phase-a end K115, the output of a transmission gate K44 is connected with the input of a transmission gate K46 and the input of an inverter K45, the output of an inverter K45 is connected with a latch data output c end K116 and the input of an inverter K47, the control port of a transmission gate K46 is connected with a clock input a end K117 and a clock input inverse phase-a end K118, the output of the inverter K47 is connected with the input end of a transmission gate K46, and the transmission gate adopts a common geminate transistor form of butt joint of an N-channel mos transistor and a P-channel mos transistor; the invention adopts the LAT structure to decode the row, column and data signals to realize the synchronization of the clock, the data and the address, and can meet the speed requirement required by the user.

As shown in fig. 3, the reinforced RS flip-flop performs anti-radiation reinforcement on the overlapping shift clock signal to obtain an anti-radiation reinforced overlapping shift clock signal, and sends the anti-radiation reinforced overlapping shift clock signal to the reinforced SRAM, and the reinforced SRAM controls the reinforced SRAM to perform data read-write by using the clock signal after receiving the anti-radiation reinforced overlapping shift clock signal.

compared with an RS trigger, the reinforced RS trigger adopts four groups of single-tube interlocking structures, so that the radiation resistance reinforcing capability is improved, and the stability of clock signals is improved.

The reinforced SRAM is provided with an SRAM array, the SRAM appointed by the decoded signals in the reinforced SRAM can be selected to read, write and shift data according to the decoded signals, meanwhile, the single event upset resistance of the programmable user register programmed to be in a storage period can be greatly improved, and compared with a traditional trigger, the single event reinforcement index is at least improved by 4 orders of magnitude.

As shown in fig. 4, the reinforced SRAM includes: a P-channel mos tube K50, a P-channel mos tube K51, a P-channel mos tube K52, a P-channel mos tube K53, a P-channel mos tube K48, a P-channel mos tube K49, a P-channel mos tube K54, a P-channel mos tube K55, an N-channel mos tube K59, an N-channel mos tube K58, an N-channel mos tube K57, an N-channel mos tube K56, a power input VRAM end K120, a word line selection input WL end K115, a bit line input R end K116, a bit line input inverse RN end K119, a data output Z end K117 and a data inverse output ZN end K118;

the source electrode of the P-channel mos tube K50, the source electrode of the P-channel mos tube K51, the source electrode of the P-channel mos tube K52 and the source electrode of the P-channel mos tube K53 are connected to the power input VRAM end K120, compared with a common six-tube SRAM, the reinforced SRAM adopts a grid interlocking structure, storage contents cannot be easily changed under the influence of irradiation, and the single-particle-upset resistance is enhanced.

TABLE 1 Single event upset ratio of clock control circuits in programmable configuration logic blocks of the present invention

Therefore, the circuit can work under a frequency clock of 200 MHz-1 GHz, the pulse width is 1ns at least, and the circuit can be used in programmable logic devices of 300 ten thousand gates to 1000 ten thousand gates. Under the clock condition of 400MHz, the circuit of the invention adopts a 65 nanometer technology 1.2v device of a central core international company, and can also select a proper device type such as a 1.0v device according to the requirements of users, the occurrence probability of decoding errors is reduced from the traditional 5 percent to 1.2 percent, the stability of data signals is improved by 2 times compared with the original stability, especially in single event strengthening indexes, as shown in the table I, under Si particles, the single event turnover rate of the circuit of the invention is reduced by 4 orders of magnitude compared with the single event turnover rate of a traditional register, so the invention has good single event strengthening effect.

Claims

1. A single event hardened clock control circuit in a programmable configuration logic block, comprising: the system comprises a clock input circuit, a row and column control generating circuit, a reinforced RS trigger and a reinforced SRAM;

2. The single event hardened clock control circuit in a programmable configuration logic block of claim 1, wherein: a global control signal comprising: a circuit effective signal ce, a write effective signal we, a global write effective signal gwe, and a global high level effective signal GHIGH; the global signal can always control the normal work of the circuit; the function of the circuit effective signal ce is a control signal for normal operation of the whole clock control circuit, the function of the write effective signal we is a control signal for normal write operation of the hardened SRAM, the function of the global write effective signal gwe is a global control signal for normal write operation of the hardened SRAM, and the function of the GHIGH is a global high-level control signal for normal write operation of the hardened SRAM.

3. The single event hardened clock control circuit in a programmable configuration logic block of claim 1, wherein: the reinforced SRAM is provided with an SRAM array, and the SRAM specified by the decoded signal in the reinforced SRAM can be selected to read, write and shift data according to the decoded signal.

4. The single event hardened clock control circuit in a programmable configuration logic block of claim 1, wherein: a clock input circuit comprising: the circuit comprises an inverter K21, a multiplexer K22, an NAND gate K23, an inverter K24, a latch K25, a buffer K26, a NAND gate K27, an AND gate K28, an inverter K29, a circuit valid signal input end K38, a write valid signal we input end K39, a global write valid signal gwe input end K40, a global high-level valid signal GHIGH input end K41, a shift signal shift input end K42 and a common clock signal clk input end K37;

5. The single event hardened clock control circuit in a programmable configuration logic block of claim 1, wherein: a row-column control generation circuit comprising: an inverter K4, a nand gate K5, a nor gate K6, a nand gate K7, an inverter K8, an inverter K9, a latch K10, a latch K11, a latch K12, a data D input K31, a COLUMN signal COLUMN input K32, a ROW signal ROW input K33, an inverter K13, an inverter K14, an inverter K15, a multiplexer K16, a nor gate K17, an inverter K18, an inverter K19, a nand gate K20, a data output K36, a COLUMN signal output K35, a ROW signal output K34, an inverter K1, a nand gate K2, and a nor gate K3;

the inverter K4 is connected with the output of the inverter K24, the output of the inverter K4 is connected with one input of the NAND gate K5, the other input of the NAND gate K5 is connected with the external power supply VS, the output of the NAND gate K5 is connected with one input of the NOR gate K6, the other input of the NOR gate K6 is a circuit reservation control terminal 2, the output of the NOR gate K6 is connected with one input of the NAND gate K7, the other input of the NAND gate K7 is connected with the common clock signal clk, the output of the NAND gate K7 is connected with the input ends of the inverter K8 and the inverter K9, the inverter K8 is connected with the clock input end a of the latch K10, the output end of the inverter K9 is connected with the clock input ends a of the latch K11 and the latch K12, the data input end b of the latch K10 is connected with the data D input end K31, the data input end b of the latch K11 is connected with the COLUMN signal COLUMN input end K32, the data input end b of the latch K12 is connected with the ROW signal ROW input end K33, the output of the latch K10 is connected with the input of an inverter K13, the output of the latch K11 is connected with the input of a K14, the output of the latch K12 is connected with the input of an inverter K15, the output of the inverter K13 is connected with one input of a multiplexer K16, the other input of the multiplexer is a circuit reservation control terminal 3, the output of the inverter K14 is connected with one input of a NOR gate K17, the other input of the NOR gate K17 is a circuit reservation control terminal 4, the output of the inverter K15 is connected with one input of a NOR gate K3, the output of the multiplexer is connected with the input of an inverter K18, the output of the NOR gate K17 is connected with one input of a NAND gate K20, the other input of a NAND gate K20 is a circuit reservation control terminal 5, the output of the inverter K18 is connected with the input of an inverter K19, the output of an inverter K19 is connected with a data output R terminal K36, the data output terminal is connected with the R terminal of the reinforced SRAM, the output of the NAND gate K20 is connected with the column signal K35, the column signal output end K35 is connected with a reinforced SRAM and acts on a WL end, the input of an inverter K1 is connected with a common clock signal clk input end K37, the output of the inverter K1 is connected with one input of a NAND gate K2, the other input of the NAND gate K2 is a circuit reservation control end 6, the output of the NAND gate K2 is connected with the other input of a NOR gate K3, the output of the NOR gate K3 is connected with a row signal output end K34, and the row signal output end K34 is connected with the reinforced SRAM and acts on a word line selection input end WL.

6. The single event hardened clock control circuit in a programmable configuration logic block of claim 4, wherein: latch K25, comprising: a latch data input b end K113, a clock input a end K114, a clock input inverting-a end K115, a transmission gate K44, an inverter K45, a transmission gate K46, an inverter K47 and a latch data output c end K116;

7. The single event hardened clock control circuit in a programmable configuration logic block of claim 1, wherein: a ruggedized SRAM, comprising: a P-channel mos tube K50, a P-channel mos tube K51, a P-channel mos tube K52, a P-channel mos tube K53, a P-channel mos tube K48, a P-channel mos tube K49, a P-channel mos tube K54, a P-channel mos tube K55, an N-channel mos tube K59, an N-channel mos tube K58, an N-channel mos tube K57, an N-channel mos tube K56, a power input VRAM end K120, a word line selection input WL end K115, a bit line input R end K116, a bit line input inverse RN end K119, a data output Z end K117 and a data inverse output ZN end K118;

8. The single event hardened clock control circuit in a programmable configuration logic block of claim 1, wherein: a ruggedized RS flip-flop, comprising: a P-channel mos tube K60, a P-channel mos tube K61, a P-channel mos tube K62, a P-channel mos tube K66, a P-channel mos tube K67, a P-channel mos tube K68, a P-channel mos tube K72, an N-channel mos tube K72, an RN-channel mos tube K72, an N-channel input terminal power supply input terminal, an RN-terminal data input terminal SN 72, an inverted terminal SN input terminal 72, an inverted terminal SN input terminal SN 72, and an inverted terminal SN 72;

the source electrode of the P-channel mos tube K78, the source electrode of the P-channel mos tube K79 and the source electrode of the P-channel mos tube K80 are connected to a power supply Vdd input end K88; the drain electrode of the P-channel mos tube K78, the drain electrode of the P-channel mos tube K79 and the drain electrode of the P-channel mos tube K80 are connected to the drain electrode of the N-channel mos tube K81; the source electrode of the N-channel mos tube K81 is connected to the drain electrode of the N-channel mos tube K82, the source electrode of the N-channel mos tube K82 is connected to the drain electrode of the N-channel mos tube K83, and the source electrode of the N-channel mos tube K83 is connected to the ground.

9. The single event hardened clock control circuit in a programmable configuration logic block of claim 1, wherein: the global clock signal and the input signal are configured to realize that the whole circuit is in an effective working state: circuit valid ce signal input K38 or write valid signal we input K39 is the high level, global write valid signal gwe input K40 is the high level, global high level valid signal GHIGH input K41 is the high level, external power source VS is effective, circuit reservation control end 1 is the high level, circuit reservation control end 2 is the low level, circuit reservation control end 3 is the low level, circuit reservation control end 4 is the low level, circuit reservation control end 5 is the high level, circuit reservation control end 6 is the high level, the circuit can normally work this moment, wait for user data clock input.

10. The method for controlling the single-event hardened clock control circuit in the programmable configuration logic block according to any one of claims 1 to 9, characterized by the steps of: