CN105761746A - Read-in time sequence matching circuit of single-particle reinforced FPGA distributed RAM - Google Patents
Read-in time sequence matching circuit of single-particle reinforced FPGA distributed RAM Download PDFInfo
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Abstract
The invention provides a read-in time sequence matching circuit of a single-particle reinforced FPGA distributed RAM. The read-in time sequence matching circuit comprises an AND gate, a single-particle reinforced trigger, a mirroring single-particle reinforced static random access memory, an n-level delay chain, an n-to-1 multiplexer, an n-bit configuration unit, a phase inverter, a transmission gate, a single-particle transient filter, an either-or selector, as well as a search table single-particle reinforced static random access memory and a configuration unit thereof, wherein WR and EN signals of an FPGA are sequentially processed by the AND gate and the single-particle reinforced trigger, so that gating signals are obtained; the gating signals are processed by a feedback loop consisting of the mirroring single-particle reinforced static random access memory, the n-level delay chain and the n-to-1 multiplexer. The circuit is capable of automatically measuring the needed read-in time of the distributed RAM, ensuring that the read-in width of data into the distributed RAM is adjusted through programming the value of the n-bit configuration unit when a user starts on or turns off the single-particle transient filter in the FPGA, and realizing time sequence matching of reinforced SRAM-type FPGA single-particle design.
Description
Technical Field
The invention belongs to the field of FPGA chip design, and relates to a write-in time sequence matching circuit of a single-particle reinforced FPGA distributed RAM.
Background
When the FPGA is applied in a space environment, space high-energy particles penetrate through the interior of an FPGA device to cause instantaneous current on a circuit node, so that a configuration storage unit is subjected to single-particle upset, and circuits in certain areas can generate local function errors and interconnection line short circuits or open circuits, so that the circuits in the areas cannot work normally. The single-particle reinforced FPGA can reinforce a register and a storage unit which are easy to overturn by using a reinforcement technology under the condition that the normal work of an FPGA circuit is not influenced, so that the difficulty of the storage unit in single-particle overturn is greatly increased, the single-particle reinforced FPGA is more suitable for a severe space radiation environment, and the service life of the single-particle reinforced FPGA is prolonged. Transient current can be caused when single particles hit certain nodes in the circuit, the transient current is much larger than the current of normal work, but the duration is shorter, so that the single particle transient filter can be used for filtering, the single particle reinforced FPGA provides an optional single particle transient filter, the filter can be controlled to be turned on and off according to different using environment programming, and the capability of the single particle FPGA for resisting the single particle transient current is improved.
The single event hardened FPGA includes input-output ports (IOBs), configurable logic modules (CLBs), block memories (BRAMs), programmable interconnect structures (pcram) that connect the modules throughout the chip, configuration memory arrays (CSRAM), configuration logic, and configuration interfaces. As shown in fig. 1, the input/output ports (IOBs) are located around the chip, the Configurable Logic Blocks (CLBs) are arranged in an array inside, the block memories (BRAMs) are interspersed in the Configurable Logic Blocks (CLBs), and the clock modules are distributed at 3 corners. The SRAM type FPGA chip does not have any logic function before configuration, and configuration is completed by loading configuration data specified by a user application into an internal configuration memory array (CSRAM).
The mathematical operations and combinational logic functions implemented in the FPGA are implemented by programmable logic blocks (CLBs) in addition to dedicated logic blocks (e.g., adders, multipliers, etc.) in the FPGA. The CLB may implement common combinational logic and sequential logic functions through configuration, such as 4-input combinational logic, distributed RAM, shift registers, accumulators, and the like. The functions of the distributed RAM and the shift register are common applications of the CLB, the CLB is used for realizing the distributed RAM which is more flexible than the BRAM, so that the design is more flexible and convenient, the CLB is used for realizing the functions of the shift register, compared with the method of using registers to be connected in series, the resources and the wiring logic are more saved, and the CLB is used for realizing the functions of the distributed RAM and the shift register by using a single-particle reinforced static random access memory DICESRAM in an LUT and additional control logic.
Compared with the situation that the values in the SRAM serving as the lookup table function are fixed and are not changed after being written by the configuration logic, the DICESRAM with the functions of the distributed RAM and the shift register needs to be written and updated in real time, and a matching circuit is needed to ensure that the data can be correctly written into the DICESRAM in the least time in the writing process. The distributed RAM function and the shift register function of the CLB share a write-in delay matching mechanism, and the width of data to be input is adjusted through a delay matching circuit. In the CLB of the existing FPGA, a mirror image SRAM in an LUT is adopted to ensure data writing, and the writing completion of the SRAM in the LUT is determined by writing mark signal data into the mirror image SRAM and detecting the change of an output signal of the mirror image SRAM. However, an optional single-particle transient filter circuit is added to an input path of an LUT in a single-particle reinforced FPGA, and a user can turn on or turn off the single-particle transient filter circuit according to actual requirements, so that the DICESRAM time for reaching the single-particle reinforced LUT has 2 choices, but the actual delay can be various due to different processing angles and working conditions, the traditional mirror SRAM can only provide one delay and cannot meet the requirements of the single-particle reinforced FPGA, and the DICESRAM write-in delay in the single-particle reinforced LUT needs to be variably adjusted according to process deviation in the production process of using the single-particle transient filter circuit or the working environment of an actual chip.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the write-in matching circuit overcomes the defects of the prior art, and provides the distributed RAM write-in delay matching circuit of the single-particle reinforced FPGA, so that a user can set the write-in matching delay of the distributed RAM in a programming mode according to the process angle and the using environment of a chip and whether the single-particle transient filter circuit is started, the effective width of data to be input of the distributed RAM is adjusted, and the data can be accurately written into the distributed RAM in the least time under various conditions.
The technical solution of the invention is as follows: a write-in time sequence matching circuit of a single-particle reinforced FPGA distributed RAM comprises an AND gate, a single-particle reinforced trigger, a mirror image single-particle reinforced static random access memory, an n-level delay chain, an n-selection-1 multi-path selector, an n-bit configuration unit, an inverter, a transmission gate, a single-particle transient filter and a configuration unit thereof, an alternative selector and a search form particle reinforced static random access memory, wherein the n value is a positive integer, except the n-bit configuration unit, other parts of the write-in time sequence matching circuit are all positioned in a CLB of an FPGA chip, WR and EN signals of the FPGA are output to the single-particle reinforced trigger through the AND gate, when EN and WR are simultaneously high level, after a clock signal arrives, a Q end of the single-particle reinforced trigger outputs high level, the high level signal is written into the memory from a DI end of the mirror image single-particle reinforced static random access memory, then, n-level delay signals of the signals are obtained from a DO end of the memory to an n-level delay chain, the n-level delay signals are respectively connected to n-selected multi-path selectors, the n-bit configuration unit configures the n-selected multi-path selectors to select 1 signal from the n-level delay signals and output to a reset end of the single-particle reinforced trigger, the high level of the reset end is effective, so that a Q end of the single-particle reinforced trigger 2 is asynchronously reset to a low level, the Q end of the single-particle reinforced trigger is output as a data gating signal, the data gating signal is input to a positive end of a transmission gate and is input to a negative end of the transmission gate through an inverter in an inverted mode, when the data gating signal is high level, the transmission gate is opened, data to be input passes through the transmission gate, when the single-particle transient filter configuration unit is configured to be 0, the data to be input is input to the search form particle reinforced static random access memory through a 0 end of the two-selected one selector, when the configuration unit of the single-particle transient filter is configured as 1, the data to be input is input to the search form particle reinforced static random access memory through the 1 end of the alternative selector after being filtered by the single-particle transient filter.
The n-stage delay chain in the write time sequence matching circuit is formed by connecting n-1 delay units in series, the output of the mirror image single particle reinforced static random access memory is connected to the input end of the 1 st delay unit and is used as the 1 st stage output of the n-stage delay chain, the output end of the m-stage delay unit is connected to the input end of the m +1 th stage delay unit and is used as the m +1 th stage output of the n-stage delay chain, m is a natural number, and m belongs to [2, n-1 ].
The value of n in the write timing matching circuit satisfies the following condition:
wherein,to round up, Tjitter_filterMaximum reduction of data width, T, caused by single-event transient filterdelay_sliceIs the unit delay value of each delay unit of the n-stage delay chain.
The n-to-1 multiplexer consists of n NMOS transistors M1～MnA first inverter, a second inverter and a PMOS transistor Mn+1Composition, i-th NMOS tube MiHas its drain connected to the i-th stage output terminal of the n-stage delay chain 4, has its gate connected to the n-th bit output terminal of the n-bit configuration unit, and has its gate connected to the n-th bit output terminal of the n-bit configuration unit1～MnAre connected to the input of a first inverter, which is connected in series with a second inverter, PMOS tube Mn+1A weak pull-up transistor with drain and gate respectively connected to input and output ends of the first inverter, source connected to power supply VDD, output end of the second inverter being the output of n-to-1 multiplexer, i being natural number, i ∈ [1, n]。
The n-bit configuration unit can be positioned above or below each column of CLBs of the FPGA chip, the ith input ends of n-to-1 multiplexers in the CLBs in the same column are all connected with the ith output end of the n-bit configuration unit, i is a natural number, and i belongs to [1, n ].
The n-bit configuration unit can also be positioned at the left or right of each column of CLBs of the FPGA chip, the ith input ends of n-to-1 multiplexers in the CLBs in the same row are all connected with the ith bit output end of the n-bit configuration unit, i is a natural number, and i belongs to [1, n ].
The n-bit configuration unit can also be positioned in each clock domain of the FPGA chip, the ith input end of the n-to-1 multiplexer in all CLBs in each clock domain is connected with the ith bit output end of the n-bit configuration unit, i is a natural number, and i belongs to [1, n ].
The single-bit configuration unit in the n-bit configuration unit can be composed of a single-particle reinforced static random access memory and an inverter, wherein the output of the single-particle reinforced static random access memory is connected to the input end of the inverter, and the output of the inverter is the output of the single-bit configuration unit.
The single bit configuration unit in the n-bit configuration unit can also be composed of a fuse and an inverter, one end of the fuse is connected to a power ground, the other end of the fuse is connected to the input end of the inverter, and the output of the inverter is the output of the single bit configuration unit.
Compared with the prior art, the invention has the following beneficial effects:
1. by providing the n-bit configuration unit, a user can realize that the write-in matching delay of the distributed RAM can be programmed and adjusted when the single-particle transient filter is turned on or turned off by configuring different configuration values, the width of data to be input is adjusted by the delay matching circuit, so that the data to be stored is correctly written into the distributed RAM, the write-in failure rate of the distributed RAM is reduced, and the maximum data storage rate of the distributed RAM can be obtained by adopting the mirrored DICESRAM to measure the minimum delay required by the normal writing of the data into the DICESRAM in the LUT.
2. By utilizing the distributed RAM write-in time sequence matching circuit, the data write-in time of the distributed RAM of each row, each line or each clock domain of the chip can be changed according to the actual process angle and working environment of the produced chip and whether the single-particle transient filter circuit is started, so that the reliability and the environment applicability of the single-particle reinforced FPGA chip are increased, and the rejection rate of the chip caused by write-in failure of the distributed RAM is reduced.
3. The shared configuration unit saves more area compared with a group of configuration units arranged on each CLB, reduces the trouble of user configuration, and is easier to realize on layout wiring according to the shared configuration unit in rows or columns.
4. The configuration units are shared according to the clock domains, so that the clock cycle of the distributed RAM can be designed more flexibly, the distributed RAM with the single-particle filter started can work in the independent clock domains, the distributed RAM without the single-particle filter started works in different clock domains, and the two clock domains work at different clock frequencies, thereby improving the design flexibility.
5. The single-particle reinforced SRAM can be used as a delay setting storage unit, and the write-in delay time can be adjusted in real time through a dynamic reconfigurable technology when the working environment changes.
Drawings
FIG. 1 is an overall block diagram of a single-particle hardened FPGA;
FIG. 2 is a schematic diagram of a write timing matching circuit according to the present invention;
FIG. 3 is a schematic diagram illustrating the variation of the effective width of data when the delay link is not used;
FIG. 4 is a schematic diagram of the variation of the effective width of data when using a delay link;
FIG. 5 is a schematic diagram of an n-level delay chain circuit according to the present invention;
FIG. 6 is a circuit diagram of an n-level delay chain unit according to the present invention;
FIG. 7 is a schematic diagram of an n-to-1 multiplexer according to the present invention;
FIG. 8 is a diagram illustrating the distribution of configuration units in columns of the write timing matching circuit according to the present invention;
FIG. 9 is a diagram illustrating the distribution of configuration units in rows of the write timing matching circuit according to the present invention;
FIG. 10 is a schematic diagram of the distribution of configuration units of the write timing matching circuit according to the present invention in clock domains;
FIG. 11 is a circuit diagram of a single-bit configuration unit based on a single-event reinforced SRAM,
FIG. 12 is a circuit diagram of a single bit configuration unit based on a fuse structure.
Detailed Description
The invention is described in further detail below with reference to the following figures and specific examples:
fig. 2 shows a write timing matching circuit of a single-particle hardened FPGA distributed random access memory, which can implement programmable distributed RAM data write matching delay control. The data writing matching delay time of different distributed RAMs can be realized by configuring the storage values in the corresponding n-bit configuration units. Different values are written in the n-bit configuration unit through programming, so that the data of the distributed RAM under different process angles, different working environments and the condition that the single-particle transient filter circuit is turned on or turned off can be normally written into a look-up form particle reinforced static random access memory DICESRAM in the LUT within the shortest time. Reliability and environmental applicability of the single-particle reinforced FPGA chip are improved, and rejection rate caused by write failure of the distributed RAM is reduced. The CLB uses the single event hardened sram dicedram in the LUT and additional control logic in the same way to implement the functions of the distributed RAM and shift register, and therefore the invention is equally applicable to shift registers.
As shown in fig. 2, the write timing matching circuit of the single-event hardened FPGA distributed random access memory includes an AND gate AND, a single-event hardened trigger DICEFF, a mirror-image single-event hardened static random access memory mirrordigital ram, an n-level delay chain DL, an n-to-1 multiplexer MUX, an n-bit configuration unit, an inverter INV, a transmission gate TG, a single-event transient filter AND its configuration circuit, an alternative selector MUX2, AND a lookup table-particle hardened static random access memory lutdicedram. The n value is a positive integer, and except the n-bit configuration unit, other parts of the write time sequence matching circuit are all positioned in a CLB of the FPGA chip.
The connection relationship of the write timing matching circuit is as follows: the write signal WR and the enable signal EN are respectively connected to two input ends of an AND gate 1, an output end of the AND gate 1 is connected to a data input end D of a single-event hardened trigger 2, a clock end CLK of the single-event hardened trigger 2 is connected to a global clock, an output end Q of the single-event hardened trigger 2 is connected to an input end DI of a mirror image single-event hardened static random access memory 3, an output end DO of the mirror image single-event hardened static random access memory 3 is connected to an input end of an n-level delay chain 4, an ith output end of the n-level delay chain 4 is connected to an ith input end of an n-to-1 multiplexer 5, i is 1-n, an ith selection end of the multiplexer 5 is connected to an ith output end of an n-bit configuration unit 6 by bit, and an output end of the multiplexer 5 is connected to a reset end of the single-event hardened trigger 2 to form a feedback loop. The output end Q of the single-particle reinforced trigger 2 is also connected to the forward selection end of the transmission gate 8, the input end and the output end of the phase inverter 7 are respectively connected to the forward selection end and the reverse selection end of the transmission gate 8, the DATA signal DATA is connected to the input end of the transmission gate 8, the output end of the transmission gate 8 is divided into two paths, one path is connected to the 0 input end of the one-out-of-two selector 10, the other path is connected to the 1 input end of the one-out-of-two selector 10 through the single-particle transient filter, the selection end of the one-out-of-two selector 10 is connected to the single-particle transient filter configuration unit 12, and the output end of the one-out-of-two.
The working principle of the write timing matching circuit is as follows: EN is an enable signal, when EN is low, the circuit is not enabled, the LUT is not used or functions as a normal lookup table, when EN is high, WR is horizontal, a distributed RAM or shift register read process, which does not require writing data, so the circuit is not used either. The LUT functions as a distributed RAM or a shift register and is in a write state, and the write timing matching circuit is in an operating state only when EN and WR are simultaneously high level. When the matching circuit is in working state, the rising edge of the clock signal is passed through Tclk-qThe Q end of the delayed single-particle reinforced trigger outputs high level, and the high level signal is written into the memory from the DI end of the mirror image single-particle reinforced static random access memory and then passes through TDICESRAMN-level delay signals of the signals are obtained from a DO end of the memory to n-level delay chains, the n-level delay signals are respectively connected to n-to-one multiplexer, the n-bit configuration unit configures the n-to-one multiplexer to select 1 delay signal from the n-level delay signals and output the delay signal to a reset end of the single-particle reinforced trigger, and the delay of the delay signal is TdelaylineThe high level of the reset end is effective, the Q end of the single-particle reinforced trigger is asynchronously reset to the low level by the delayed high level signal, and the delay of the reset process is Tclr-q. The Q end output of the single-particle reinforced trigger is a data gating signal, the data gating signal is input to the positive end of the transmission gate 8 and is input to the negative end of the transmission gate in an inverted mode through the phase inverter 7, when the data gating signal is at a high level, the transmission gate 8 is opened, data to be input pass through the transmission gate, when the single-particle transient filter configuration unit 12 is configured to be 0, the data to be input are input to the search form particle reinforced static random access memory 11 through the 0 end of the two-out-one selector 10, and when the single-particle transient filter is configured to be 0When the unit 12 is configured as 1, the data to be input is filtered by the single-particle transient filter 9 and then input to the search form particle reinforced static random access memory 11 through the 1 end of the alternative selector 10.
The calculation formula of the width of the data strobe signal is as follows:
Tperiod＝TDICESRAM+Tdelayline+Tclr-q(2)
the input data path is opened when the data strobe signal is active, the active time of the data strobe signal determining the period in which the signal is written to the distributed RAM or shift register.
When the DATA DATA is input into the search form particle reinforced static random access memory, the DATA DATA needs to be kept for at least a certain time TreqThe DICESRAM setup/hold conditions are met to ensure that the LUTDICESRAM can be written correctly.
When a user closes the single-particle transient filter, namely the value stored in the configuration unit of the single-particle transient filter is 0, the MUX2 selects the 0 input end, the single-particle transient filter is bypassed, and data passing through the single-particle transient filter is directly input into the search form particle reinforced static random access memory. The mirror image single particle reinforced static random access memory MirrorDICESRAM and the LUTDICESRAM are realized by the same process, the data writing time is basically the same, the mirror image single particle reinforced static random access memory MirrorDICESRAM simulates the writing process of searching the LUTDICESRAM of the form particle reinforced static random access memory, the minimum writing time of the data of the LUTDICESRAM can be written into the MirrorDICESRAM by using a mark signal through a reinforced trigger DICEFF, the mark signal is output and fed back to a reset end of the DICEFF after being written, and the mark bit is cleared to realize automatic measurement. Therefore, when the single-particle transient filter is closed, the minimum effective width of input data is the minimum data writing time required for searching the form particle reinforced static random access memory LUTDICESRAM, and the mirror image single-particle reinforced static random access memory is adopted to realize the minimum data writing timeThe minimum data writing time T can be automatically measuredreqThereby controlling the input data effective width. In order to obtain the maximum data writing rate, T is carried out when the single-particle transient filter is not starteddelaylineCan be set to 0, at which time the minimum width of data writing is Tmin＝TDICESRAM+Tclr-q。
However, when the single-event transient filter is turned on, the input data is filtered by the single-event transient filter, and due to the filtering influence on the data bits, the actual effective width of the data on the data path is reduced, which may cause the address or the enable signal to be switched in the process of writing the data into the DICESRAM, so that the write time actually written into the single DICESRAM does not satisfy the establishment/retention time of the DICESRAM. Therefore, the write timing matching circuit of the invention designs n stages of delay chain introduction TdelaylineAnd increasing delay control on the gating signal to increase the width of data input to the single-particle transient filter, thereby realizing matching delay and data write-in width matching. The method makes up the data width loss caused by the single-particle transient filter, so that the data written into the LUTDICEESRAM can meet the requirement of the setup/hold time. The user can adjust the specific delay in the delay chain through the n-bit configuration unit and the multiplexer, and the dynamic adjustment of the delay is realized according to the requirement of circuit design.
Fig. 3 and 4 show the effective width change of data arriving at the lutdicesam with no delay chain introduced and with delay chain introduced, respectively, with the single event transient filter turned on and off. In the figure, Data represents Data written into the lutdicesam, Addr represents an address of Data stored in the lutdicesam, TG _ EN is a strobe signal, filter of the lutdicesam Data is Data inputted to the lutdicesam when the single-particle transient filter is turned off, and T is a Data minimum write time requirement, as can be seen from fig. 3, after the single-particle transient filter is processed, an effective width of Data becomes T1, T1<T data can not be stably and reliably written into the LUTDICESRAM, and T is introduced in FIG. 4delaylineThe effective width of the gating signal is T2, after the processing of the single-particle transient filter, the effective width of the data is changed into T, the requirement of the minimum write pulse width of the LUTDICESRAM is met, and the data can be reliably written into the LUTDICESRAM.
In the invention, n-bit configuration units are designed for a write-in time sequence matching circuit of a single-particle reinforced FPGA distributed random access memory in a single-particle reinforced FPGA, n is a positive integer, and the value of n meets the following conditions:
the numerical value is comprehensively determined according to the actual circuit requirement, the layout area and the unit delay value of the delay unit. The larger N is, the more configuration units are needed, the larger the required layout area is, the larger the margin configurable by a user is, and N can be as follows as an optimal choice:
wherein,to round up, Tjitter_filterFor maximum reduction of data width, T, caused by single-particle transient filterdelay_sliceIs the delay value of the delay unit in the delay chain. According to the time delay required by the user, the smaller the time delay selected by the user is, the faster the clock rate which can be designed by the user can be, and the faster the read-write rate of the FPGA memory can be under the condition of meeting the minimum time delay. Due to the difference between the processing angle and the working condition of the chip, a chip manufacturer can give a suggested delay value for a user to set when the user starts the single-particle transient filter during the factory test.
Fig. 5 is a schematic design diagram of an n-stage delay chain according to the present invention, where an n-stage delay chain DL of the present invention is formed by connecting n-1 delay units in series, an input of the n-stage delay chain DL is connected to an input terminal of a 1 st delay unit and is used as a 1 st output of the n-stage delay chain, an output terminal of an m-stage delay unit is connected to an input terminal of an m +1 th delay unit and is used as an m +1 th output of the n-stage delay chain, m is a natural number, and m belongs to [2, n-1 ].
There are many kinds of delay units, which may be analog or digital, and fig. 6 is a schematic diagram of a conventional delay unit. The delay unit comprises 2 inverters which are connected in series, or even number of inverters which are connected in series, and the delay value of the delay unit can be calculated to obtain an approximate value by using SPICE software according to the technological parameters and the structure adopted by a chip and the size of a transistor.
As shown in FIG. 7, the n-to-1 multiplexer consists of n NMOS transistors M1～MnA first inverter 13, a second inverter 14 and a PMOS transistor Mn+1Composition, i-th NMOS tube MiIs connected to the i-th stage output of the n-stage delay chain 4, MiIs connected to the nth output terminal M _ SEL [ i ] of the n-bit configuration unit 6]，M1～MnAre connected to the input of a first inverter 13, the first inverter 13 is connected in series with a second inverter 14, a PMOS transistor Mn+1The transistor is a weak pull-up transistor, namely the width-length ratio of the transistor is smaller than that of a PMOS transistor in a normal phase inverter.
When the ith output end M _ SEL [ i ] of the n-stage delay chain]When the voltage is high level, the ith NMOS tube is conducted, MiIs D _ OUT [ i ]]When D _ OUT [ i ]]When the output of the first phase inverter is 1 when the output is 0, the PMOS transistor Mn+1Off, the output of the n-to-1 multiplexer is MiAn output of (d); when D _ OUT [ i ]]When 1, the output of the first inverter is 0, the PMOS transistor Mn+1On, Mn+1Can compensate the threshold loss caused by high level passing through NMOS tube, and make the output of n-to-1 multiplexer be MiThe output of (a) is VDD, and the first inverter and the second inverter are used in pair.
The invention adopts the 13um technology to realize M1～MnHas a length of 0.13um and a width of 2um, Mn+1Is 0.13um long and wideIs 0.2um, and the NMOS pipe length is 0.13um in the phase inverter 13, and is wide to be 9.8um, and the PMOS pipe length is 0.13um, and is wide to be 4.6um, and the NMOS pipe length is 0.13um in the phase inverter 14, and is wide 4.8um, and the PMOS pipe length is 0.13um, and is wide 9.6 um.
Fig. 8 is a schematic diagram of the distribution of configuration units in columns according to the present invention, and only the CLB module is shown in the diagram for simplicity. All distributed RAM write-in guarantee circuits in each row of CLBs in the FPGA chip share one n-bit configuration unit, as shown in the figure, the n-bit configuration unit is positioned below each row of CLBs in the FPGA chip, the ith input ends of n-to-1 multiplexers 5 in the same row of CLBs are all connected with the ith bit output end of an n-bit configuration unit 6, i is a natural number, and i belongs to [1, n ]. Configuration units may also be placed above each column CLB of the FPGA chip.
Fig. 9 is a schematic diagram of the configuration units in the present design distributed in rows, and only the CLB module is shown in the diagram for simplicity. All distributed RAM write-in guarantee circuits in each row of CLBs in the FPGA chip share n configuration units. The n-bit configuration unit 6 is positioned at the right side of each column of CLBs of the FPGA chip, the ith input end of the n-to-1 multiplexer 5 in the CLBs in the same row is connected with the ith bit output end of the n-bit configuration unit 6, i is a natural number, and i belongs to [1, n ]. Configuration cells may also be placed to the right of each column CLB of the FPGA chip.
The shared configuration unit saves more area compared with a group of configuration units arranged on each CLB, reduces the trouble of user configuration, and is easier to realize on layout wiring according to rows or columns.
Fig. 10 is a schematic diagram of the distribution of configuration units in the present design according to clock domains, and only the CLB module is shown in the diagram for simplicity. Distributed RAM write-in guarantee circuits in all CLBs of each clock domain in the FPGA chip share n configuration units. The n-bit configuration unit 6 is located in each clock domain of the FPGA chip, the ith input end of the n-to-1 multiplexer 5 in all CLBs in each clock domain is connected with the ith bit output end of the n-bit configuration unit 6, i is a natural number, and i is 1-n.
By adopting the arrangement mode of the configuration units shown in fig. 10, the widths of the write data of the lookup table particle reinforced static random access memories LUTDICESRAM in all CLBs in the same clock domain are consistent, and when a user configures a large-capacity random access memory, the CLBs in the same clock domain are selected to form the configuration unit, so that the consistency of the read-write performance of the obtained memory unit is good. Meanwhile, the configuration units are shared according to the clock domains, so that the clock cycle of the distributed RAM can be designed more flexibly, the distributed RAM with the single-particle filter started can work in the independent clock domains, the distributed RAM without the single-particle filter started works in different clock domains, and the two clock domains work at different clock frequencies, so that the design flexibility is improved.
Fig. 11 and 12 show schematic diagrams of a single-bit configuration unit of two n-bit configuration units. The single-bit configuration unit shown in fig. 11 is composed of a single-particle reinforced static random access memory, namely, a digital random access memory 15 and an inverter 16, wherein a word line wb, a complement wb _ b of the word line and a write enable en of the digital random access memory are connected to a configuration bus, an output bit _ b of the digital random access memory is connected to an input end of the inverter 16, an output end of the inverter 16 is output of the single-bit configuration unit, and the size of the inverter 16 is larger than that of a normal inverter so as to have larger driving capacity and needs to be selected according to the size of a subsequent load.
The single-bit configuration unit shown in fig. 12 is composed of a fuse 17 and an inverter 18, one end of the fuse 17 is connected to a power ground, the other end is connected to an input end of the inverter 18, an output of the inverter 18 is an output of the single-bit configuration unit, and the size of the inverter 18 is larger than that of a normal inverter so as to have a larger driving capability. The size needs to be selected according to the size of the subsequent load.
The configuration unit in fig. 11 is easier to implement, can be configured repeatedly, and can share configuration logic and paths with other modules, but the radiation resistance of the configured single particle is weaker than that in fig. 12, and the configuration unit in fig. 12 has stronger resistance to the single particle, but needs additional programming circuits, and can not be programmed repeatedly.
Those skilled in the art will appreciate that those matters not described in detail in this specification are well known in the art.
Claims (9)
1. A write-in time sequence matching circuit of a single-particle reinforced FPGA distributed RAM is characterized in that: the single-particle reinforced single-particle time sequence matching circuit comprises an AND gate (1), a single-particle reinforced trigger (2), a mirror image single-particle reinforced static random access memory (3), an n-level delay chain (4), an n-1-selected multiplexer (5), an n-bit configuration unit (6), an inverter (7), a transmission gate (8), a single-particle transient filter (9), a configuration unit (12) of the single-particle transient filter, an alternative selector (10) and a search form particle reinforced static random access memory (11), wherein the n value is a positive integer, except the n-bit configuration unit (6), other parts of the write time sequence matching circuit are all located in a CLB of an FPGA chip, WR and EN signals of the FPGA are in and output to the single-particle reinforced trigger (2) through the AND gate (1), when EN and WR are high electric levels at the same time, a clock signal arrives, a Q end of the single-particle reinforced trigger (2) outputs a high electric level, and the high electric level signal is written into the memory from a DI end of, then n-level delay signals of the signals are obtained from a DO end of the memory to an n-level delay chain (4), the n-level delay signals are respectively connected to an n-selected multiplexer (5), the n-bit configuration unit (6) configures the n-selected multiplexer to select 1 signal from the n-level delay signals and output to a reset end of a single-particle reinforced trigger (2), the high level of the reset end is effective, so that a Q end of the single-particle reinforced trigger (2) is asynchronously reset to the low level, the Q end of the single-particle reinforced trigger (2) outputs a data strobe signal, the data strobe signal is input to a positive end of a transmission gate (8) and is simultaneously input to a negative end of the transmission gate in an inverted mode through an inverter (7), when the data strobe signal is high level, the transmission gate (8) is opened, data to be input pass through the transmission gate, and when a single-particle transient filter configuration unit (12) is configured to be 0, the data to be input is input into a search form particle reinforced static random access memory (11) through the 0 end of the one-out-of-two selector (10), and when the single-particle transient filter configuration unit (12) is configured to be 1, the data to be input is filtered by the single-particle transient filter (9) and then is input into the search form particle reinforced static random access memory (11) through the 1 end of the one-out-of-two selector (10).
2. The write timing matching circuit of the single-particle reinforced FPGA distributed RAM according to claim 1, characterized in that: the n-stage delay chain (4) is formed by connecting n-1 delay units in series, the output of the mirror image single-particle reinforced static random access memory (3) is connected to the input end of the 1 st delay unit and is used as the 1 st output of the n-stage delay chain (4), the output end of the m-stage delay unit is connected to the input end of the m +1 th delay unit and is used as the m +1 th output of the n-stage delay chain, m is a natural number, and m belongs to [2, n-1 ].
3. The write timing matching circuit of the single-particle reinforced FPGA distributed RAM according to claim 1, characterized in that: the n value satisfies the following condition:
wherein,to round up, Tjitter_filterFor the maximum reduction value of the data width, T, caused by the single-event transient filterdelay_sliceA unit delay value for each delay unit of the n-level delay chain.
4. The write timing matching circuit of the single-particle reinforced FPGA distributed RAM according to claim 1, characterized in that: the n-to-1 multiplexer consists of n NMOS transistors M1～MnA first inverter (13), a second inverter (14) and a PMOS transistor Mn+1Composition, i-th NMOS tube MiIs connected to the i-th stage output terminal of the n-stage delay chain (4), the gate of Mi is connected to the n-th bit output terminal of the n-bit configuration unit (6), M1～MnAre connected to the input of a first inverter (13), the first inverter (13) is connected in series with a second inverter (14), a PMOS transistor Mn+1A weak pull-up transistor with drain and gate respectively connected to input and output ends of the first inverter, source connected to power supply VDD, output end of the second inverter (14) being output of n-to-1 multiplexer, i being natural number, i ∈ [1, n]。
5. The write timing matching circuit of the single-particle reinforced FPGA distributed RAM according to claim 1, characterized in that: the n-bit configuration unit (6) is positioned above or below each column of CLBs of the FPGA chip, the ith input end of the n-to-1 multiplexer (5) in the same column of CLBs is connected with the ith bit output end of the n-bit configuration unit (6), i is a natural number and belongs to [1, n ].
6. The write timing matching circuit of the single-particle reinforced FPGA distributed RAM according to claim 1, characterized in that: the n-bit configuration unit (6) is positioned at the left or right of each column of CLBs of the FPGA chip, the ith input end of the n-to-1 multiplexer (5) in the CLBs in the same row is connected with the ith bit output end of the n-bit configuration unit (6), i is a natural number, and i belongs to [1, n ].
7. The write timing matching circuit of the single-particle reinforced FPGA distributed RAM according to claim 1, characterized in that: the n-bit configuration unit (6) is positioned in each clock domain of the FPGA chip, the ith input end of the n-to-1 multiplexer (5) in all CLBs in each clock domain is connected with the ith bit output end of the n-bit configuration unit (6), i is a natural number, and i belongs to [1, n ].
8. The write timing matching circuit of the single-particle reinforced FPGA distributed RAM according to claim 1, characterized in that: the n-bit configuration unit (6) is composed of n single-bit configuration units, each single-bit configuration unit is composed of a single-particle reinforced static random access memory (15) and an inverter (16), the output of the single-particle reinforced static random access memory (15) is connected to the input end of the inverter (16), and the output of the inverter (16) is the output of the single-bit configuration unit.
9. The write timing matching circuit of the single-particle reinforced FPGA distributed RAM according to claim 1, characterized in that: the n-bit configuration unit (6) is composed of n single-bit configuration units, each single-bit configuration unit is composed of a fuse (17) and a phase inverter (18), one end of each fuse (17) is connected to a power ground, the other end of each fuse is connected to the input end of the phase inverter (18), and the output of the phase inverter (18) is the output of the single-bit configuration unit.
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