CN105761746A - Read-in time sequence matching circuit of single-particle reinforced FPGA distributed RAM - Google Patents

Abstract

The present invention proposes a write timing matching circuit for a single-particle hardened FPGA distributed RAM, which includes an AND gate, a single-particle hardened trigger, a mirrored single-particle hardened static random access memory, an n-level delay chain, and more than one selected from n Way selector, n-bit configuration unit, inverter, transmission gate, single-event transient filter, two-to-one selector, lookup table particle hardened static random access memory and its configuration unit. The WR and EN signals of the FPGA pass through the AND gate and the single-event hardened flip-flop in turn to obtain the gating signal, which is composed of the mirror single-event hardened static random access memory, n-level delay chain and n-to-1 multiplexer feedback loop. This circuit can automatically measure the writing time required by the distributed random access memory, and allows the user to adjust the width of data written to the distributed RAM by programming the value of the n-bit configuration unit when the single event transient filter in the FPGA is turned on or off. , to achieve timing matching after SRAM-type FPGA single-particle design reinforcement.

Description

A write timing matching circuit for single event hardened FPGA distributed RAM

technical field

The invention belongs to the field of FPGA chip design, and relates to a write timing matching circuit of a single particle reinforced FPGA distributed RAM.

Background technique

When FPGA is applied in the space environment, space high-energy particles passing through the interior of the FPGA device will cause instantaneous current on the circuit nodes, causing single-event flipping of the configuration storage unit, and local functional errors, interconnection wire short circuit or open circuit in some areas of the circuit. Circuits in the area will not function properly. Single-event-hardened FPGAs can use reinforcement technology to reinforce registers and storage units that are prone to flipping without affecting the normal operation of the FPGA circuit, greatly increasing the difficulty of single-event flipping in storage cells, making single-event-hardened FPGAs more adaptable to harsh conditions The space radiation environment, prolong its service life. When a single particle hits some nodes in the circuit, it may cause a transient current. The transient current is much larger than the normal working current, but the duration is relatively short, so it can be filtered out by using a single particle transient filter. , The single event hardened FPGA provides an optional single event transient filter, which can be programmed to control the opening and closing of the filter according to different usage environments, which improves the single event FPGA's ability to resist single event transient currents.

Single-event hardened FPGAs include input-output ports (IOBs), configurable logic blocks (CLBs), block memory (BRAM), programmable interconnects that connect modules throughout the chip, configuration memory arrays (CSRAM), configuration logic, and configuration interfaces . As shown in Figure 1, the input and output ports (IOB) are located around the chip, the configurable logic block (CLB) is arranged in an array internally, the block memory (BRAM) is interspersed in the configurable logic block (CLB), and the clock module is distributed on 3 corners. The SRAM FPGA chip does not have any logic functions before configuration, and the configuration is completed by loading the configuration data specified by the user application into the internal configuration memory array (CSRAM).

Except the dedicated logic modules in FPGA (such as adder, multiplier, etc.), the mathematical operations and combinational logic functions implemented in FPGA are realized through programmable logic modules (CLB). CLB can be configured to implement common combinational logic and sequential logic functions, such as 4-input combinational logic, distributed RAM, shift register, accumulator, etc. Among them, distributed RAM and shift register functions are common applications of CLB. Using CLB to implement distributed RAM is more flexible than BRAM, making the design more flexible and convenient. Using CLB to implement shift register functions saves resources and costs more than using registers in series. Routing logic, CLB is to use single particle reinforced static random access memory DICESRAM in LUT and additional control logic to realize distributed RAM and shift register functions.

Compared with the case where the value in SRAM as a lookup table function is fixed and does not change after being written by configuration logic, the data in DICESRAM with distributed RAM and shift register function needs to be written and updated in real time, and a matching circuit is needed to Guarantee that this writing process can correctly write data into DICESRAM in the least time. The distributed RAM function of the CLB and the shift register function share the write delay matching mechanism, and the width of the data to be input is adjusted through the delay matching circuit. In the CLB of the existing FPGA, the SRAM in a LUT is mirrored to ensure data writing. By writing the flag signal data to the mirrored SRAM, and detecting the output signal change of the mirrored SRAM, it is determined that the writing of the SRAM in the LUT is completed. However, an optional single-event transient filter circuit is added to the input path of the LUT in the single-event hardened FPGA. Users can turn on or off the single-event transient filter circuit according to actual needs, so the time to reach the DICESRAM of the single-event hardened LUT is shorter. There are 2 options, but due to the different processing angles and working conditions, the actual delay will be various. The traditional mirrored SRAM can only provide one delay, which cannot meet the needs of single-particle hardened FPGA. Single-particle hardened LUT The DICESRAM write delay needs to be variably adjusted according to whether the single event transient filter circuit is used, the deviation of the process in the production process, and the working environment of the actual chip.

Contents of the invention

The technical problem of the present invention is: to overcome the deficiencies of the prior art, to provide a distributed RAM writing delay matching circuit for single particle reinforced FPGA, so that the user can check the chip according to the process angle of the chip, the use environment and whether to open the single particle instant The state filter circuit is used to program and set the write matching delay of the distributed RAM, adjust the effective width of the data to be input in the distributed RAM, and ensure that the data can be accurately written into the distributed RAM in the least time under various conditions.

The technical solution of the present invention is: a write timing matching circuit of a single-event hardened FPGA distributed RAM, including an AND gate, a single-event hardened flip-flop, a mirrored single-event hardened static random access memory, n-level delay chains, n Select 1 multiplexer, n-bit configuration unit, inverter, transmission gate, single-event transient filter and its configuration unit, two-choice selector, lookup table particle hardened static random access memory, and the value of n is Positive integer, except for the n-bit configuration unit, other parts of the write timing matching circuit are located in the CLB of the FPGA chip. The WR and EN signals of the FPGA are output to the single event hardened flip-flop through the AND gate. When EN and WR are simultaneously When it is high level, after the clock signal arrives, the Q terminal of the single event hardened flip-flop outputs a high level, and the high level signal is written into the memory from the DI terminal of the mirrored single event hardened SRAM, and then output from the DO terminal of the memory To the n-level delay chain to obtain the n-level delay signal of the signal, the n-level delay signal is respectively connected to the n-choice multiplexer, and the n-level configuration unit configures the n-choice one-way multiplexer from the n-level Select one signal from the delay signal and output it to the reset terminal of the single event reinforcement trigger. The output of the Q terminal is a data strobe signal. The data strobe signal is input to the positive terminal of the transmission gate, and is input to the negative terminal of the transmission gate through the inversion of the inverter. When the data strobe signal is high, the transmission gate is opened. , the data to be input passes through the transmission gate. When the single event transient filter configuration unit is configured as 0, the data to be input is input to the lookup table particle-hardened static random access memory through the 0 terminal of the two-choice selector. When the single event transient When the filter configuration unit is configured as 1, the input data is input to the lookup table particle-hardened static random access memory through terminal 1 of the one-two selector after being filtered by the single-event transient filter.

The n-level delay chain in the write timing matching circuit is composed of n-1 delay units connected in series, and the output of the mirror image single particle reinforced static random access memory is connected to the input end of the first delay unit, and simultaneously serves as an n-level The first stage output of the delay chain, the output end of the mth stage delay unit is connected to the input end of the m+1 stage delay unit, and at the same time it is used as the m+1 stage output of the n stage delay chain, m is a natural number , m∈[2,n-1].

The value of n in the write timing matching circuit satisfies the following conditions:

in, To round up, T _{jitter_filter} is the maximum reduction value of the data width caused by the single event transient filter, and T _{delay_slice} is the unit delay value of each delay unit of the n-level delay chain.

The n-to-1 multiplexer is composed of n NMOS transistors M ₁ ~M _n , the first inverter, the second inverter and a PMOS transistor M _n+1 , and the drain of the i-th NMOS transistor M _i is connected to To the output end of the i-th stage of the n-stage delay chain 4, the gate of Mi is connected to the n-th output end of the n-bit configuration unit, and the source stages of M ₁ ~ M _n are all connected to the input end of the first inverter , the first inverter and the second inverter are connected in series, the PMOS transistor Mn ₊₁ is a weak pull-up transistor, its drain and gate are respectively connected to the input and output of the first inverter, and the source Connected to the power supply VDD, the output terminal of the second inverter is the output of an n-to-1 multiplexer, i is a natural number, i∈[1,n].

The n-bit configuration unit can be located above or below each CLB column of the FPGA chip. The i-th input terminal of the n-to-1 multiplexer in the same column CLB is connected to the i-bit output terminal of the n-bit configuration unit, and i is a natural number. i∈[1,n].

The n-bit configuration unit can also be located on the left or right side of each column CLB of the FPGA chip, and the i-th input terminal of the n-to-1 multiplexer in the same row of CLBs is connected to the i-th output terminal of the n-bit configuration unit, i is a natural number, i∈[1,n].

The n-bit configuration unit can also be located in each clock domain of the FPGA chip, and the i-th input terminal of the n-to-1 multiplexer in all CLBs in each clock domain is connected to the i-th output terminal of the n-bit configuration unit, and i is a natural number , i∈[1,n].

The single-bit configuration unit in the n-bit configuration unit may be composed of a single-event reinforced SRAM and an inverter, the output of the single-event reinforced SRAM is connected to the input of the inverter, and the output of the inverter is a single-bit configuration output of the unit.

The single-bit configuration unit in the n-bit configuration unit can also be composed of a fuse and an inverter. One end of the fuse is connected to the power ground, and the other end is connected to the input terminal of the inverter. The output of the inverter is a single-bit configuration. output of the unit.

Compared with the prior art, the present invention has the following beneficial effects:

1. The present invention provides an n-bit configuration unit, so that users can program and adjust the write matching delay of distributed RAM when the single-event hardened FPGA is turned on or off when the single-event transient filter is turned on or off by configuring different configuration values, Adjust the width of the data to be input through the delay matching circuit, so that the data to be stored can be correctly written into the distributed RAM, reducing the write failure rate of the distributed RAM, and the mirrored DICESRAM can be used to measure the normal writing of data The minimum delay required to enter the DICESRAM in the LUT obtains the maximum data storage rate of the distributed RAM.

2. Using the distributed RAM write timing matching circuit of the present invention, it is possible to change the timing of each column, each row or each clock domain of the chip according to the actual process angle of the produced chip, the working environment and whether to open the single event transient filter circuit. Distributed RAM data writing time increases the reliability and environmental applicability of single-particle hardened FPGA chips, and at the same time reduces the chip scrap rate caused by distributed RAM writing failures.

3. Compared with setting a group of configuration units for each CLB, the shared configuration unit of the present invention saves more area, and at the same time reduces the trouble of user configuration, and at the same time, sharing configuration units by row or column is also easier to implement in layout wiring.

4. The present invention shares the configuration unit according to the clock domain, so that the clock cycle of the distributed RAM can be designed more flexibly, so that the distributed RAM with the single event filter enabled can work in an independent clock domain, and the distributed RAM with the single event filter not enabled can work in an independent clock domain. The distributed RAM works in different clock domains, and the two clock domains work in different clock frequencies, which improves design flexibility.

5. The present invention can use a single particle reinforced SRAM as a delay setting storage unit, and can adjust the write delay time in real time through the dynamic reconfigurable technology when the working environment changes.

Description of drawings

Figure 1 is the overall block diagram of a single particle hardened FPGA;

FIG. 2 is a schematic diagram of a write timing matching circuit of the present invention;

Fig. 3 is a schematic diagram of data effective width variation when no delay link is used;

Fig. 4 is a schematic diagram of data effective width variation when using a delay link;

Fig. 5 is the circuit diagram of n-stage delay chain circuit of the present invention;

Fig. 6 is the unit circuit diagram of n-level delay chain unit of the present invention;

Fig. 7 is the schematic diagram of n selecting 1 multiplexer of the present invention;

FIG. 8 is a schematic diagram of the configuration units of the write timing matching circuit according to the present invention;

FIG. 9 is a schematic diagram of row-by-row distribution of configuration units of the write timing matching circuit of the present invention;

FIG. 10 is a schematic diagram of the configuration units of the write timing matching circuit according to the clock domain according to the present invention;

Fig. 11 is a schematic diagram of a single-bit configuration unit circuit based on single-event hardened SRAM,

FIG. 12 is a schematic diagram of a single-bit configuration unit circuit based on a fuse structure.

detailed description

Below in conjunction with accompanying drawing and specific embodiment the present invention is described in further detail:

Figure 2 shows a single event hardened FPGA distributed random access memory write timing matching circuit, which can realize programmable distributed RAM data write matching delay control. By configuring the storage value in the corresponding n-bit configuration unit, the data writing matching delay time of different distributed RAMs can be realized. Write different values in the n-bit configuration unit by programming to ensure that the data of the distributed RAM can be written normally in the shortest time under different process angles, different working environments and the single event transient filter circuit is turned on or off Lookup forms in LUT Particle-hardened SRAM DICESRAM. It increases the reliability and environmental applicability of single-particle hardened FPGA chips, and at the same time reduces the scrap rate caused by distributed RAM write failures. CLB utilizes the single-event hardened static random access memory DICESRAM in the LUT and additional control logic to realize the functions of the distributed RAM and the shift register in the same way, therefore, the present invention is also applicable to the shift register.

As shown in Figure 2, the write timing matching circuit of single event hardened FPGA distributed random access memory includes AND gate AND, single event hardened trigger DICEFF, mirror single event hardened static random access memory MirrorDICESRAM, n-level delay chain DL, n-to-1 multiplexer MUX, n-bit configuration unit, inverter INV, transmission gate TG, single-event transient filter and its configuration circuit, two-to-one selector MUX2, lookup table particle reinforced static random access memory LUTDICESRAM . The n value is a positive integer, except for the n-bit configuration unit, other parts of the write timing matching circuit are located in the CLB of the FPGA chip.

The connection relationship of the write timing matching circuit is as follows: the write signal WR and the enable signal EN are respectively connected to the two input terminals of the AND gate 1, and the output terminal of the AND gate 1 is connected to the data input terminal D of the single event hardened flip-flop 2, The clock terminal CLK of the single event hardened flip-flop 2 is connected to the global clock, the output terminal Q of the single event hardened flip-flop 2 is connected to the input port DI of the mirrored single event hardened SRAM 3, and the mirrored single event hardened SRAM The output terminal DO of 3 is connected to the input terminal of n-level delay chain 4, and the i-th output end of n-level delay chain 4 is connected to the i-th input end of n-choice 1 multiplexer 5, i=1 ~ n, the i-th selection end of the multiplexer 5 is connected bit by bit to the i-th output end of the n-bit configuration unit 6, and the output end of the multiplexer 5 is connected to the reset end of the single event reinforcement trigger 2, forming feedback loop. The output terminal Q of the single event reinforcement trigger 2 is also connected to the forward selection terminal of the transmission gate 8, the input terminal and the output terminal of the inverter 7 are respectively connected to the forward selection terminal and the reverse selection terminal of the transmission gate 8, and the data signal DATA Connected to the input end of the transmission gate 8, the output end of the transmission gate 8 is divided into two paths, one path is connected to the 0 input end of the one-to-two selector 10, and the other path is connected to the one-to-two selector 10 through a single event transient filter 1 input terminal, the selection terminal of the one-two selector 10 is connected to the single event transient filter configuration unit 12, and the output terminal of the one-two selector 10 is connected to the input terminal of the lookup table particle hardened SRAM 11.

The working principle of the write timing matching circuit is: EN is the enable signal, when EN is low level, the circuit is not enabled, LUT is not used or used as a general lookup table function, when EN is high level, WR is level For distributed RAM or shift register read process, it is not necessary to write data, so this circuit is also unused. Only when EN and WR are high at the same time, the LUT is used as a distributed RAM or a shift register, and it is in a writing state, and the writing timing matching circuit is in a working state. When the matching circuit is in the working state, after the rising edge of the clock signal arrives, the Q terminal of the single event reinforcement flip-flop outputs a high level after a delay of T _clk-q , and the high level signal is from the mirror image single event reinforcement static random Access the DI terminal of the memory to write into the memory, and then output from the DO terminal of the memory to the n-level delay chain through T _DICESRAM to obtain the n-level delay signal of the signal, and the n-level delay signal is respectively connected to the n-selection multiplexer An n-bit configuration unit configures an n-choice multiplexer to select a delayed signal from the n-level delayed signals and output it to the reset terminal of the single event reinforcement trigger. The delay of the delayed signal is T _delayline , the reset terminal is active at high level, and the delayed high-level signal makes the Q terminal of the single event reinforcement trigger asynchronously reset to low level, and the delay of the reset process is T _clr-q . The Q terminal output of the single event reinforcement flip-flop is a data strobe signal, and the data strobe signal is input to the positive terminal of the transmission gate 8, and is input to the negative terminal of the transmission gate through the inversion of the inverter 7 at the same time. When the pass signal is at a high level, the transmission gate 8 is opened, and the data to be input passes through the transmission gate. When the configuration unit 12 of the single event transient filter is configured as 0, the data to be input is input to the search channel via the terminal 0 of the selector 10. Form particle reinforced static random access memory 11, when the single event transient filter configuration unit 12 is configured as 1, the input data is filtered by the single event transient filter 9 and then input to the Lookup Form Particle Hardened SRAM 11.

The formula for calculating the width of the above data strobe signal is:

T _period ＝T _DICESRAM +T _delayline +T _clr-q (2)

The input data path is opened when the data strobe signal is valid, and the valid time of the data strobe signal determines the cycle in which the signal is written into the distributed RAM or the shift register.

When the data DATA is input into the lookup form particle-reinforced static random access memory, it needs to be kept for at least a certain time T _req to meet the establishment/holding conditions of DICESRAM and ensure that it can be correctly written into LUTDICESRAM.

When the user closes the single event transient filter, that is, the value stored in the single event transient filter configuration unit is 0, MUX2 selects the 0 input terminal, the single event transient filter is bypassed, and passes through the single event transient filter The data is input directly into the lookup form particle-hardened SRAM. Since Mirror DICESRAM and LUTDICESRAM are implemented with the same process, the data writing time is basically the same. Mirror DICESRAM simulates the write process of lookup form particle-hardened SRAM LUTDICESRAM, LUTDICESRAM The minimum writing time of the data can be written into MirrorDICESRAM by using a flag signal through a reinforcement trigger DICEFF, after the flag signal is written, the output is fed back to the reset terminal of DICEFF, and the flag bit is cleared to realize automatic measurement. In the present invention, WR and The AND signal of EN is used as the flag signal. Therefore, when the single-event transient filter is turned off, the minimum effective width of the input data is the minimum data writing time required by the lookup form particle-hardened SRAM LUTDICESRAM, which can be automatically measured by using a mirrored single-event-hardened SRAM The minimum data writing time T _req is obtained, so as to control the effective width of the input data. In order to obtain the maximum data writing rate, T _delayline can be set to 0 when the single event transient filter is not enabled, and at this time, the minimum data writing width is T _min =T _DICESRAM +T _clr-q .

However, when the single event transient filter is turned on, the input data is filtered through the single event transient filter. Due to the filtering effect on the data bit, the actual effective width of the data on the data path will be reduced, which may cause address or The enable signal is switched during the process of writing data into DICESRAM, so that the writing time actually written into a single DICESRAM does not meet the setup/hold time of DICESRAM. Therefore, an n-stage delay chain is designed in the timing matching circuit of the present invention to introduce T _delayline to increase the delay control of the strobe signal so that the data width input to the single event transient filter becomes larger, thereby realizing matching delay and data writing to match the input width. This method makes up for the loss of data width caused by the single-event transient filter, so that the data written into LUTDICESRAM can meet the setup/hold time requirements. The user can adjust the size of the specific delay in the delay chain through the n-bit configuration unit and the multiplexer, and realize the dynamic adjustment of the delay according to the needs of the circuit design.

Fig. 3 and Fig. 4 show the change of the effective width of the data arriving at LUTDICESRAM when the delay link is not introduced and the delay link is introduced, and the single event transient filter is turned on and off. In the figure, Data represents the data written into LUTDICESRAM, Addr represents the address where the data is stored in LUTDICESRAM, TG_EN is the strobe signal, FilteroffLUTDICESRAMDatain is the data input to LUTDICESRAM when the single event transient filter is turned off, and FilteronLUTDICESRAMDatain is the single event transient filter off When the data is input to LUTDICESRAM, T is the minimum data write time requirement. It can be seen from Figure 3 that after the processing of the single event transient filter, the effective width of the data becomes T1, and the data of T1<T cannot be stable Reliably write into LUTDICESRAM, T _delayline is introduced in Figure 4, the effective width of the strobe signal is T2, after processing by the single event transient filter, the effective width of the data becomes T, which meets the minimum write pulse width of LUTDICESRAM Requirements, data can be reliably written in LUTDICESRAM.

The present invention designs an n-bit configuration unit for the write timing matching circuit of the single-particle reinforced FPGA distributed random access memory in the single-particle reinforced FPGA, where n is a positive integer, and the value of n satisfies the following conditions:

The value is comprehensively determined according to actual circuit requirements, layout area and unit delay value of the delay unit. The larger N is, the more configuration units are required, the larger the required layout area, and the larger the user-configurable margin. As the optimal choice, n can be:

in, To round up, T _{jitter_filter} is the maximum data width reduction caused by the single event transient filter, and T _{delay_slice} is the delay value of the delay unit in the delay chain. The user can select the required delay. When the minimum delay is met, the smaller the delay selected by the user, the faster the clock rate can be designed by the user, and the faster the read and write rate of the FPGA memory. Due to the difference in the processing angle and chip working conditions, the chip manufacturer will give a suggested delay value for the user to set when turning on the single event transient filter when testing at the factory.

Fig. 5 is the schematic diagram of the design of the n-level delay chain in the present invention, the n-level delay chain DL of the present invention is made up of n-1 time delay units in series, and the input of the n-level delay chain DL is connected to the first The input end of one delay unit is simultaneously used as the first-stage output of the n-stage delay chain, and the output end of the m-th stage delay unit is connected to the input end of the m+1-th stage delay unit, and simultaneously serves as an n-stage delay chain The m+1th stage output of the time chain, m is a natural number, m∈[2,n-1].

There are many kinds of delay units, which can be analog or digital. Figure 6 is a schematic diagram of a commonly used delay unit. It consists of 2 inverters in series, or can be designed as an even number of inverters in series. The delay value of the delay unit can be calculated using SPICE software to obtain an approximate value according to the process parameters, structure and transistor size used by the chip.

As shown in FIG. 7, the n-to-1 multiplexer is composed of n NMOS transistors M ₁ -M _n , a first inverter 13, a second inverter 14 and a PMOS transistor M _n+1 . The drain of the i NMOS transistor M _i is connected to the i-th output end of the n-level delay chain 4, and the gate of M _i is connected to the n-th output end M_SEL[i] of the n-bit configuration unit 6, M ₁ ~ The source stages of _Mn are all connected to the input end of the first inverter 13, the first inverter 13 is connected in series with the second inverter 14, and the PMOS transistor Mn ₊₁ is a weak pull-up transistor, that is, its width and length The width-to-length ratio of the PMOS tube in the normal inverter is smaller.

When the i-th output terminal M_SEL[i] of the n-level delay chain is high level, the i-th NMOS transistor is turned on, and the output of M _i is D_OUT[i]. When D_OUT[i] is 0, the first The output of the inverter is 1, the PMOS tube M _n+1 is turned off, and the output of the n-to-1 multiplexer is the output of M _i ; when D_OUT[i] is 1, the output of the first inverter is 0, and the PMOS The tube M _n+1 is turned on, and M _n+1 can compensate the threshold loss caused by the high level passing through the NMOS tube, so that the output of the n-to-1 multiplexer is Mi and the output of M _i is VDD, and the first inverter and The second inverter is used as a pair.

The present invention adopts the .13um process to realize that the length of M1～ _Mn is 0.13um and the width is 2um, the length of Mn _{+1 is} 0.13um and the width is 0.2um, and the length of the NMOS tube in the inverter 13 is 0.13um and the width is 9.8um. um, the PMOS tube is 0.13um long and 4.6um wide, the NMOS tube in the inverter 14 is 0.13um long and 4.8um wide, and the PMOS tube is 0.13um long and 9.6um wide.

FIG. 8 is a schematic diagram of the distribution of configuration units in columns according to the present invention. For simplicity, only the CLB module is drawn in the figure. All distributed RAM write guarantee circuits in each column of CLB in the FPGA chip share an n-bit configuration unit, as shown in the figure, the n-bit configuration unit is located under each column of CLB in the FPGA chip, and n selects 1 multiplex in the same column of CLB The i-th input end of the device 5 is connected to the i-th output end of the n-bit configuration unit 6, i is a natural number, i∈[1,n]. The configuration unit can also be placed above each CLB column of the FPGA chip.

Figure 9 is a schematic diagram of the configuration units in this design distributed in rows. For simplicity, only the CLB module is drawn in the figure. All distributed RAM write guarantee circuits in each row of CLBs in the FPGA chip share n configuration units. The n-bit configuration unit 6 is located on the right side of each column CLB of the FPGA chip, and the i-th input terminal of the n-choice 1 multiplexer 5 in the same row of CLBs is connected to the i-th output terminal of the n-bit configuration unit 6, and i is a natural number , i∈[1,n]. The configuration unit can also be placed on the right side of each column CLB of the FPGA chip.

Compared with setting a group of configuration cells for each CLB, sharing configuration cells saves more area, and also reduces the trouble of user configuration. At the same time, sharing configuration cells by row or column is also easier to implement in layout and wiring.

Figure 10 is a schematic diagram of the distribution of the configuration units in this design according to the clock domain. For simplicity, only the CLB module is drawn in the figure. The distributed RAM writing guarantee circuits in all CLBs of each clock domain in the FPGA chip share n configuration units. The n-bit configuration unit 6 is located in each clock domain of the FPGA chip, and the i-th input terminal of the n-choice 1 multiplexer 5 in all CLBs in each clock domain is connected to the i-th output terminal of the n-bit configuration unit 6, i is a natural number, i=1~n.

Using the arrangement of configuration units shown in Figure 10, the data width written in the lookup table particle-hardened static random access memory LUTDICESRAM in all CLBs in the same clock domain is consistent. When configuring a large-capacity random access memory, the user selects CLBs in the same clock domain. The read and write performance of the obtained memory unit is relatively good. At the same time, sharing the configuration unit according to the clock domain can make the clock cycle of the distributed RAM more flexible, so that the distributed RAM with the single event filter enabled can work in an independent clock domain, and the distributed RAM without the single event filter enabled The RAM works in different clock domains, and the two clock domains work in different clock frequencies, which improves design flexibility.

FIG. 11 and FIG. 12 show schematic diagrams of single-bit configuration units of two kinds of n-bit configuration units. The single-bit configuration unit shown in Figure 11 is composed of a single-particle hardened SRAM DICESRAM15 and an inverter 16, and the word line wb of the DICESRAM, the complement code wb_b of the word line, and the write enable en are connected to the configuration bus , the output bit_b of the DICESRAM is connected to the input terminal of the inverter 16, the output terminal of the inverter 16 is the output of the single-bit configuration unit, and the size of the inverter 16 is larger than that of a normal inverter, so as to have a larger Drive capacity, the size needs to be selected according to the size of the load behind it.

The single-bit configuration unit shown in FIG. 12 is composed of a fuse 17 and an inverter 18. One end of the fuse 17 is connected to the power ground, and the other end is connected to the input of the inverter 18. The output of the inverter 18 is For the output of the single-bit configuration unit, the size of the inverter 18 is larger than that of a normal inverter in order to have a greater driving capability. The size needs to be selected according to the size of the subsequent load.

The configuration unit in Figure 11 is easier to implement, can be reconfigured, and can share configuration logic and paths with other modules, but the anti-radiation ability of configuring single events is weaker than that in Figure 12, and the configuration unit in Figure 12 is resistant to single events The ability is stronger, but additional programming circuits are required, and repeated programming is not possible.

The contents not described in detail in this specification belong to the well-known technologies of those skilled in the art.

Claims (9)

1. A write-in time sequence matching circuit of a single-particle reinforced FPGA distributed RAM is characterized in that: the single-particle reinforced single-particle time sequence matching circuit comprises an AND gate (1), a single-particle reinforced trigger (2), a mirror image single-particle reinforced static random access memory (3), an n-level delay chain (4), an n-1-selected multiplexer (5), an n-bit configuration unit (6), an inverter (7), a transmission gate (8), a single-particle transient filter (9), a configuration unit (12) of the single-particle transient filter, an alternative selector (10) and a search form particle reinforced static random access memory (11), wherein the n value is a positive integer, except the n-bit configuration unit (6), other parts of the write time sequence matching circuit are all located in a CLB of an FPGA chip, WR and EN signals of the FPGA are in and output to the single-particle reinforced trigger (2) through the AND gate (1), when EN and WR are high electric levels at the same time, a clock signal arrives, a Q end of the single-particle reinforced trigger (2) outputs a high electric level, and the high electric level signal is written into the memory from a DI end of, then n-level delay signals of the signals are obtained from a DO end of the memory to an n-level delay chain (4), the n-level delay signals are respectively connected to an n-selected multiplexer (5), the n-bit configuration unit (6) configures the n-selected multiplexer to select 1 signal from the n-level delay signals and output to a reset end of a single-particle reinforced trigger (2), the high level of the reset end is effective, so that a Q end of the single-particle reinforced trigger (2) is asynchronously reset to the low level, the Q end of the single-particle reinforced trigger (2) outputs a data strobe signal, the data strobe signal is input to a positive end of a transmission gate (8) and is simultaneously input to a negative end of the transmission gate in an inverted mode through an inverter (7), when the data strobe signal is high level, the transmission gate (8) is opened, data to be input pass through the transmission gate, and when a single-particle transient filter configuration unit (12) is configured to be 0, the data to be input is input into a search form particle reinforced static random access memory (11) through the 0 end of the one-out-of-two selector (10), and when the single-particle transient filter configuration unit (12) is configured to be 1, the data to be input is filtered by the single-particle transient filter (9) and then is input into the search form particle reinforced static random access memory (11) through the 1 end of the one-out-of-two selector (10).

2. The write timing matching circuit of the single-particle reinforced FPGA distributed RAM according to claim 1, characterized in that: the n-stage delay chain (4) is formed by connecting n-1 delay units in series, the output of the mirror image single-particle reinforced static random access memory (3) is connected to the input end of the 1 st delay unit and is used as the 1 st output of the n-stage delay chain (4), the output end of the m-stage delay unit is connected to the input end of the m +1 th delay unit and is used as the m +1 th output of the n-stage delay chain, m is a natural number, and m belongs to [2, n-1 ].

3. The write timing matching circuit of the single-particle reinforced FPGA distributed RAM according to claim 1, characterized in that: the n value satisfies the following condition:

wherein,to round up, T_{jitter_filter}For the maximum reduction value of the data width, T, caused by the single-event transient filter_{delay_slice}A unit delay value for each delay unit of the n-level delay chain.

4. The write timing matching circuit of the single-particle reinforced FPGA distributed RAM according to claim 1, characterized in that: the n-to-1 multiplexer consists of n NMOS transistors M₁～M_nA first inverter (13), a second inverter (14) and a PMOS transistor M_n+1Composition, i-th NMOS tube M_iIs connected to the i-th stage output terminal of the n-stage delay chain (4), the gate of Mi is connected to the n-th bit output terminal of the n-bit configuration unit (6), M₁～M_nAre connected to the input of a first inverter (13), the first inverter (13) is connected in series with a second inverter (14), a PMOS transistor M_n+1A weak pull-up transistor with drain and gate respectively connected to input and output ends of the first inverter, source connected to power supply VDD, output end of the second inverter (14) being output of n-to-1 multiplexer, i being natural number, i ∈ [1, n]。

5. The write timing matching circuit of the single-particle reinforced FPGA distributed RAM according to claim 1, characterized in that: the n-bit configuration unit (6) is positioned above or below each column of CLBs of the FPGA chip, the ith input end of the n-to-1 multiplexer (5) in the same column of CLBs is connected with the ith bit output end of the n-bit configuration unit (6), i is a natural number and belongs to [1, n ].

6. The write timing matching circuit of the single-particle reinforced FPGA distributed RAM according to claim 1, characterized in that: the n-bit configuration unit (6) is positioned at the left or right of each column of CLBs of the FPGA chip, the ith input end of the n-to-1 multiplexer (5) in the CLBs in the same row is connected with the ith bit output end of the n-bit configuration unit (6), i is a natural number, and i belongs to [1, n ].

7. The write timing matching circuit of the single-particle reinforced FPGA distributed RAM according to claim 1, characterized in that: the n-bit configuration unit (6) is positioned in each clock domain of the FPGA chip, the ith input end of the n-to-1 multiplexer (5) in all CLBs in each clock domain is connected with the ith bit output end of the n-bit configuration unit (6), i is a natural number, and i belongs to [1, n ].

8. The write timing matching circuit of the single-particle reinforced FPGA distributed RAM according to claim 1, characterized in that: the n-bit configuration unit (6) is composed of n single-bit configuration units, each single-bit configuration unit is composed of a single-particle reinforced static random access memory (15) and an inverter (16), the output of the single-particle reinforced static random access memory (15) is connected to the input end of the inverter (16), and the output of the inverter (16) is the output of the single-bit configuration unit.

9. The write timing matching circuit of the single-particle reinforced FPGA distributed RAM according to claim 1, characterized in that: the n-bit configuration unit (6) is composed of n single-bit configuration units, each single-bit configuration unit is composed of a fuse (17) and a phase inverter (18), one end of each fuse (17) is connected to a power ground, the other end of each fuse is connected to the input end of the phase inverter (18), and the output of the phase inverter (18) is the output of the single-bit configuration unit.