CN103580678A - High-performance lookup table circuit based on FGPA - Google Patents
High-performance lookup table circuit based on FGPA Download PDFInfo
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Abstract
The invention belongs to the technical field of integrated circuits and particularly relates to a high-performance lookup table circuit based on an FGPA. According to the high-performance lookup table circuit based on the FGPA, a logic gate unit and a transmission gate are mixed, and for instance, a four-input lookup table circuit comprises three inverters, two CMOS transmission gates and one NAND gate. According to the high-performance lookup table circuit based on the FGPA, four levels of pass transistors on a critical path of the circuit are reduced to two levels, the time delay of the critical path is greatly shortened; the low-threshold CMOS transmission gate is applied, unsymmetrical time delay caused by threshold loss is avoided, and therefore the difficulty of design of a follow-up sequential circuit is reduced; the size of each PMOS transistor and the size of each NMOS transistor in the CMOS pass transistors are identical, so that the area of partial PMOS transistors in the pass transistors is reduced by 50%. By the adoption of the high-performance lookup table circuit based on the FGPA, through the improvement of the structure of the circuit, the speed performance, the power consumption performance and the area performance are remarkably improved, and therefore programmable logic resources supported by lookup table logic can be more widely applied.
Description
Technical field
The invention belongs to FPGA circuit engineering field, be specifically related to a kind of high performance lut circuits.
Technical background
As the FPGA that is widely used in integrated circuit (IC) design and checking, due to its powerful programmable features and constantly add the IP kernels such as Block RAM, DSP, High-speed I/O and PLL and powerful alternative function system gradually, make it in integrated circuit (IC) design field from now on, occupy very important status.But along with constantly reducing of process, the scale of digital integrated circuit is increasing, the requirement of functional integration and the requirement of chip performance are also more and more higher.For can to function more comprehensively, design that performance requirement is higher verifies, FPGA is through the development of decades, there is larger variation in structure, scale has also increased several orders of magnitude, range of application is also more and more wider, the design of FPGA is when pursuing more perfect storage, computing, communication function, to the continuous lifting of performance another challenge can not be ignored really.
FPGA a kind ofly can configure inside programming point according to bitstream information and realizes the array that various combinations or sequential logical circuit occur and formed Arbitrary Input Function, and can realize the unit of various function generating functions, programmable logic block, the just core of this field programmable gate array and important component part.Typical programmable logic block (hereinafter to be referred as CLB) is mainly comprised of three parts: lut circuits, flip-flop circuit and other combinational logic circuits.Flip-flop circuit is the timing unit providing for realizing sequential logic, and other combinational logics are to coordinate lut circuits to realize some to input less combinational logic, such as, 2 inputs and logic, 2 input XOR.Realizing the unit of the function generating function of input is arbitrarily lut circuits.So, the optimization to lut circuits, in the lifting of the aspect properties such as speed, power consumption, area to realizing the FPGA important in inhibiting of high-speed low-power-consumption.
Lut circuits consists of 4 to 6 user's inputs, corresponding decoding circuit and SRAM memory point conventionally, can realize combinational logic or the ROM function of 4 to 6 input 1 outputs arbitrarily; In the development in FPGA past, the structure of look-up table has several, and Fig. 1 is the look-up table configuration of one three input, be a kind of by NMOS transfer tube, made eight select one decoder, the quantity of transfer tube is that the topological structure with binary tree launches.Along with look-up table fan-in object increases, its circuit scale will be by 2
krule sharply increases, and therefore high input lut circuits does not have practical value.Fig. 2 is the look-up table configuration based on CMOS transfer tube, can avoid the threshold value loss problem of using the transmission of NMOS single tube to cause, but Q end will drive very large load (programmable interconnection) conventionally, so the inverter of afterbody is done very greatly conventionally, add the cmos transmission gate of multi-stage cascade, make the load of inverter of SRAM output very large, the time delay of increase circuit so greatly.
Summary of the invention
The object of the present invention is to provide and a kind ofly can reduce lut circuits progression, reduce critical path time delay, reduce leakage current, thereby solve the lut circuits based on FPGA of the problems such as rise and fall time is asymmetric.
Lut circuits based on FPGA provided by the invention (is (the Configuration Logic Block of programmable logic block in FPGA, abbreviation CLB) lut circuits in), by improving the structure of lut circuits, the CMOS transfer tube that adopts low threshold value pipe to form, and optimize metal-oxide-semiconductor size, reduce lut circuits progression, reduce critical path time delay, reduce leakage current, the problems such as solution rise and fall time is asymmetric, make lut circuits in FPGA can support more high performance Design of Digital Circuit and checking.
The lut circuits of the present invention's design, adopts gate unit and CMOS transfer tube Mixed Design.The 4 input look-up tables of take are example, one-level inverter, first-level buffer device, the low threshold value transfer tube of two-stage CMOS and a NAND gate, consist of.As shown in Figure 3, the buffer I16 consisting of two inverters is arranged at before look-up table output Q, and one-level inverter I0 ~ I15 is arranged at the anti-phase output of the data storage cell SRAM of look-up table
~
after; After two-stage CMOS low threshold value transfer tube C0 ~ C15 and C16 ~ C19 are arranged at respectively one-level inverter I0 ~ I15 and before buffer I16.The output of one-level NAND gate is arranged at the control end of the low threshold value transfer tube of CMOS.
If: P0, P1～P15 represent the storing value of 16 SRAM programmed point, but the value of programmed point is all the end of oppisite phase output from SRAM,
~
; A1, A2, A3, A4 represent 4 function inputs of look-up table, and A1B, A2B, A3B, A4B represent 4 function input A1, A2, A3, the A4 negate signal afterwards of look-up table successively, and Q is look-up table output; The decoding of input A1 ~ A4 is adopted to the mode of two decodings, be function input A1, the A2 of look-up table, and the combination of the signal A1B after negate and A2B realizes the control to the low threshold value transfer tube of first order CMOS circuit C0 ~ C15 through one with door, function input A3, the A4 of look-up table, and the combination of the signal A3B after negate and A4B realizes the control to the low threshold value transfer tube of second level CMOS circuit C16 ~ C19 through one with door; Wherein, the low threshold value transfer tube of CMOS C0 ~ C19 is formed in parallel by low threshold value NMOS pipe and PMOS, and NMOS manages and PMOS pipe is measure-alike.Finally, the value of SRAM storage is through end of oppisite phase output
~
, through 1 grade of inverter I0 ~ I15 and 1 grade of buffer I16(buffer I16, by 2 inverters, formed), 2 grades of low threshold value transfer tube of CMOS C0 ~ C15, C16 ~ C19, finally arrive look-up table output Q.
In circuit design, considered a kind of method for designing that the design is expanded to the lut circuits of band control function.While there is an asserts signal in lut circuits, traditional method is as added one to realize set function with door E1 at Q end in Fig. 5, the design changes an inverter I15 in Fig. 3 into one as the NAND gate D1 in Fig. 4, and asserts signal is joined to an input with door.As long as thereby A4 ~ A1 is input as complete 1 R1=1, R5=1 gating C15 and two CMOS transfer tubes of C16, asserts signal SET can carry out set to output Q like this.The design has reduced the time delay of critical path upper level with door than the method for traditional access control signal of Fig. 5.
the speed-optimization explanation of design
In the design's lut circuits, for the consideration of speed-optimization, there is the following aspects:
(1) on circuit structure, changed traditional mode to 4 input step-by-step decodings, the present invention has become 4 inputs by the mode of two decodings.Specifically, traditional decoded mode is according to A1, to 0/1 the value of A4, to control one by one the switch of transfer tube, altogether needs to carry out 4 grades of transfer tube decodings and completes corresponding function and occur.The present invention considers two bit address simultaneously, carries out once preliminary decoding, then the value after preliminary decoding is controlled to CMOS transfer tube by NAND gate, realizes the selection of SRAM data, and at this moment, data only need to be exportable through two-stage CMOS transfer tube.Thereby the transfer tube in critical path is reduced to 2 grades from 4 grades, and this has reduced critical path time delay, has improved the speed of look-up table.
(2) when circuit design, consider that cmos transmission gate driving force when multi-stage cascade can exist very large problem, thus the data transmission bauds of having influence on.So need to insert inverter to improve driving force in critical path, but inverter is to change signal polarity, so must insert in pairs.The delay causing in order to reduce multistage inverter, the present invention, in the output of SRAM memory point, adopts from end of oppisite phase output,
arrive
output.If from the positive terminal output (P0 is to P15) of SRAM memory point, just need 4 grades of inverters on data transfer path on the contrary.By exporting such design from SRAM end of oppisite phase, can reduce the one-level inverter of one-level data transfer path, improve the time delay of data from memory cell to Q, the speed of look-up table is accomplished to certain raising.
(3), in circuit design, considering that inverter can solve a little less than CMOS transfer tube driving force in this problem, also has an expanded application, comparison diagram 4 and Fig. 5.While there is an asserts signal in lut circuits, if by asserts signal separately with one-level and door/or door join Q end, can increase like this time delay of one-level critical path.Consideration of the present invention, if enable signal will be incorporated to some inverters, can select to be so incorporated to first inverter, because, the first-level buffer device of Q end is owing to considering that subsequent conditioning circuit may have large load, what size can design so is larger, so be incorporated to the increase greatly that afterbody buffer can cause area.And the load of first order inverter is very little, size is also just very little, made so one with door or or goalkeeper's control signal be incorporated to, not only can reduce one-level gate leve and postpone, also can accomplish that area only has a small amount of increase.Just, when asserts signal is effective, 4 inputs just should be transferred to Q end to guarantee asserts signal for certain fixing value.
(4) when the design of CMOS transfer tube, the present invention adopts low threshold value pipe, and transfer of data time delay can be accomplished certain reducing like this, but is but very little on the impact of electric leakage, can not cause the increase of power consumption.
power consumption and the area-optimized explanation of design
In the design's lut circuits, the consideration of the optimization of power consumption and area is had to the following aspects:
(1) on circuit structure, with Fig. 2 contrast, the present invention selects CMOS transfer tube circuit rather than NMOS transfer tube, the problem that the power consumption of having avoided the asymmetric problem of signal lag that caused by the threshold value loss of NMOS transfer tube and electric leakage to cause increases.
(2) in size design, in general, the PMOS size of CMOS transfer tube can be 2 ~ 3 times of NMOS pipe, so that the rising and falling time of circuit keeps symmetrical, but can increase widely like this chip area of look-up table.Because Q end has added first-level buffer device I16, as Fig. 3, we can guarantee the AXIALLY SYMMETRIC PROBLEMS of the rise and fall time of circuit, and the size of PMOS and NMOS is accomplished the same large.The great like this area that reduces look-up table.
technique effect
the present invention, by improving the method for the structure of lut circuits, the CMOS transfer tube that adopts low threshold value pipe formation and optimization metal-oxide-semiconductor size, has designed a kind of high-performance lut circuits.In speed, under 65nm SMIC technique, the time delay of this lut circuits can reach only has 0.22ns; Under 250MHZ operating frequency, dynamic drain current can only have 82.5uA.On area, the optimization to transistor size, makes PMOS manage shared area reducing 30% to 50%.
Accompanying drawing explanation
Fig. 1 tri-input look-up table configuration.
The look-up table configuration of Fig. 2 based on CMOS transfer tube.
Fig. 3 look-up table configuration of the present invention.
Fig. 4 asserts signal embeds the look-up table configuration of inverter.
Fig. 5 asserts signal adds the look-up table configuration of independent one-level gate.
Fig. 6 SRAM memory cell structure.
Embodiment
The 4 input look-up tables of take are example, as Fig. 3, by control the switch of cmos transmission gate to the logical value of A4 tetra-bit address by A1, make SRAM hold Q end to occur a guiding path, thus the functional value of the required realization of Q end output.
In principle, 16 SRAM programmed point have just formed the truth table of any 4 input combinational logics.One the 4 input XOR of look-up tables'implementation of take is example, and the storage information of 4 input messages and 16 programmed point is as table 1, and when effective A1 inputs to A4, Q just exports the value of the memory point of corresponding SRAM.
In FPGA, the function implementation procedure of look-up table is as follows:
First, at FPGA, download in the process of bit stream, these 16 memory points of the look-up table that will can use design by word line and bit line write, and SRAM memory cell structure is as Fig. 6.
After download completes, as Fig. 3,16 values that the truth table of function to be achieved is being stored at this moment step-by-step of sram cell, the positive output end of sram cell be P0 to P15, the reversed-phase output of sram cell is
arrive
.
At this moment, at A1 ~ A4 end, add different values, can cause opening different CMOS transfer tubes, thereby Q end is by the value of the SRAM on the CMOS pipe path, place of output conducting.For example, in Fig. 3, when A1A2A3A4=0011, R1=R2=R3=0, R4=1, this opens the CMOS transfer tube of being controlled by R4, thereby
value and
value can pass first order CMOS transfer tube.Due to A3A4=11, thus R6=R7=R8=0, R5=1, this opens the CMOS transfer tube of being controlled by R5, will pass the first order
value pass to last two-stage inverter and finally arrive Q end output, and due to R8=0, the CMOS transfer tube that R8 controls is closed, and makes by first order transfer tube
value can not arrive Q end output.So just realized a look-up table logic.
In addition, if need to add the logic of the expanded functions such as asserts signal in circuit, Fig. 5 has illustrated the traditional approach that adds set function in circuit.And method of the present invention is, as Fig. 4, change first inverter on data path into a NAND gate.When asserts signal is effectively when (0 is effective), 4 input A1 of look-up table are set to 1 entirely to the value of A4,, by the path gating at asserts signal place, data output end Q is set to 1.So just realized the look-up table logic of supporting the expanded functions such as set.Table 1 is 4 input XOR and programmed point SRAM value.
table 1
| Memory cell | Storing value | Effectively A4-A1 input |
| SRAM0(P0) | 0 | 0000 |
| SRAM1(P1) | 1 | 0001 |
| SRAM2(P2) | 1 | 0010 |
| SRAM3(P3) | 0 | 0011 |
| SRAM4(P4) | 1 | 0100 |
| SRAM5(P5) | 0 | 0101 |
| SRAM6(P6) | 0 | 0110 |
| SRAM7(P7) | 1 | 0111 |
| SRAM8(P8) | 1 | 1000 |
| SRAM9(P9) | 0 | 1001 |
| SRAM10(P10) | 0 | 1010 |
| SRAM11(P11) | 1 | 1011 |
| SRAM12(P12) | 0 | 1100 |
| SRAM13(P13) | 1 | 1101 |
| SRAM14(P14) | 1 | 1110 |
| SRAM15(P15) | 0 | 1111 |
Claims (1)
1. the high-performance lut circuits based on FPGA, it is characterized in that adopting gate unit and CMOS transfer tube Mixed Design, for 4 input look-up tables, by one-level inverter, first-level buffer device, the low threshold value transfer tube of two-stage CMOS and a NAND gate, formed; Wherein, described first-level buffer device (I16) consists of two inverters, is arranged at before look-up table output Q; One-level inverter (I0 ~ I15), is arranged at the anti-phase output of the data storage cell SRAM of look-up table
~
after; The low threshold value transfer tube of two-stage CMOS (C0 ~ C15 and C16 ~ C19) be arranged at respectively after one-level inverter (I0 ~ I15) and buffer (I16) front; The output of one-level NAND gate is arranged at the control end of the low threshold value transfer tube of CMOS;
If: P0, P1～P15 represent the storing value of 16 SRAM programmed point, but the value of programmed point is all the end of oppisite phase output from SRAM,
~
; A1, A2, A3, A4 represent 4 function inputs of look-up table, and A1B, A2B, A3B, A4B represent 4 function input A1, A2, A3, the A4 negate signal afterwards of look-up table successively, and Q is look-up table output; The decoding of 4 input A1 ~ A4 is adopted to the mode of two decodings, it is first, second function input (A1, A2) of look-up table, and the combination of the signal (A1B and A2B) after negate realizes the control to the low threshold value transfer tube of first order CMOS circuit (C0 ~ C15) through one with door, the the 3rd, the 4th function input (A3, A4) of look-up table, and the combination of the signal (A3B and A4B) after negate realizes the control to the low threshold value transfer tube of second level CMOS circuit (C16 ~ C19) through one with door; Wherein, the low threshold value transfer tube of CMOS (C0 ~ C19) is to be formed in parallel by low threshold value NMOS pipe and PMOS, and NMOS manages and PMOS pipe is measure-alike; The value of SRAM storage is through end of oppisite phase output
~
, through one-level inverter (I0 ~ I15) and first-level buffer device (I16), 2 grades of low threshold value transfer tubes of CMOS (C0 ~ C15, C16 ~ C19), finally arrive look-up table output Q.
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| CN106815381A (en) * | 2015-11-30 | 2017-06-09 | 中国科学院电子学研究所 | The mapping method of logical node in sparse look-up table and FPGA |
| CN106815381B (en) * | 2015-11-30 | 2019-10-18 | 中国科学院电子学研究所 | The mapping method of logical node in sparse look-up table and FPGA |
| CN108370251A (en) * | 2016-01-13 | 2018-08-03 | 阿尔特拉公司 | Power gating lut circuits |
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| CN106357265A (en) * | 2016-09-19 | 2017-01-25 | 中国电子科技集团公司第五十八研究所 | Small-area high-speed six-input searching table structure |
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| CN111600597A (en) * | 2020-06-19 | 2020-08-28 | 成都华微电子科技有限公司 | Ultra-low power consumption lookup table circuit |
| CN111934670A (en) * | 2020-08-17 | 2020-11-13 | 电子科技大学 | FPGA (field programmable Gate array) framework of quasi-N lookup table |
| CN112234959A (en) * | 2020-10-09 | 2021-01-15 | 成都华微电子科技有限公司 | FPGA high-performance interconnection circuit |
| CN112733474A (en) * | 2020-12-15 | 2021-04-30 | 西安国微半导体有限公司 | Netlist-level circuit area optimization method based on AND gate inverter diagram and storage medium |
| CN112733474B (en) * | 2020-12-15 | 2023-12-22 | 西安国微半导体有限公司 | Netlist-level circuit area optimization method based on AND gate inverter diagram and storage medium |
| CN113971159A (en) * | 2021-10-28 | 2022-01-25 | 山东芯慧微电子科技有限公司 | Programmable logic block based on improved lookup table structure |
| CN113971159B (en) * | 2021-10-28 | 2024-02-20 | 山东芯慧微电子科技有限公司 | Programmable logic block based on improved lookup table structure |
| CN117634383A (en) * | 2023-12-26 | 2024-03-01 | 苏州异格技术有限公司 | Critical path delay optimization method, device, computer equipment and storage medium |
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