CN103580678A - High-performance lookup table circuit based on FGPA - Google Patents

Abstract

The invention belongs to the technical field of integrated circuits, in particular to an FPGA-based high-performance look-up table circuit. The present invention adopts the hybrid design of logic gate unit and transmission gate; taking the 4-input look-up table circuit as an example, it is composed of three inverters, 2 CMOS transmission gates and a NAND gate. The present invention reduces the transmission tube on the critical path of the circuit from 4 stages to 2 stages, which greatly reduces the delay of the critical path; adopts a low threshold CMOS transmission gate to avoid the delay asymmetry caused by the threshold loss, thereby reducing the impact on the subsequent Difficulty in sequential circuit design; the size of the PMOS and NMOS tubes in the CMOS transmission tube is designed to be the same, so that the area of the PMOS tube in the transmission tube is reduced by 50%. Through the improvement of the circuit structure, the present invention obviously improves the performance in three aspects of speed, power consumption and area, so that the programmable logic resources supported by the look-up table logic can be more widely used.

Description

A High Performance Lookup Table Circuit Based on FPGA

technical field

The invention belongs to the technical field of FPGA circuits, and in particular relates to a high-performance look-up table circuit. the

technical background

As an FPGA widely used in integrated circuit design and verification, due to its powerful programmable features and the continuous addition of IP cores such as Block RAM, DSP, high-speed IO, and PLL, the gradually powerful alternative functional system makes its integration in the future The field of circuit design occupies a pivotal position. However, with the continuous reduction of process size, the scale of digital integrated circuits is getting larger and larger, and the requirements for functional integration and chip performance are also getting higher and higher. In order to verify designs with more comprehensive functions and higher performance requirements, after decades of development, the FPGA structure has undergone major changes, the scale has also increased by several orders of magnitude, and the application range has become wider and wider. While pursuing more perfect storage, computing, and communication functions, the continuous improvement of performance is another challenge that cannot be ignored.

FPGA is a unit that can configure internal programming points according to bit stream information to realize arbitrary input function generation and form an array of various combinations or sequential logic circuits, and can realize various function generation functions. Programmable logic blocks, positive It is the core and important part of this field programmable gate array. A typical programmable logic block (hereinafter referred to as CLB) is mainly composed of three parts: look-up table circuit, flip-flop circuit and other combinational logic circuits. The flip-flop circuit is a sequential unit provided for the realization of sequential logic, while other combinational logics cooperate with the look-up table circuit to realize some combinational logic with fewer inputs, such as 2-input AND logic, 2-input XOR logic. The unit that realizes the function generation function of any input is a look-up table circuit. Therefore, the optimization of the look-up table circuit and the improvement of various performances in terms of speed, power consumption, and area are of great significance to the realization of high-speed and low-power FPGAs.

The look-up table circuit is usually composed of 4 to 6 user inputs, corresponding decoding circuits and SRAM storage points, which can realize any combinational logic or ROM function of 4 to 6 inputs and 1 output; in the past development of FPGA, the look-up table There are several structures. Figure 1 shows a three-input lookup table structure, which is a one-of-eight decoder made of NMOS transmission tubes. The number of transmission tubes is expanded in a binary tree topology. With the increase of the number of input terminals of the look-up table, its circuit scale will increase sharply according to the law of 2 ^k , so the high-input look-up table circuit does not have practical value. Figure 2 shows the look-up table structure based on CMOS transmission tube, which can avoid the threshold loss problem caused by the use of NMOS single-transistor transmission, but usually the Q terminal needs to drive a large load (programmable interconnection), so the last stage of inversion The inverter is usually made very large, coupled with the multi-stage cascaded CMOS transmission gates, the load of the inverter output by the SRAM is very large, which will greatly increase the delay of the circuit.

Contents of the invention

The purpose of the present invention is to provide a FPGA-based look-up table circuit that can reduce the number of stages of the look-up table circuit, reduce the delay of the critical path, and reduce the leakage current, thereby solving problems such as rising and falling time asymmetry.

The FPGA-based look-up table circuit provided by the present invention (that is, the look-up table circuit in the programmable logic block (Configuration Logic Block, CLB for short) in the FPGA) improves the structure of the look-up table circuit and adopts a CMOS transmission tube composed of a low-threshold tube. , and optimize the size of the MOS tube to reduce the number of look-up table circuit stages, reduce the delay of the critical path, reduce the leakage current, and solve the problems of asymmetric rise and fall times, so that the look-up table circuit in the FPGA can support higher performance digital circuit design And verification. the

～

后；两级CMOS低阈值传输管C0~C15和C16~C19分别设置于一级反相器I0~I15后和缓冲器I16前。一级与非门输出设置于CMOS低阈值传输管的控制端。 The look-up table circuit designed by the present invention adopts a hybrid design of logic gate units and CMOS transmission tubes. Taking the 4-input look-up table as an example, it consists of a first-level inverter, a first-level buffer, two-level CMOS low-threshold transmission transistors, and a NAND gate. As shown in Figure 3, the buffer I16 composed of two inverters is set before the output terminal Q of the look-up table, and the first-stage inverters I0~I15 are set at the inverting output of the data storage unit SRAM of the look-up table

~

rear; the two-stage CMOS low-threshold transmission tubes C0~C15 and C16~C19 are respectively arranged after the first-stage inverters I0~I15 and before the buffer I16. The output of the primary NAND gate is set at the control end of the CMOS low-threshold transmission tube.

～；A1、A2、A3、A4代表查找表的4个函数输入端，A1B、A2B、A3B、A4B依次代表查找表的4个函数输入端A1、A2、A3、A4取反之后的信号，Q是查找表输出端；对输入A1~A4的译码采用两位译码的方式，即查找表的函数输入端A1、A2，以及取反之后的信号A1B和A2B的组合经过一个与门实现对第一级CMOS低阈值传输管电路C0~C15的控制，查找表的函数输入端A3、A4，以及取反之后的信号A3B和A4B的组合经过一个与门实现对第二级CMOS低阈值传输管电路C16~C19的控制；其中，CMOS低阈值传输管C0~C19是由低阈值NMOS管和PMOS并联而成，并且NMOS管和PMOS管尺寸相同。最后，SRAM存储的值经过反相端输出～，经过1级反相器I0~I15和1级缓冲器I16（缓冲器I16由2个反相器组成），2级CMOS低阈值传输管C0~C15、C16~C19，最终到达查找表输出端Q。 Suppose: P0, P1~P15 represent the storage values of 16 SRAM programming points, but the values of the programming points are all output from the inverting end of the SRAM, that is

~ ; A1, A2, A3, A4 represent the 4 function input terminals of the look-up table, A1B, A2B, A3B, A4B represent the signals after the inversion of the 4 function input terminals A1, A2, A3, A4 of the look-up table in turn, Q is The output terminal of the lookup table; the decoding of the input A1~A4 adopts a two-bit decoding method, that is, the function input terminals A1, A2 of the lookup table, and the combination of the signals A1B and A2B after inversion are realized through an AND gate. The control of the first-level CMOS low-threshold transmission tube circuit C0~C15, the combination of the function input terminals A3 and A4 of the look-up table, and the inverted signals A3B and A4B are realized through an AND gate to the second-level CMOS low-threshold transmission tube circuit Control of C16~C19; among them, CMOS low-threshold transmission tubes C0~C19 are formed by parallel connection of low-threshold NMOS tubes and PMOS tubes, and the sizes of NMOS tubes and PMOS tubes are the same. Finally, the value stored in SRAM is output through the inverting terminal ~ , through 1-stage inverters I0~I15 and 1-stage buffer I16 (buffer I16 is composed of 2 inverters), 2-stage CMOS low-threshold transmission tubes C0~C15, C16~C19, and finally reach the output of the lookup table Q.

In the circuit design, a design method of expanding this design into a look-up table circuit with control function is considered. When a set signal appears in the look-up table circuit, the traditional method is to add an AND gate E1 at the Q terminal as shown in Figure 5 to realize the set function, but this design is to change an inverter I15 in Figure 3 into a As shown in the NAND gate D1 in Figure 4, the set signal is added to an input end of the AND gate. In this way, as long as the inputs of A4~A1 are all 1s so that R1=1 and R5=1 select the two CMOS transmission tubes C15 and C16, then the set signal SET can set the output terminal Q. Compared with the traditional method of adding control signals in Figure 5, this design reduces the delay of the first-level AND gate on the critical path.

Design speed optimization instructions

In the look-up table circuit of this design, the following aspects are considered for speed optimization:

(1) In terms of circuit structure, the traditional bit-by-bit decoding method for 4-bit input is changed, and the present invention changes to a two-bit decoding method for 4-bit input. Specifically, the traditional decoding method is to control the switches of the transmission tubes one by one according to the 0/1 values of A1 to A4, and a total of 4 stages of transmission tube decoding are required to complete the corresponding function generation. However, the present invention considers two addresses at the same time, uses the NAND gate to carry out a preliminary decoding, and then controls the CMOS transmission tube with the value after the preliminary decoding to realize the selection of SRAM data. At this time, the data only needs to go through two stages The CMOS transmission tube can be output. Thus, the transmission pipe on the critical path is reduced from 4 stages to 2 stages, which reduces the critical path delay and improves the speed of the look-up table. the

输出。相反如果从SRAM存储点的正相端输出（P0到P15）的话，则数据传输路径上就需要4级反相器。通过从SRAM反相端输出这样的设计，可以减少一级数据传输路径的一级反相器，提高数据从存储单元到Q的延时，对查找表的速度做到一定的提高。  (2) When designing the circuit, it is considered that the driving capability of the CMOS transmission gates in multi-level cascading will have great problems, which will affect the data transmission speed. Therefore, it is necessary to insert an inverter on the critical path to improve the driving capability, but the inverter will change the polarity of the signal, so it must be inserted in pairs. In order to reduce the delay caused by the multi-stage inverter, the output of the storage point of the SRAM in the present invention is output from the inverting terminal, that is, arrive

output. On the contrary, if it is output from the non-inverting terminal of the SRAM storage point (P0 to P15), then a 4-stage inverter is required on the data transmission path. Through the design of outputting from the inverting end of the SRAM, the first-level inverter of the first-level data transmission path can be reduced, the delay of data from the storage unit to Q can be improved, and the speed of the look-up table can be improved to a certain extent.

(3) In terms of circuit design, while considering that the inverter can solve the problem of weak drive capability of the CMOS transmission tube, there is also an extended application, compare Figure 4 and Figure 5. When a set signal appears in the look-up table circuit, if the set signal is added to the Q terminal by a single-stage AND/OR gate, this will increase a stage of critical path delay. The present invention considers that if the enable signal is to be incorporated into a certain inverter, then the first inverter will be selected to be incorporated, because the primary buffer at the Q end may have a large load in consideration of the follow-up circuit, Then the size will be designed relatively large, so incorporating the last level of buffer will greatly increase the area. However, the load of the first-stage inverter is very small, and the size is also very small, so it can be made into an AND gate or an OR gate to incorporate the control signal, which can not only reduce the first-stage gate-level delay, but also achieve an area of only small increase. Only when the setting signal is valid, the 4 input terminal should be a certain fixed value to ensure that the setting signal is transmitted to the Q terminal. the

(4) In the design of the CMOS transmission tube, the present invention adopts a low-threshold tube, so that the data transmission delay can be reduced to a certain extent, but the impact on the leakage is very small, and the power consumption will not be increased.

Power and Area Optimization Notes for Designs

In the look-up table circuit of this design, the considerations for the optimization of power consumption and area include the following aspects:

(1) In terms of circuit structure, compared with Fig. 2, the present invention selects CMOS transmission tube circuit instead of NMOS transmission tube, avoiding the problem of signal delay asymmetry caused by the threshold value loss of NMOS transmission tube and power leakage caused by problem of increased consumption.

(2) In terms of size design, generally speaking, the PMOS size of the CMOS transmission tube will be 2 to 3 times that of the NMOS tube, so that the rise and fall times of the circuit remain symmetrical, but this will greatly increase the layout area of the lookup table . Since the first-level buffer I16 is added to the Q terminal, as shown in Figure 3, we can make the size of the PMOS and NMOS the same without ensuring the symmetry of the rise and fall times of the circuit. This greatly reduces the area of the lookup table.

technical effect

      The invention designs a high-performance look-up table circuit by improving the structure of the look-up table circuit, adopting a CMOS transmission tube composed of low-threshold tubes and optimizing the size of the MOS tube. In terms of speed, under the 65nm SMIC process, the delay of the look-up table circuit can reach only 0.22ns; under the operating frequency of 250MHZ, the dynamic leakage current can be only 82.5uA. In terms of area, the optimization of transistor size reduces the area occupied by PMOS transistors by 30% to 50%.

Description of drawings

Figure 1 Three-input lookup table structure.

Figure 2 The look-up table structure based on CMOS transmission tube.

Fig. 3 Lookup table structure of the present invention.

Figure 4 The look-up table structure of the set signal embedded in the inverter.

Figure 5 The set signal is added to the look-up table structure of a single logic gate.

Figure 6 SRAM memory cell structure.

Detailed ways

Taking the 4-input lookup table as an example, as shown in Figure 3, the switch of the CMOS transmission gate is controlled by pressing the logic value of the four-bit address A1 to A4, so that a conduction path appears from the SRAM terminal to the Q terminal, so that the output of the Q terminal needs to be realized. function value.

In principle, 16 SRAM programming points constitute the truth table of any 4-input combinatorial logic. Take the lookup table to implement a 4-input XOR logic as an example. The storage information of 4 input information and 16 programming points is shown in Table 1. When valid A1 to A4 are input, Q will output the value of the corresponding SRAM storage point.

The function realization process of the lookup table in FPGA is as follows:

First, in the process of FPGA downloading the bit stream, the 16 storage points of the look-up table used in the design will be written through word lines and bit lines. The structure of the SRAM storage unit is shown in Figure 6.

到

。 After the download is complete, as shown in Figure 3, the 16 SRAM units store the value of the truth table of the function to be realized bit by bit at this time, the positive phase output terminals of the SRAM unit are P0 to P15, and the inverting output terminals of the SRAM unit are

arrive

.

的值和

的值可以传过第一级CMOS传输管。由于A3A4=11，所以R6=R7=R8=0,R5=1，这使得由R5控制的CMOS传输管打开，将传过第一级的

的值传到最后两级反相器最终到达Q端输出，而由于R8=0，R8控制的CMOS传输管关闭，使得已经通过第一级传输管的

的值不能到达Q端输出。这样就实现了一个查找表逻辑。 At this time, adding different values to terminals A1~A4 will cause different CMOS transmission transistors to be turned on, so that terminal Q will output the value of the SRAM on the path where the CMOS transistors that are turned on are located. For example, in Figure 3, when A1A2A3A4=0011, R1=R2=R3=0, R4=1, which makes the CMOS transmission tube controlled by R4 open, thus

value and

The value of can pass through the first-stage CMOS transmission tube. Since A3A4=11, R6=R7=R8=0, R5=1, which makes the CMOS transmission tube controlled by R5 open, which will pass through the first stage

The value is transmitted to the last two stages of inverters and finally reaches the output of the Q terminal, and since R8=0, the CMOS transmission tube controlled by R8 is turned off, so that the first-stage transmission tube has passed

The value of can not reach the Q terminal output. This implements a lookup table logic.

In addition, if the circuit needs to add the logic of the set signal and other extended functions, Figure 5 illustrates the traditional way of adding the set function to the circuit. And the method of the present invention is, as shown in Figure 4, change the first inverter on the data path into a NAND gate. When the set signal is valid (0 is valid), the values of the four inputs A1 to A4 of the lookup table are all set to 1, then the channel where the set signal is located is selected, and the data output terminal Q is set to 1. This implements the lookup table logic that supports extended functions such as setting bits. Table 1 shows the 4-input XOR logic and programming point SRAM value.

Table 1

storage unit stored value Valid A4-A1 input SRAM0 (P0) 0 0000 SRAM1(P1) 1 0001 SRAM2 (P2) 1 0010 SRAM3 (P3) 0 0011 SRAM4(P4) 1 0100 SRAM5 (P5) 0 0101 SRAM6(P6) 0 0110 SRAM7(P7) 1 0111 SRAM8 (P8) 1 1000 SRAM9(P9) 0 1001 SRAM10 (P10) 0 1010 SRAM11 (P11) 1 1011 SRAM12 (P12) 0 1100 SRAM13 (P13) 1 1101 SRAM14 (P14) 1 1110 SRAM15 (P15) 0 1111

Claims (1)

1. the high-performance lut circuits based on FPGA, it is characterized in that adopting gate unit and CMOS transfer tube Mixed Design, for 4 input look-up tables, by one-level inverter, first-level buffer device, the low threshold value transfer tube of two-stage CMOS and a NAND gate, formed; Wherein, described first-level buffer device (I16) consists of two inverters, is arranged at before look-up table output Q; One-level inverter (I0 ~ I15), is arranged at the anti-phase output of the data storage cell SRAM of look-up table

~

after; The low threshold value transfer tube of two-stage CMOS (C0 ~ C15 and C16 ~ C19) be arranged at respectively after one-level inverter (I0 ~ I15) and buffer (I16) front; The output of one-level NAND gate is arranged at the control end of the low threshold value transfer tube of CMOS;

If: P0, P1～P15 represent the storing value of 16 SRAM programmed point, but the value of programmed point is all the end of oppisite phase output from SRAM,

~

; A1, A2, A3, A4 represent 4 function inputs of look-up table, and A1B, A2B, A3B, A4B represent 4 function input A1, A2, A3, the A4 negate signal afterwards of look-up table successively, and Q is look-up table output; The decoding of 4 input A1 ~ A4 is adopted to the mode of two decodings, it is first, second function input (A1, A2) of look-up table, and the combination of the signal (A1B and A2B) after negate realizes the control to the low threshold value transfer tube of first order CMOS circuit (C0 ~ C15) through one with door, the the 3rd, the 4th function input (A3, A4) of look-up table, and the combination of the signal (A3B and A4B) after negate realizes the control to the low threshold value transfer tube of second level CMOS circuit (C16 ~ C19) through one with door; Wherein, the low threshold value transfer tube of CMOS (C0 ~ C19) is to be formed in parallel by low threshold value NMOS pipe and PMOS, and NMOS manages and PMOS pipe is measure-alike; The value of SRAM storage is through end of oppisite phase output

~

, through one-level inverter (I0 ~ I15) and first-level buffer device (I16), 2 grades of low threshold value transfer tubes of CMOS (C0 ~ C15, C16 ~ C19), finally arrive look-up table output Q.

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