CN112733474A - Netlist-level circuit area optimization method based on AND gate inverter diagram and storage medium - Google Patents
Netlist-level circuit area optimization method based on AND gate inverter diagram and storage medium Download PDFInfo
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Abstract
The invention discloses a netlist-level circuit area optimization method and a storage medium based on an AND gate inverter diagram, wherein the optimization method comprises the following steps: step 1, obtaining a first netlist level circuit file; step 2, obtaining a plurality of first nodes and the connection relation between the first nodes according to the first netlist level circuit file and a preset sequence; step 3, correspondingly creating the first node as a second node of the AND gate/inverter graph based on a preset sequence, and searching the isomorphic structure of the local substructure in the hash table by using a hash searching method when the local substructure exists in the second node so as to obtain a creating result of the second node; and 4, processing the next first node according to the method in the step 3 based on the preset sequence until all the first nodes are processed, and obtaining a final AND gate/inverter graph. The optimization method can remove redundant circuit structures, thereby achieving the purposes of reducing the redundancy of the circuit structures and reducing the area of the circuit structures, and finally reducing the memory.
Description
Technical Field
The invention belongs to the technical field of circuit design, and particularly relates to a netlist-level circuit area optimization method based on an AND gate inverter diagram and a storage medium.
Background
With the rapid increase of the scale of the integrated circuit, due to some software and hardware factors, when the scale of the integrated circuit is large, the number of components in the generated circuit is often increased during the design and the subsequent synthesis, simulation and verification processes, which may further increase the scale of the circuit and cause the waste of time and money.
Under the promotion of such market conditions, when designing an integrated circuit, it is necessary to consider how to reduce the design iteration time of the integrated circuit, improve the design efficiency to shorten the design flow, and follow-up verification and other processes. In the design process, a large number of operations need to be performed on the netlist-level circuit, so that optimization of the netlist-level circuit is particularly important, and under the condition of reducing excessive redundant circuits, the cost of operating the netlist-level circuit, such as subsequent circuit segmentation or verification, can be greatly reduced.
For an initial netlist-level circuit model, continuous processing is often required to be performed for performing the next operation, such as performing behaviors like segmentation, and further conversion is required on the basis, and for these purposes, although in reality, optimization methods such as corresponding areas exist, these optimization methods are optimized for specific purposes, and have no universality.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a netlist-level circuit area optimization method based on an AND gate inverter diagram and a storage medium. The technical problem to be solved by the invention is realized by the following technical scheme:
a netlist-level circuit area optimization method based on an AND gate inverter diagram and a storage medium comprise the following steps:
and 4, processing the next first node according to the method in the step 3 based on the preset sequence until all the first nodes are processed, and obtaining a final AND gate/inverter graph.
In an embodiment of the present invention, creating the first node corresponding to the second node of the and gate/inverter graph based on the preset order includes:
based on the preset sequence, when the first node is the input node, the created second node is the initial node, when the first node is the intermediate node, the created second node is the AND node, when the first node is the output node, the created second node is the terminal node, and when two connected first nodes have an inverted input therebetween, the inverter node is created between the two first nodes having an inverted input therebetween.
In an embodiment of the present invention, searching for the isomorphic structure of the local substructure in the hash table by using a hash search method to obtain a creation result of the second node, includes:
obtaining an address index of an output logic value according to the local substructure;
and searching whether the address index has the output logic value or not in a hash table by using a hash searching method, if the output logic value does not exist, indicating that the second node does not have an isomorphic structure, creating the second node, and if the output logic value exists, indicating that the second node has the isomorphic structure, not creating the second node.
In an embodiment of the invention, obtaining the address index of the output logic value according to the local substructure includes:
obtaining an output logic value according to the local substructure;
and obtaining the address index of the output logic value according to the hash function.
In an embodiment of the present invention, if the output logic value does not exist, a corresponding relationship between the output logic value of the local substructure and the address index is created in the hash table.
In one embodiment of the invention, the output logic value comprises a first output logic value and a second output logic value, wherein the second output logic value is the first output logic value after the swapping.
In one embodiment of the invention, the first output logic value and the second output logic value comprise an inverter attribute and an input relationship of the second node.
In an embodiment of the present invention, the local substructure is a structure formed by a second node to be currently created and a second node located before and connected to the second node.
In an embodiment of the present invention, after the step 4, the method further includes:
and restoring the final AND gate/inverter diagram to a second netlist level circuit file.
The invention also provides a computer-readable storage medium, in which a computer program is stored, which, when being executed by a processor, carries out the steps of the above-mentioned method.
The invention has the beneficial effects that:
the invention provides a new universal netlist-level circuit area optimization method, which converts a netlist-level design circuit into an and/inverter diagram form for processing, and simultaneously searches whether the circuit has a isomorphic structure or not in a hash searching mode to remove a redundant circuit structure, thereby achieving the purposes of reducing the redundancy of the circuit structure, reducing the area of the circuit structure and finally reducing the memory.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a flow chart of a netlist-level circuit area optimization method based on an AND/inverter diagram according to an embodiment of the present invention;
FIG. 2 is a flow chart of another netlist-level circuit area optimization method based on AND/inverter diagram according to the embodiment of the invention;
FIG. 3 is a diagram of a general block diagram of an inverter/inverter diagram and a block diagram represented by nodes and arcs provided by an embodiment of the present invention;
FIG. 4 is a schematic diagram of an unoptimized and/or inverter diagram according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of an optimized AND/inverter diagram provided by an embodiment of the present invention;
fig. 6 is a schematic block diagram of a computer device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
At present, the related technology is optimized and improved aiming at a netlist-level circuit, most of the related technologies are that the netlist-level circuit is preprocessed and then corresponds to a next specific operation process, a corresponding algorithm is adopted to optimize the cost of the operation process, for example, when the netlist-level circuit is divided, the netlist-level circuit is often converted into a hypergraph form or other forms, and then methods in the aspects of time, accuracy and the like of the division algorithm are adopted to optimize, although the methods can achieve the optimization result, the methods are all that the operation of performing a certain purpose on the circuit is optimized, and the optimization cannot be performed on the level of the circuit; secondly, for some designs with small circuit scale, people may perform mathematical calculation on the designs through boolean algebra such as carnot diagrams or other simplified modes to achieve the purposes of reducing circuit structure redundancy and reducing circuit area.
Referring to fig. 1 and fig. 2, fig. 1 is a schematic flowchart of a netlist-level circuit area optimization method based on an and-gate inverter diagram according to an embodiment of the present invention, and fig. 2 is a schematic flowchart of another netlist-level circuit area optimization method based on an and-gate inverter diagram according to an embodiment of the present invention. For the above reasons, the present embodiment provides a netlist-level circuit area optimization method based on an and-gate inverter diagram, the netlist-level circuit area optimization method including steps 1 to 4, where:
Specifically, the first netlist-level circuit file is a netlist-level circuit file which needs to be optimized.
And 2, obtaining a plurality of first nodes and the connection relation between the first nodes according to the first netlist level circuit file and a preset sequence, wherein the first nodes are input nodes, intermediate nodes or output nodes.
Specifically, an input first netlist level circuit file is stored in a corresponding first data structure, the element sequence in the first data structure is determined according to the connection relation from circuit input to circuit output in sequence, the first data structure comprises information of input, output, nodes, connection relation and the like of the circuit, and the preset sequence is the sequence from the input to the output of the circuit.
In this embodiment, each unit of the first netlist-level circuit file is stored in the first data structure as a first node, so that the connection relationship between a plurality of first nodes of the first netlist-level circuit file and each first node can be stored in the first data structure according to a preset sequence, and the first nodes can be input nodes, intermediate nodes or output nodes, where the input nodes are input units of the entire circuit, the input nodes have no input arcs, the intermediate nodes are units having both input arcs and output arcs, the output nodes are output units of the entire circuit, and the arcs are connection lines between the two nodes. In addition, each first node is labeled to distinguish the first nodes, for example, the first nodes are labeled as 1, 2, 3, 4, etc., and 1, 2, 3, and 4 represent 4 different first nodes, respectively.
And 3, correspondingly creating the first node as a second node of the and gate/inverter graph based on a preset sequence, and when the second node has a local substructure, searching the isomorphic structure of the local substructure in a hash table by using a hash searching method to obtain a creation result of the second node, wherein the second node is an initial node, an and node, an inverter node or a terminal node, for example, please refer to fig. 3, the graph on the left of the arrow in fig. 3 is a general structure of the and gate/inverter graph, and the graph on the left of the arrow in fig. 3 is a graph represented by nodes and arcs.
Specifically, a second node of the and gate/inverter graph is created according to a first node stored in a first data structure in a preset order, when the second node is created, whether a local substructure exists in the second node is further judged, if the local substructure exists, whether an isomorphic structure exists in the local substructure is searched in a hash table by using a hash search method, and whether the second node is created according to whether the isomorphic structure exists or not is determined, wherein the isomorphic structure is equal to the input relationship of the currently processed node and the inverter attribute of the connecting arc is the same.
For example, please refer to fig. 4, the local substructure of the node 1 is a structure formed by a node a, a node b, a node 1 and a connection relationship thereof.
Further, creating the first node correspondence as a second node of the and gate/inverter graph based on a preset order, comprising:
based on the preset sequence, when the first node is an input node, the created second node is an initial node, when the first node is an intermediate node, the created second node is an AND node, when the first node is an output node, the created second node is a terminal node, and when two connected first nodes have an inverted input therebetween, the inverter node is created between the two first nodes having the inverted input.
In this embodiment, the first nodes stored in the first data structure are called in a preset order, for example, as shown in fig. 4, the order of calling is sequentially node a, node b, node 1, node 2, node 3, node 4, node 5, and node 6, where fig. 2 shows that expressions c ═ XOR (a, b), and d ═ XNOR (a, b), the circuit structure shown is simplified into a form of node and arc (node is a circle, and arc is a connecting edge), inputs are a, b, c, d, and outputs are c, d, and the expression represented in fig. 4 means that if a and b have the same value, the value of c is 0, and if a and b have different values, the result of c is 1.
When the called first node is an input node, that is, the first node has no input relationship, the first node is used as an initial node in the and/inverter graph, that is, nodes a and b in fig. 4 are initial nodes, for example, an initial node of the and/inverter is created by using a create _ input function, which is used to create an input node, that is, an initial node, the initial node belongs to a node without an input arc and a main input, and the initial node has no local substructure because the initial node has no input arc; when the called first node is an intermediate node, that is, the first node is not an output node of the circuit and has a node connected to the first node, the first node is an and node in the and/inverter graph, such as nodes 1, 2, 3 and 4 in fig. 4, that is, an and node, the inputs of the four nodes are directly input from nodes a and b, and none of the four nodes is an ultimate output node of the circuit, for example, an and node of the and/inverter is created by using a creat _ and function for creating an and node belonging to an output node having an input arc and not being a circuit; when the called first node is an output node, that is, the first node is an output node of the circuit, then the first node is used as a terminal node in the and/inverter diagram, for example, nodes 5 and 6 in fig. 4 are terminal nodes, which are final output nodes of the circuit, and the terminal nodes can be represented by logic values "0" or "1"; in addition, since there is a node connected to the node and the terminal node before the node, there may be an inverted input, when creating the node or the terminal node, it is also determined whether there is an inverted input between the node and the previous node connected to the node, if there is an inverted input, an inverter node needs to be created between the two nodes, for example, when creating the node 2 in fig. 4, because there is an inverted input between the node a and the node 2, it is necessary to create an inverter node between the node a and the node 2, which is a black circle of the node a and the node 2, and when there is an inverted input, the fresh _ inverter function is called to create the inverter node, and fresh _ inverter is used to create the inverter node.
Further, searching the isomorphic structure of the local substructure in the hash table by using a hash search method to obtain a creation result of the second node, including:
obtaining an address index of an output logic value according to the local substructure;
and searching whether the address index has an output logic value or not in a hash table by using a hash searching method, if the output logic value does not exist, indicating that the second node does not have an isomorphic structure, creating the second node, and if the output logic value exists, indicating that the second node has the isomorphic structure, not creating the second node.
In this embodiment, the output logic value includes a first output logic value and a second output logic value, where the second output logic value is a first output logic value after the exchange position is performed, and the first output logic value and the second output logic value include an input relationship and an inverter attribute of a second node, that is, for a node to be currently created, first, a local substructure of the node is determined, then, the local substructure is analyzed, a logic calculation is performed to obtain an equality relationship of the node to be currently created and an inverter attribute of a connection arc, an input logic is obtained, and then, an output logic value of the local substructure is obtained by whether an inverter exists on the connection arc or not, for example, the node to be currently created is node 1, an input of the node 1 is input by node a and node b, and for node 1, the corresponding local substructure thereof is node a, node b, and node b, In the structure formed by the node 1 and the connection relation thereof, because there is no inverter node between the node 1 and the node a, and between the node 1 and the node b, the output logic value corresponding to the local substructure of the node 1 may be expressed as 1 ═ a · b, which indicates that the value of the output node 1 is the result of the node a and the node b, and in order to ensure the accuracy of the result, it is necessary to exchange the positions of the node a and the node b in the hash lookup, that is, to simultaneously consider whether 1 ═ b · a exists, so that the exchange position does not affect the result, therefore, when 1 ═ a · b is the first output logic value, 1 ═ b · a is the second output logic value, and for example, the node to be created is the node 5, the input of the node 5 is input by the node 1 and the node 2, and the corresponding local substructure of the node 5 is the structure formed by the node 1, the node 2, the node 5 and the connection relation thereof, because there are inverter nodes between node 5 and node 1 and between node 5 and node 2, the output logic value corresponding to the local substructure of node 5 may be represented as 5 ═ 1'· 2', which indicates that the value of output node 5 is the result of node 1 and node 2 and there are inverting inputs between node 5 and node 1 and between node 5 and node 2, and in the hash lookup, in order to ensure the accuracy of the result, it is necessary to exchange the positions of node 1 and node 2, i.e. to consider whether 5 ═ 2'· 1' exists at the same time.
Then, the obtained output logic value is stored in the second data structure, then the address index of the output logic value can be obtained, then, whether the output logic value exists in the address index can be searched in a hash table by using a hash search method, that is, after the address index of the output logic value is determined, if the storage location corresponding to the address index already stores content, that is, the output logic value is already stored, it is indicated that an isomorphic structure corresponding to the local substructure already exists in the second data structure, at this time, the second node does not need to be created, and the isomorphic structures stored in the second data structure, such as the node 5 and the node 6 in fig. 4, can be called directly, because the node 5 is created first, because the output logic value of the local substructure corresponding to the node 5 already exists in the second data structure, when the node 6 is created, the isomorphic structure already exists, so the structure of the node 5 can be called without creating the node 6, for example, fig. 5 is the result of the optimization through fig. 4. If the storage position corresponding to the address index does not store the content, the local substructure is proved to have no isomorphic structure, and the node needs to be created.
In this embodiment, the hash table represents a corresponding relationship between an output logic value and an address index, that is, the hash table records a corresponding relationship between indexes of storage locations, in the second data structure, where all the storage locations are stored with the output logic values corresponding to the currently processed first netlist-level circuit file, and the output logic values, so that when the index of the output logic value corresponding to the currently to-be-processed local substructure cannot be found in the hash table, it is described that the storage location corresponding to the index does not yet store the output logic value, and at this time, a corresponding relationship between the output logic value of the currently processed local substructure and the address index needs to be created in the hash table.
Wherein obtaining an address index of the output logic value according to the local substructure comprises: obtaining an output logic value according to the local substructure; and obtaining the address index of the output logic value according to the hash function.
That is, first, an output logic value corresponding to a local substructure to be processed is obtained according to the local substructure, and the output logic value is stored in a corresponding second data structure, and meanwhile, a result of storing an address of the output logic value in the second data structure is calculated by using a hash function, and the result calculated by using the hash function is used as an address index of the output logic value, so as to perform hash lookup in a hash table.
And 4, processing the next first node according to the method in the step 3 based on the preset sequence until all the first nodes are processed, and obtaining a final AND gate/inverter graph.
That is, according to the preset sequence, the first nodes in the first data structure are processed one by one according to the processing manner in step 3 until all the first nodes are processed, and then an optimized and gate/inverter graph, that is, a final and gate/inverter graph, is obtained, for example, fig. 5 is the final and gate/inverter graph after being optimized in fig. 4, as can be seen from fig. 4 and fig. 5, compared with the previous and gate/inverter graph, the content in the virtual coil in fig. 4 is removed in the creation process, meanwhile, the node 6 is also removed, the output arc of d is directly connected to the node 5, and the output node of d directly calls the local sub-structure of the node 5, so that the redundancy of the corresponding circuit structure is reduced, the circuit area is reduced, and the purpose of reducing the use of the memory is achieved.
And 5, restoring the final AND gate/inverter diagram to a second netlist level circuit file.
That is, according to the optimized and gate/inverter diagram, the optimized and gate/inverter diagram is restored to a netlist-level circuit file, and the netlist-level circuit file is the second netlist-level circuit file.
The invention has the advantages that the design circuit of the netlist level is converted into the form of the AND/inverter diagram for processing, the netlist circuit is optimized through the structure of the AND/inverter diagram, whether the isomorphic structure exists in the circuit is searched in a hash searching mode, so that the structure and the area of the circuit are optimized, the circuit is written back to the netlist level circuit again, the redundancy of the circuit can be greatly reduced, the cost of a memory and the like required by subsequent operation is reduced, meanwhile, the use of the memory can be greatly reduced when the optimized netlist level circuit is divided, and the dividing efficiency is improved.
Example two
The present invention also provides a computer-readable storage medium, in which a computer program is stored, and the computer program implements the steps of the first embodiment when being executed by a processor.
Generally, the computer readable storage medium can be disposed in a computer device, see fig. 6, which can include units or modules of a processor, a communication interface, a computer readable storage medium, and a communication bus, wherein the processor, the communication interface, and the memory are communicated with each other through the communication bus,
a computer-readable storage medium for storing a computer program;
a processor, configured to implement the following steps when executing a program stored on a computer-readable storage medium:
and 4, processing the next first node according to the method in the step 3 based on the preset sequence until all the first nodes are processed, and obtaining a final AND gate/inverter graph.
The communication bus mentioned in the above computer device may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The communication bus may be divided into an address bus, a data bus, a control bus, etc.
The communication interface is used for communication between the electronic equipment and other equipment.
The Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components.
The computer device may be: desktop computers, laptop computers, intelligent mobile terminals, servers, and the like. Without limitation, any electronic device that can implement the present invention is within the scope of the present invention.
For the computer device/storage medium embodiment, since it is substantially similar to the method embodiment, the description is simple, and the relevant points can be referred to the partial description of the method embodiment one.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
While the present application has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, apparatus, or computer program product. Accordingly, this application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects that may all generally be referred to herein as a "module" or "system. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein. A computer program stored/distributed on a suitable medium supplied together with or as part of other hardware, may also take other distributed forms, such as via the Internet or other wired or wireless telecommunication systems.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In the description of the present invention, it is to be understood that the terms "first", "second" and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. A netlist-level circuit area optimization method based on an AND gate inverter diagram is characterized by comprising the following steps:
step 1, obtaining a first netlist level circuit file;
step 2, obtaining a plurality of first nodes and the connection relation between the first nodes according to the first netlist level circuit file and a preset sequence, wherein the first nodes are input nodes, intermediate nodes or output nodes;
step 3, correspondingly creating the first node as a second node of the AND gate/inverter graph based on the preset sequence, and when the second node has a local substructure, searching the isomorphic structure of the local substructure in a hash table by using a hash searching method to obtain a creation result of the second node, wherein the second node is an initial node, an AND node, an inverter node or a terminal node;
and 4, processing the next first node according to the method in the step 3 based on the preset sequence until all the first nodes are processed, and obtaining a final AND gate/inverter graph.
2. The netlist-level circuit area optimization method of claim 1, wherein creating the first node correspondence as a second node of an and gate/inverter graph based on the preset order comprises:
based on the preset sequence, when the first node is the input node, the created second node is the initial node, when the first node is the intermediate node, the created second node is the AND node, when the first node is the output node, the created second node is the terminal node, and when two connected first nodes have an inverted input therebetween, the inverter node is created between the two first nodes having an inverted input therebetween.
3. The netlist-level circuit area optimization method of claim 1, wherein the searching the isomorphic structure of the local substructure in a hash table using a hash search method to obtain the creation result of the second node comprises:
obtaining an address index of an output logic value according to the local substructure;
and searching whether the address index has the output logic value or not in a hash table by using a hash searching method, if the output logic value does not exist, indicating that the second node does not have an isomorphic structure, creating the second node, and if the output logic value exists, indicating that the second node has the isomorphic structure, not creating the second node.
4. The netlist-level circuit area optimization method of claim 3, wherein obtaining the address index of the output logic value from the local substructure comprises:
obtaining an output logic value according to the local substructure;
and obtaining the address index of the output logic value according to the hash function.
5. The netlist-level circuit area optimization method of claim 3, wherein if the output logic value does not exist, a correspondence between the output logic value of the local substructure and the address index is created in the hash table.
6. The netlist stage circuit area optimization method of any one of claims 3 to 5, the output logic values comprising a first output logic value and a second output logic value, wherein the second output logic value is the first output logic value after the swap bit.
7. The netlist stage circuit area optimization method of any of claims 6, the first and second output logic values comprising an inverter property and an input relationship of the second node.
8. The netlist-level circuit area optimization method of claim 1, wherein the local substructure is a structure of a second node to be created currently and a second node preceding and connected to the second node.
9. The netlist-level circuit area optimization method of claim 1, further comprising, after step 4:
and restoring the final AND gate/inverter diagram to a second netlist level circuit file.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 9.
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