CN112733474B - Netlist-level circuit area optimization method based on AND gate inverter diagram and storage medium - Google Patents
Netlist-level circuit area optimization method based on AND gate inverter diagram and storage medium Download PDFInfo
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Abstract
The invention discloses a netlist-level circuit area optimization method and a storage medium based on an AND gate inverter graph, wherein the optimization method comprises the following steps: step 1, obtaining a first netlist level circuit file; step 2, obtaining connection relations between a plurality of first nodes and each first node according to a preset sequence according to the first netlist level circuit file; step 3, correspondingly creating the first node as a second node of the AND gate/inverter diagram based on a preset sequence, and when the second node has a local substructure, searching the isomorphic structure of the local substructure in a hash table by using a hash searching method to obtain the creation result of the second node; and 4, processing the next first node according to the method of the step 3 based on a preset sequence until all the first nodes are processed, and obtaining a final AND gate/inverter diagram. The optimization method can remove redundant circuit structures, thereby achieving the purpose of reducing the redundancy of the circuit structures and reducing the area of the circuit structures, and finally reducing the memory.
Description
Technical Field
The invention belongs to the technical field of circuit design, and particularly relates to a netlist-level circuit area optimization method based on an AND gate inverter graph and a storage medium.
Background
With the rapid growth of the scale of integrated circuits, due to some software and hardware factors, when the scale of the integrated circuits is very large, the number of components in the generated circuits is often increased during the design and subsequent synthesis, simulation and verification processes, so that the scale of the circuits is further increased, and time and money are wasted.
Under the push of this market situation, these factors need to be considered in designing an integrated circuit, for how to reduce the design iteration time of the integrated circuit, improve the design efficiency to shorten the design flow, and the subsequent verification process. In the design process, since a large number of operations are required to be performed on the netlist-level circuit, optimization of the netlist-level circuit is particularly important, and in the case of reducing excessive redundant circuits, the cost in the operation of the netlist-level circuit, such as subsequent circuit segmentation or verification, can be greatly reduced.
For the initial netlist-level circuit model, the initial netlist-level circuit model often needs to be processed continuously for performing next operations, such as splitting and the like, and then needs to be converted on the basis of the next operations, so that the initial netlist-level circuit model is optimized according to specific purposes although optimization methods such as corresponding areas and the like exist in reality, and the initial netlist-level circuit model is not universal.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a netlist-level circuit area optimization method based on an AND gate inverter diagram and a storage medium. The technical problems to be solved by the invention are realized by the following technical scheme:
a netlist-level circuit area optimization method and a storage medium based on an AND gate inverter graph comprise the following steps:
step 1, obtaining a first netlist level circuit file;
step 2, obtaining connection relations between a plurality of first nodes and each first node according to the first netlist level circuit file and a preset sequence, wherein the first nodes are input nodes, intermediate nodes or output nodes;
step 3, correspondingly creating the first node as a second node of an AND gate/inverter graph based on the preset sequence, and when a local substructure exists in the second node, searching an isomorphic structure of the local substructure in a hash table by using a hash searching method to obtain a creation result of the second node, wherein the second node is an initial node, a AND node, an inverter node or a terminal node;
and 4, processing the next first node according to the method of the step 3 based on the preset sequence until all the first nodes are processed, and obtaining a final AND gate/inverter diagram.
In one embodiment of the present invention, the creating the first node correspondence as the second node of the and gate/inverter graph based on the preset order includes:
based on the preset sequence, when the first node is the input node, the second node is the initial node, when the first node is the intermediate node, the second node is the AND node, when the first node is the output node, the second node is the terminal node, and when there is an inverting input between the two connected first nodes, the inverter node is created between the two first nodes having inverting inputs.
In one embodiment of the present invention, searching the isomorphic structure of the local sub-structure in the hash table by using a hash searching method to obtain the creation result of the second node includes:
obtaining an address index of an output logic value according to the local substructure;
and searching whether the output logic value exists in the address index in a hash table by utilizing a hash searching method, if the output logic value does not exist, the second node is created if the second node does not exist in an isomorphic structure, and if the output logic value exists, the second node is not created if the second node exists in an isomorphic structure.
In one embodiment of the present invention, obtaining the address index of the output logical value according to the local substructure includes:
obtaining an output logic value according to the local substructure;
and obtaining the address index of the output logic value according to the hash function.
In one embodiment of the present invention, if the output logical value is not present, a correspondence of the output logical value of the local substructure and the address index is created in the hash table.
In one embodiment of the invention, the output logic values include a first output logic value and a second output logic value, wherein the second output logic value is the first output logic value after the swap position.
In one embodiment of the invention, the first output logic value and the second output logic value comprise an input relationship and inverter properties of the second node.
In one embodiment of the present invention, the local substructure is a structure formed by a second node to be currently created and a second node that is located before and connected to the second node.
In one embodiment of the present invention, after the step 4, the method further includes:
and restoring the final AND gate/inverter diagram to a second netlist-level circuit file.
The present invention also provides a computer readable storage medium having a computer program stored therein, which when executed by a processor, implements the steps of the above method.
The invention has the beneficial effects that:
the invention provides a new universal netlist-level circuit area optimization method, which converts a netlist-level design circuit into a form of a graph of a phase inverter for processing, and searches whether a circuit has an isomorphic structure or not in a hash searching mode so as to remove redundant circuit structures, thereby achieving the purposes of reducing the redundancy of the circuit structures and reducing the area of the circuit structures and finally reducing the memory.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a schematic flow chart of a netlist-level circuit area optimization method based on an AND/inverter diagram according to an embodiment of the present invention;
FIG. 2 is a flow chart of another method for optimizing the area of a netlist-level circuit based on an AND/inverter diagram according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a general block diagram of an AND/NODE diagram and a block diagram represented by nodes and arcs provided by an embodiment of the present invention;
FIG. 4 is a schematic diagram of an unoptimized AND/inverter diagram provided by an embodiment of the present invention;
FIG. 5 is a schematic diagram of an optimized AND/inverter diagram provided by an embodiment of the present invention;
fig. 6 is a schematic diagram of a computer device module according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
Example 1
At present, with respect to the related technology of optimizing and improving a netlist-level circuit, most of the related technology is that after the netlist-level circuit is preprocessed, a corresponding algorithm is adopted to optimize the cost of the operation process corresponding to the next step, for example, when the netlist-level circuit is segmented, the netlist-level circuit is often optimized in terms of time, accuracy and the like of an optimized segmentation algorithm after being converted into a hypergraph form or other forms, and although the optimized results can be achieved, the operation for a certain purpose is performed on the circuit, but the optimization cannot be performed on the level of the circuit; secondly, for some designs with small circuit scale, people may perform mathematical computation on the design by using boolean algebra such as carnot diagram or other simplified modes, so as to achieve the purposes of reducing redundancy of circuit structures and reducing circuit area.
Referring to fig. 1 and 2, fig. 1 is a schematic flow chart of a netlist-level circuit area optimization method based on an and gate inverter diagram according to an embodiment of the present invention, and fig. 2 is a schematic flow chart of another netlist-level circuit area optimization method based on an and gate inverter diagram according to an embodiment of the present invention. For the above reasons, the present embodiment provides a netlist-level circuit area optimization method based on an and gate inverter diagram, which includes steps 1 to 4, wherein:
step 1, obtaining a first netlist level circuit file.
Specifically, the first netlist-level circuit file is a netlist-level circuit file that needs to be optimized.
And 2, obtaining connection relations between a plurality of first nodes and each first node according to the first netlist level circuit file and a preset sequence, wherein the first nodes are input nodes, intermediate nodes or output nodes.
Specifically, for an input first netlist-level circuit file, the input first netlist-level circuit file is stored in a corresponding first data structure, the element sequence in the first data structure is sequentially determined according to the connection relation from the input to the output of the circuit, the first data structure comprises information such as the input, the output, the nodes and the connection relation of the circuit, and the preset sequence is the sequence from the input to the output of the circuit.
In this embodiment, each unit of the first netlist-level circuit file is stored as a first node in the first data structure, so that the connection relationships between a plurality of first nodes of the first netlist-level circuit file and each first node can be stored in the first data structure according to a preset sequence, the first nodes can be input nodes, intermediate nodes or output nodes, wherein the input nodes are input units of the whole circuit, the input nodes have no input arcs, the intermediate nodes are units with input arcs and output arcs, the output nodes are output units of the whole circuit, and the arcs are connecting lines between the two nodes. In addition, each first node is labeled to distinguish the first nodes, e.g., the first nodes are labeled 1, 2, 3, 4, etc., and then 1, 2, 3, and 4 represent 4 different first nodes, respectively.
And 3, correspondingly creating the first node as a second node of the AND gate/inverter diagram based on a preset sequence, and when the second node has a local substructure, searching the isomorphic structure of the local substructure in the hash table by using a hash searching method to obtain a creation result of the second node, wherein the second node is an initial node, a AND node, an inverter node or a terminal node, for example, please refer to fig. 3, a diagram on the left of an arrow in fig. 3 is a general structure of the AND gate/inverter diagram, and a diagram on the left of the arrow in fig. 3 is a diagram represented by the nodes and arcs.
Specifically, a second node of an AND gate/inverter graph is created according to a first node stored in a first data structure according to a preset sequence, when the second node is created, whether a local sub-structure exists in the second node is further judged, if the local sub-structure exists, whether the local sub-structure exists in a isomorphic structure is searched in a hash table by utilizing a hash searching method, so that whether the second node is created is determined according to whether the isomorphic structure exists, wherein the isomorphic structure is equal to the input relation of the currently processed node, and the inverter attribute of a connecting arc is the same.
The local substructure is a structure formed by the second node to be created and the second node that is located before and connected to the second node, for example, referring to fig. 4, the local substructure of the node 1 is a structure formed by the node a, the node b, the node 1 and the connection relationship thereof.
Further, creating the first node correspondence as a second node of the and gate/inverter graph based on the preset order, comprising:
based on a preset sequence, when a first node is an input node, a second node is created as an initial node, when the first node is an intermediate node, the second node is a AND node, when the first node is an output node, the second node is a terminal node, and when two connected first nodes have an inverted input, the inverter node is created between the two first nodes having the inverted input.
In this embodiment, the first node stored in the first data structure is called according to a preset sequence, for example, as shown in fig. 4, the called sequence is sequentially node a, node b, node 1, node 2, node 3, node 4, node 5 and node 6, where fig. 2 shows that the expressions c=xor (a, b) and d=xnor (a, b) indicate that the circuit structure is simplified into the form of nodes and arcs (the nodes are circles, the arcs are connecting edges), the input is a, b, c, d, the output is c, d, and the meaning of the expression represented by fig. 4 is that if a and b are the same, the value of c is 0, and if a and b are different, the result of c is 1.
When the first node is an input node, i.e. the first node has no input relation, the first node is used as an initial node in the and/or inverter graph, for example, node a and node b in fig. 4 are initial nodes, for example, an initial node of the and/or inverter is created by using a create_input function, wherein the create_input function is used for creating an input node, i.e. an initial node, the initial node belongs to a node without an input arc and a main input, and the initial node has no local substructure because the initial node has no input arc; when the first node is an intermediate node, i.e. the first node is not an output node of the circuit and is connected with the first node, then the first node is an and node in the and/inverter graph, such as node 1, node 2, node 3, and node 4 in fig. 4 are and nodes, the inputs of the four nodes are all directly input by node a and node b, and the four nodes are not final output nodes of the circuit, for example, an and node of the and/inverter is created by using a create and function, the create and function is used for creating an and node, and the and node belongs to an output node with an input arc and not of the circuit; when the first node is the output node, i.e. the first node is the output node of the circuit, then the first node is used as the terminal node in the and/or inverter graph, such as node 5 and node 6 in fig. 4 are terminal nodes, the two nodes are final output nodes of the circuit, and the terminal node can be represented by logic value "0" or "1"; in addition, since there may be an inverting input before it is connected to both the node and the terminal node, it is also determined whether there is an inverting input between the node and the previous node connected thereto when creating the node or the terminal node, and if there is an inverting input, an inverter node needs to be created between the two nodes, for example, when creating node 2 in fig. 4, an inverter node needs to be created between node a and node 2 because there is an inverting input between node a and node 2, that is, a black circle of node a and node 2, and when there is an inverting input, then the create inverter node is called by the create_inverter function, and the create_inverter is used to create the inverter node.
Further, searching the isomorphic structure of the local sub-structure in the hash table by using a hash searching method to obtain the creation result of the second node, including:
obtaining an address index of an output logic value according to the local substructure;
and searching whether the output logic value exists in the address index in the hash table by utilizing a hash searching method, if the output logic value does not exist, the second node is created if the second node does not exist in the isomorphic structure, and if the output logic value exists, the second node is created if the second node does exist in the isomorphic structure, the second node is not created.
In this embodiment, the output logic value includes a first output logic value and a second output logic value, where the second output logic value is the first output logic value after the switch position, and the first output logic value and the second output logic value include the input relation and the inverter attribute of the second node, i.e., for the node to be created currently, the local substructure of the node is first determined, then the local substructure is analyzed, logic calculation is performed to obtain the inverter attribute of the equal relation and the connection arc of the node to be created currently, and then the output logic value of the local substructure is obtained by inverting the inverter on the connection arc, for example, if the node to be created currently is node 1, the input of the node 1 is input by node a and node b, and for the node 1, the local substructure corresponding to the node 1 is the structure formed by node a, node b, node 1 and the connection relation thereof, because there is no inverter node between node 1 and node b, the output logic value corresponding to the local substructure of the node 1 can be represented by 1=a·b, and represents that when the node 1 is node 1 and node b is node 1, the node 1 is not found out of the local substructure is 1, for example, the node 1 is not found out of node 1, and for example, the node 1 is node 1, node b is not found out when the node 1 is the node 1, node 1 is found out of the node b, and node 1 is not found out of the node 1, and node 1 is found out of the node b, and node 1 is not found out when the node 1, and node 1 is found out is corresponding to be the node 1, and node b Because there are all inverter nodes between the node 5 and the node 1 and between the node 5 and the node 2, the output logic value corresponding to the local substructure of the node 5 may be expressed as 5=1 '. 2', which means that the value of the output node 5 is the result of the node 1 and the node 2 and that there is an inverting input between the node 5 and the node 1 and between the node 5 and the node 2, and in order to ensure the accuracy of the result in hash lookup, the positions of the node 1 and the node 2 need to be exchanged, that is, whether 5=2 '. 1' exists is considered at the same time.
Then, the obtained output logical value is stored in the second data structure, then the address index of the output logical value can be obtained, then the hash lookup method can be used to find whether the output logical value exists in the address index in the hash table, namely, after the address index of the output logical value is determined, if the storage position corresponding to the address index already stores the content, that is, the output logical value is already stored, it is indicated that the isomorphic structure corresponding to the local substructure already exists in the second data structure, at this time, the second node is not required to be created, the isomorphic structure stored in the second data structure is directly called, for example, the node 5 and the node 6 in fig. 4 are required to be directly called, because the node 5 is created first, because the output logical value of the local substructure corresponding to the node 5 is already stored in the second data structure, when the node 6 is created, the isomorphic structure is already existing, and therefore, the node 6 is not created, and the structure of the node 5 is called, for example, the result optimized through fig. 4 is just required. If the storage location corresponding to the address index has no stored content, the local sub-structure is not provided with a isomorphic structure, and the node needs to be created.
In this embodiment, the hash table characterizes the correspondence between the output logic value and the address index, that is, the hash table records the correspondence between the indexes of all the storage locations storing the output logic values corresponding to the current processed first netlist-level circuit file in the second data structure and the output logic values, so when the index of the output logic value corresponding to the current to-be-processed local substructure is not found in the hash table, it is indicated that the storage location corresponding to the index does not store the output logic value yet, and at this time, the correspondence between the output logic value of the current to-be-processed local substructure and the address index needs to be created in the hash table.
Wherein obtaining an address index of the output logical value according to the local substructure includes: obtaining an output logic value according to the local substructure; an address index of the output logical value is obtained from the hash function.
That is, firstly, an output logic value corresponding to the local sub-structure is obtained according to the local sub-structure to be processed, the output logic value is stored in a corresponding second data structure, meanwhile, the result of storing the address of the output logic value in the second data structure is calculated by utilizing a hash function, and the calculated result of the hash function is used as an address index of the output logic value so as to facilitate hash lookup in a hash table.
And 4, processing the next first node according to the method of the step 3 based on a preset sequence until all the first nodes are processed, and obtaining a final AND gate/inverter diagram.
That is, according to the preset sequence, the first nodes in the first data structure are processed one by one according to the processing manner of step 3 until all the first nodes are processed, so as to obtain an optimized and gate/inverter diagram, i.e. a final and gate/inverter diagram, for example, fig. 5 is the final and gate/inverter diagram after being optimized in fig. 4, as can be seen from fig. 4 and fig. 5, compared with the previous and gate/inverter diagram, the contents in the virtual coil in fig. 4 are removed in the process of creation, meanwhile, node 6 is also removed, the output arc of d is directly connected to node 5, and the output node of d directly invokes the local substructure of node 5, which reduces redundancy of the corresponding circuit structure, reduces the circuit area, and achieves the purpose of reducing the memory usage.
And 5, restoring the final AND gate/inverter diagram to a second netlist-level circuit file.
That is, the optimized and gate/inverter diagram is restored to the netlist-level circuit file according to the optimized and gate/inverter diagram, and the netlist-level circuit file is the second netlist-level circuit file.
The method has the advantages that the design circuit of the netlist level is converted into the form of the and/or inverter diagram for processing, the netlist circuit is optimized through the structure of the and/or inverter diagram, whether the circuit has an isomorphic structure is searched through a hash searching mode, so that the structure and the area of the circuit are optimized, the netlist level circuit is rewritten, redundancy of the circuit can be greatly reduced, cost such as memory required by subsequent operation is reduced, and meanwhile, the use of the memory is greatly reduced when the optimized netlist level circuit is segmented again, and the segmentation efficiency is improved.
Example two
The present invention also provides a computer-readable storage medium having a computer program stored therein, which when executed by a processor, implements the steps of the first embodiment described above.
In general, the computer readable storage medium may be disposed in a computer device, referring to fig. 6, which may include a processor, a communication interface, a computer readable storage medium, and a communication bus or other units or modules, where the processor, the communication interface, and the memory perform communication with each other via the communication bus,
a computer readable storage medium storing a computer program;
a processor for executing the program stored on the computer readable storage medium, implementing the steps of:
step 1, obtaining a first netlist level circuit file;
step 2, obtaining connection relations between a plurality of first nodes and each first node according to a preset sequence according to the first netlist level circuit file, wherein the first nodes are input nodes, intermediate nodes or output nodes;
step 3, correspondingly creating the first node as a second node of the AND gate/inverter graph based on a preset sequence, and when the second node has a local substructure, searching the isomorphic structure of the local substructure in a hash table by using a hash searching method to obtain a creation result of the second node, wherein the second node is an initial node, a AND node, an inverter node or a terminal node;
and 4, processing the next first node according to the method of the step 3 based on a preset sequence until all the first nodes are processed, and obtaining a final AND gate/inverter diagram.
The communication bus mentioned above for the computer device may be a peripheral component interconnect standard (Peripheral Component Interconnect, PCI) bus or an extended industry standard architecture (Extended Industry Standard Architecture, EISA) bus, etc. The communication bus may be classified as an address bus, a data bus, a control bus, or the like.
The communication interface is used for communication between the electronic device and other devices.
The processor may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU), a network processor (Network Processor, NP), etc.; but also digital signal processors (Digital Signal Processing, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), field programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.
The computer device may be: desktop computers, portable computers, intelligent mobile terminals, servers, etc. Any electronic device capable of implementing the present invention is not limited herein, and falls within the scope of the present invention.
For a computer device/storage medium embodiment, the description is relatively simple as it is substantially similar to the method embodiment, and reference is made to the description of part one of the method embodiments for relevant points.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Further, one skilled in the art can engage and combine the different embodiments or examples described in this specification.
Although the present application has been described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the figures, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, apparatus, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects all generally referred to herein as a "module" or "system. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein. A computer program may be stored/distributed on a suitable medium supplied together with or as part of other hardware, but may also take other forms, such as via the Internet or other wired or wireless telecommunication systems.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In the description of the present invention, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (10)
1. A netlist-level circuit area optimization method based on an and gate inverter diagram, comprising:
step 1, obtaining a first netlist level circuit file;
step 2, obtaining connection relations between a plurality of first nodes and each first node according to the first netlist level circuit file and a preset sequence, wherein the first nodes are input nodes, intermediate nodes or output nodes;
step 3, correspondingly creating the first node as a second node of an AND gate/inverter graph based on the preset sequence, and when a local substructure exists in the second node, searching an isomorphic structure of the local substructure in a hash table by using a hash searching method to obtain a creation result of the second node, wherein the second node is an initial node, a AND node, an inverter node or a terminal node;
and 4, processing the next first node according to the method of the step 3 based on the preset sequence until all the first nodes are processed, and obtaining a final AND gate/inverter diagram.
2. The netlist-level circuit area optimization method of claim 1, wherein creating the first node correspondence as a second node of an and/inverter graph based on the preset order comprises:
based on the preset sequence, when the first node is the input node, the second node is the initial node, when the first node is the intermediate node, the second node is the AND node, when the first node is the output node, the second node is the terminal node, and when there is an inverting input between the two connected first nodes, the inverter node is created between the two first nodes having inverting inputs.
3. The netlist-level circuit area optimization method of claim 1, wherein searching isomorphic structures of the local substructures in a hash table using a hash lookup method to obtain the creation result of the second node comprises:
obtaining an address index of an output logic value according to the local substructure;
and searching whether the output logic value exists in the address index in a hash table by utilizing a hash searching method, if the output logic value does not exist, the second node is created if the second node does not exist in an isomorphic structure, and if the output logic value exists, the second node is not created if the second node exists in an isomorphic structure.
4. A method of netlist-level circuit area optimization according to claim 3, wherein deriving an address index of the output logic value from the local substructures comprises:
obtaining an output logic value according to the local substructure;
and obtaining the address index of the output logic value according to the hash function.
5. A method of netlist-level circuit area optimization according to claim 3, wherein if the output logic value is absent, a correspondence of the output logic value of the local substructure and the address index is created in the hash table.
6. The netlist-level circuit area optimization method of any of claims 3-5, the output logic values comprising a first output logic value and a second output logic value, wherein the second output logic value is the first output logic value after swapping a place.
7. The netlist-level circuit area optimization method of any of claims 6, the first and second output logic values comprising an input relationship and inverter properties of the second node.
8. The method of netlist-level circuit area optimization of claim 1, wherein the local substructure is a structure of a second node to be currently created and a second node preceding and connected to the second node.
9. The netlist-level circuit area optimization method of claim 1, further comprising, after the step 4:
and restoring the final AND gate/inverter diagram to a second netlist-level circuit file.
10. A computer readable storage medium, characterized in that the computer readable storage medium has stored therein a computer program which, when executed by a processor, implements the steps of the method of any of claims 1-9.
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