CN115828803A - Netlist reduction method, chip verification method and computer storage medium - Google Patents
Netlist reduction method, chip verification method and computer storage medium Download PDFInfo
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Abstract
According to the netlist reduction method, the chip verification method and the computer storage medium, when the number of the connecting nodes of the target node is larger than the number threshold, the target node is eliminated, one part of the connecting resistors is subjected to equivalent transformation, the other part of the connecting resistors is transferred to one of the connecting nodes, the nodes can be eliminated, the number of the resistors is prevented from being increased, the netlist reduction efficiency can be improved, and the error rate is small. The netlist reduction method comprises the following steps: acquiring a target node to be eliminated in the netlist, wherein the target node is connected with a connecting node through a connecting resistor; and when the number of the connection nodes of the target node is larger than the number threshold, eliminating the target node, performing equivalent transformation on one part of the connection resistor, and transferring the other part of the connection resistor to one of the connection nodes.
Description
Technical Field
The present application relates to the field of chip technologies, and in particular, to a netlist reduction method, a chip verification method, and a computer storage medium.
Background
As the scale and complexity of chips continue to increase, the role of chip verification becomes more and more important. In the verification link of the chip, a parasitic resistance capacitance circuit netlist (netlist for short) obtained by extracting parasitic parameters is transmitted to subsequent time sequence verification. Thus, the size of the netlist directly affects the runtime of subsequent timing verification.
In order to shorten the running time of the verification link and accelerate the iteration cycle of the chip, a reduction (reduction) process needs to be performed on the large-scale netlist so as to reduce at least one of the number of nodes and the number of resistors of the large-scale netlist while maintaining the equivalence of the netlist. However, the existing netlist reduction method may increase the number of resistors in the netlist while eliminating nodes, thereby resulting in inefficient netlist reduction.
Disclosure of Invention
In view of the above technical problems, the present application provides a netlist reduction method, which can avoid the increase of the number of resistors while eliminating nodes, thereby improving the reduction efficiency of the netlist.
Technical scheme one
A netlist reduction method, comprising the steps of:
acquiring a target node to be eliminated in the netlist, wherein the target node is connected with a connecting node through a connecting resistor;
after judging whether the number of the connection nodes of the target node is larger than a number threshold value, then:
in case one, when the number of the connection nodes of the target node is greater than the number threshold, the target node is eliminated, and one part of the connection resistors is subjected to equivalent transformation, and the other part of the connection resistors is transferred to one of the connection nodes;
and in case two, when the number of the connection nodes of the target node is not greater than the number threshold, eliminating the target node and performing equivalent transformation on the connection resistance.
The netlist reduction method is characterized in that the first case specifically comprises the following steps:
performing equivalent transformation on the connecting resistor with the resistance value smaller than the resistance threshold value; and transferring the connection resistance having the resistance value not less than the resistance threshold to one of the connection nodes.
The netlist reduction method is characterized in that the resistance threshold is determined according to the minimum value of the resistance values of the connection resistors.
In the netlist reduction method, in the first case, the "one of the connection nodes" is a connection node corresponding to a connection resistance having a minimum resistance value.
The netlist reduction method is characterized in that the equivalent transformation is carried out on the connecting resistance with the resistance value smaller than the resistance threshold, and the method is specifically realized by adopting a TICER algorithm.
The netlist reduction method is characterized in that the number threshold is greater than or equal to 3.
The netlist reduction method is characterized in that a target node to be eliminated in the netlist is obtained, and the realization method comprises the following steps:
acquiring a time constant of a node to be confirmed in the netlist;
and when the time constant of the node to be confirmed is not in a preset frequency range, determining the node to be confirmed as the target node to be eliminated.
The netlist reduction method is characterized in that the netlist reduction method further comprises:
and when judging that the nodes to be confirmed exist in the netlist, performing a step of acquiring a time constant of the nodes to be confirmed in the netlist.
Technical scheme two
A method of chip verification, comprising:
the netlist reduction method generates a netlist after the nodes are eliminated;
and performing time sequence verification according to the netlist after the node elimination.
Technical scheme three
A computer storage medium, wherein a computer program is stored on the readable storage medium, and when executed by a processor, implements the netlist reduction method.
According to the netlist reduction method, the netlist reduction chip verification method and the computer storage medium, when the number of the connection nodes of the target node is larger than the number threshold value, the target node is eliminated, one part of the connection resistors is subjected to equivalent transformation, the other part of the connection resistors is transferred to one of the connection nodes, the nodes can be eliminated, the number of the resistors is prevented from being increased, the netlist reduction efficiency can be improved, and the error rate is small.
Drawings
FIG. 1 is a flowchart illustrating a netlist reduction method according to a first embodiment of the present application;
FIG. 2 is a schematic diagram illustrating comparison of netlist structures before and after node elimination according to an embodiment of the application;
FIG. 3 is a flowchart illustrating a netlist reduction method according to a second embodiment of the application.
Detailed Description
The following description of the embodiments of the present application is provided for illustrative purposes, and other advantages and capabilities of the present application will become apparent to those skilled in the art from the present disclosure.
In the following description, reference is made to the accompanying drawings that describe several embodiments of the application. It is to be understood that other embodiments may be utilized and that mechanical, structural, electrical, and operational changes may be made without departing from the spirit and scope of the present application. The following detailed description is not to be taken in a limiting sense, and the scope of embodiments of the present application is defined only by the claims of the issued patent. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
Although the terms first, second, etc. may be used herein to describe various elements in some instances, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.
Also, as used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes" and/or "including," when used in this specification, specify the presence of stated features, steps, operations, elements, components, items, species, and/or groups, but do not preclude the presence, or addition of one or more other features, steps, operations, elements, components, species, and/or groups thereof. The terms "or" and/or "as used herein are to be construed as inclusive or meaning any one or any combination. Thus, "a, B or C" or "a, B and/or C" means "any of the following: a; b; c; a and B; a and C; b and C; A. b and C ". An exception to this definition will occur only when a combination of elements, functions, steps or operations are inherently mutually exclusive in some way.
First embodiment
FIG. 1 is a flowchart illustrating a netlist reduction method according to a first embodiment of the present application. As shown in FIG. 1, a netlist reduction method includes the following steps:
acquiring a target node to be eliminated in the netlist, wherein the target node is connected with the connecting node through a connecting resistor;
judging whether the number of the connection nodes of the target node is greater than a number threshold value or not;
when the number of the connecting nodes is larger than the number threshold value, eliminating the target node, carrying out equivalent transformation on one part of the connecting resistor, and transferring the other part of the connecting resistor to one of the connecting nodes;
and when the number of the connection nodes of the target node is not greater than the number threshold, eliminating the target node and carrying out equivalent transformation on the connection resistance.
In one embodiment, obtaining the target node to be eliminated in the netlist may include, but is not limited to: acquiring a time constant of a node to be confirmed in the netlist; and when the time constant of the node to be confirmed is not in the preset frequency range, determining the node to be confirmed as a target node to be eliminated.
The time constant of the node to be verified is the total capacitance of the node to be verified to other nodes and to ground divided by the total conductance of the node to be verified to other nodes and to ground. By comparing the time constant of the node to be confirmed with the preset frequency range, the node to be confirmed whose time constant is not within the preset frequency range can be classified as a fast node or a slow node, and the node to be confirmed whose time constant is within the preset frequency range can be classified as a general node (or referred to as a common node). The fast node and the slow node have little influence on the system performance in the concerned frequency range, so that the fast node and the slow node, namely the node to be confirmed with the time constant not in the preset frequency range, can be determined as the target node to be eliminated, and then the target node to be eliminated is eliminated from the netlist, so as to reduce the scale of the netlist. The preset frequency range can be preset by a system, and can also be set by a user according to requirements.
In one embodiment, when the number of the connection nodes is greater than the number threshold, eliminating the target node and performing equivalent transformation on a part of the connection resistance and transferring the other part to one of the connection nodes includes: performing equivalent transformation on the connecting resistor with the resistance value smaller than the resistance threshold value; and transferring the connecting resistance with the resistance value not less than the resistance threshold value to one of the connecting nodes.
In one embodiment, the resistance threshold is determined according to a minimum value among resistance values of the connection resistance. Specifically, the resistance threshold may be R = t × R1, where t is a preset value and R1 is a minimum value of the resistance values of the connection resistance. Where t can be confirmed from the upper limit of the error rate. In other embodiments, the resistance threshold may be other values that are preset by the system or input by the user.
In one embodiment, in order to reduce errors due to node elimination, a connection resistor having a resistance value not less than a resistance threshold value may be shifted to a connection node corresponding to a connection resistor having a minimum resistance value. In other embodiments, a connection resistance having a resistance value not less than the resistance threshold value may be transferred to another connection node.
In one embodiment, the equivalent transformation of the connection resistance may be performed by using a Time Constant equalization Reduction (TICER) algorithm. In other embodiments, other algorithms may be used to perform equivalent transformation on the connection resistance, and the application is not limited thereto.
Specifically, if the target node to be eliminated is correspondingly connected with the m connection nodes through the first to mth connection resistors R1 to Rm in sequence, and m is greater than the number threshold, the resistance values of the first to mth connection resistors R1 to Rm are gradually increased. If the resistance values of the first to nth connecting resistors R1 to Rn are all smaller than the resistance threshold value R, the resistance values of the n +1 th to mth connecting resistors R (n + 1) to Rm are larger than the resistance threshold value R, wherein n is smaller than m. The first to nth connection resistors R1 to Rn are equivalently transformed, and the resistance values of the (n + 1) th to mth connection resistors are transferred to other connection nodes, for example, to the first connection node corresponding to the first connection resistor R1. Illustrated in fig. 2:
taking m equal to 6,n equal to 3,r = t × R1 as an example, as shown in (a) of fig. 2, a target node 0 to be eliminated is connected to 6 connection nodes 1, 2, 3, 4, 5, 6 in sequence through first to sixth connection resistors R1, R2, R3, R4, R5, R6, respectively, wherein resistance values of the first to third connection resistors R1, R2, R3 are all smaller than a resistance threshold value R, and resistance values of the fourth to sixth connection resistors R4, R5, R6 are all larger than the resistance threshold value R, as shown in (b) of fig. 2, the target node 0 is eliminated, and resistance values of the first to third connection resistors R1, R2, R3 are equivalently converted, for example, by a TICER algorithm, and the fourth to sixth connection resistors R4, R5, R6 are transferred to the first to sixth connection resistors R1, R2, R3.
Specifically, the equivalent transformation of the first to third connecting resistors R1, R2, and R3 by the above tic er algorithm may be:
a new resistor is inserted between any two adjacent connection nodes among the first connection node 1, the second connection node 2, and the third connection node 3, as shown in fig. 2 (b), the first new resistor r1 is inserted between the first connection node 1 and the second connection node 2, the second new resistor r2 is inserted between the second connection node 1 and the third connection node 2, and the third new resistor r3 is inserted between the first connection node 1 and the third connection node 3. The conductance of the first new resistor R1 is equal to g1g 2/(g 1+ g2+ g 3), the conductance of the second new resistor is equal to g2g 3/(g 1+ g2+ g 3), and the conductance of the third new resistor R3 is equal to g1g 3/(g 1+ g2+ g 3), where g1 is the conductance of the first connecting resistor R1, g2 is the conductance of the second connecting resistor R2, and g3 is the conductance of the third connecting resistor R3.
According to the netlist reduction method, when the number of the connection nodes of the target node is larger than the number threshold value, the target node is eliminated, one part of the connection resistors is subjected to equivalent transformation, the other part of the connection resistors is transferred to one of the connection nodes, the nodes can be eliminated, the increase of the number of the resistors is avoided, the reduction efficiency of the netlist can be improved, and the error rate is small.
Second embodiment
As shown in fig. 3, the netlist reduction method of the present embodiment includes the following steps:
step S30: obtaining a node to be confirmed in the netlist;
in one embodiment, the nodes to be validated in the netlist are obtained by traversing the netlist. Traversing the netlist means sequentially accessing each node in the netlist along a search route. The operation performed by the access node may be to check the value of the node, update the value of the node, etc.
Step S31: acquiring a time constant of a node to be confirmed in the netlist;
step S32: judging whether the time constant of the node to be confirmed is in a preset frequency range or not;
if the time constant of the node to be confirmed is within the non-preset frequency range, step S33 is performed: determining a node to be confirmed as a target node to be eliminated;
step S34, judging whether the number of the connection nodes of the target node is larger than a number threshold value;
if the number is greater than the number threshold, the process proceeds to step S35: eliminating the target node, carrying out equivalent transformation on one part of the connecting resistor, and transferring the other part of the connecting resistor to one of the connecting nodes;
if not, the process proceeds to step S36: eliminating a target node, and carrying out equivalent transformation on the connecting resistor;
in an embodiment, the number threshold may be preset by, but not limited to, a system, or may be set by a user according to a requirement, and when the tie algorithm is used to perform the equivalent transformation on the connection resistance, the number threshold may be, for example, 3 or an integer greater than 3. Specifically, since the tic er algorithm inserts a new resistor between any two adjacent connection nodes when the target node is eliminated, if the number of connection resistors before the target node is eliminated is N, the number of connection resistors after the target node is eliminated (the inserted new resistor) is N (N-1)/2. Therefore, when N is greater than 3, the number of connection resistors generated after the target node is eliminated is greater than the original number of connection resistors, so in an embodiment, the number threshold may be set to 3, so that when the number of connection nodes is greater than 3 or not greater than 3, the problem of low reduction efficiency of the netlist due to the increase of the number of resistors after the target node is eliminated can be avoided.
In one embodiment, the netlist reduction method further comprises:
step S37: judging whether a node to be confirmed exists in the netlist;
in one embodiment, step S35 may be executed after the target node is eliminated and the equivalent transformation and/or transfer processing is performed on the connection resistance: eliminating the target node, performing equivalent transformation on one part of the connection resistance, and transferring the other part to one of the connection nodes, or executing the step S36: eliminating the target node, performing equivalent transformation on the connection resistance, and then entering the step S37: judging whether the netlist has the node to be confirmed or not, and after step S33 is executed, determining the node to be confirmed as the target node to be eliminated, directly entering step S37: and judging whether the nodes to be confirmed exist in the netlist.
If the node to be confirmed exists, the step S30 is returned to: acquiring nodes to be confirmed in the netlist;
in one embodiment, the netlist reduction method further comprises:
if the time constant of the node to be confirmed is within the preset frequency range, the method proceeds to step S37: and judging whether the nodes to be confirmed exist in the netlist.
In an embodiment, whether a node to be confirmed exists in the netlist can be determined by determining whether traversal of the netlist is completed, specifically, if traversal of the netlist is completed, it is determined that the node to be confirmed does not exist in the netlist, and if traversal of the netlist is not completed, it is determined that the node to be confirmed exists in the netlist.
The netlist reduction method of the embodiment can confirm the target node through the time constant, the netlist reduction efficiency is improved, when the number of the connecting nodes of the target node is larger than the number threshold value, the connecting resistors are divided into two parts, one part is subjected to equivalent transformation, the other part is transferred to one of the connecting nodes, when the number of the connecting nodes of the target node is not larger than the number threshold value, all the connecting resistors are subjected to equivalent transformation, the target node can be eliminated, meanwhile, the increase of the number of the connecting resistors is avoided, the error rate is reduced, and the netlist reduction efficiency can be further improved.
The application also provides a chip verification method, which comprises the steps of generating a netlist after nodes are eliminated according to the netlist reduction method; and performing time sequence verification according to the netlist after the node elimination.
The embodiment of the present application further provides an intelligent terminal, including: the device comprises a memory and a processor, wherein the memory is stored with an operating program, and the operating program realizes the steps of any one of the methods when being executed by the processor.
Embodiments of the present application further provide a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the computer program implements the steps of any one of the above methods.
In the embodiments of the intelligent terminal and the computer-readable storage medium provided in the present application, all technical features of any one of the above-described embodiments of the interaction method may be included, and the expanding and explaining contents of the specification are basically the same as those of the above-described embodiments of the method, and are not described herein again.
Embodiments of the present application also provide a computer program product, which includes computer program code, when the computer program code runs on a computer, the computer is caused to execute the method in the above various possible embodiments.
The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.
The steps in the method of the embodiment of the application can be sequentially adjusted, combined and deleted according to actual needs.
The units in the device in the embodiment of the application can be merged, divided and deleted according to actual needs.
In the present application, the same or similar term concepts, technical solutions and/or application scenario descriptions will be generally described only in detail at the first occurrence, and when the description is repeated later, the detailed description will not be repeated in general for brevity, and when understanding the technical solutions and the like of the present application, reference may be made to the related detailed description before the description for the same or similar term concepts, technical solutions and/or application scenario descriptions and the like which are not described in detail later.
In the present application, each embodiment is described with an emphasis on the description, and reference may be made to the description of other embodiments for parts that are not described or recited in any embodiment.
The technical features of the technical solution of the present application may be arbitrarily combined, and for brevity of description, all possible combinations of the technical features in the embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, the scope of the present application should be considered as being described in the present application.
The above embodiments are merely illustrative of the principles and utilities of the present application and are not intended to limit the application. Any person skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present application. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical concepts disclosed in the present application shall be covered by the claims of the present application.
Claims (10)
1. A netlist reduction method, comprising the steps of:
acquiring a target node to be eliminated in the netlist, wherein the target node is connected with a connecting node through a connecting resistor;
after judging whether the number of the connection nodes of the target node is larger than a number threshold value, then:
in case one, when the number of the connection nodes of the target node is greater than the number threshold, the target node is eliminated, and one part of the connection resistors is subjected to equivalent transformation, and the other part of the connection resistors is transferred to one of the connection nodes;
and in case two, when the number of the connection nodes of the target node is not greater than the number threshold, eliminating the target node and performing equivalent transformation on the connection resistance.
2. The netlist reduction method of claim 1, wherein case one specifically includes:
performing equivalent transformation on the connecting resistor with the resistance value smaller than the resistance threshold value; and transferring the connection resistance having the resistance value not less than the resistance threshold value to one of the connection nodes.
3. The netlist reduction method of claim 2, wherein the resistance threshold is determined from a minimum of the resistance values of the connection resistances.
4. The netlist reduction method according to claim 1 or 2, wherein in case one, the "one of the connection nodes" is a connection node corresponding to a connection resistance having a smallest resistance value.
5. The netlist reduction method of claim 2, wherein the "equivalent transformation of connection resistances with resistance values smaller than the resistance threshold" is implemented using a TICER algorithm.
6. The netlist reduction method of claim 1, wherein the number threshold is greater than or equal to 3.
7. The netlist reduction method of claim 1, wherein the target node to be eliminated in the netlist is obtained by:
acquiring a time constant of a node to be confirmed in the netlist;
and when the time constant of the node to be confirmed is not in a preset frequency range, determining the node to be confirmed as the target node to be eliminated.
8. The netlist reduction method of claim 7, further comprising:
and when judging that the nodes to be confirmed exist in the netlist, obtaining a time constant of the nodes to be confirmed in the netlist.
9. A method of chip verification, comprising:
the netlist reduction method according to any one of claims 1 to 8, generating a netlist after node elimination;
and performing time sequence verification according to the netlist after the node elimination.
10. A computer storage medium, characterized in that the readable storage medium has stored thereon a computer program which, when executed by a processor, implements a netlist reduction method as claimed in any one of claims 1-9.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116882329A (en) * | 2023-09-06 | 2023-10-13 | 杭州行芯科技有限公司 | Netlist reduction method, time sequence verification method, electronic equipment and storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116882329A (en) * | 2023-09-06 | 2023-10-13 | 杭州行芯科技有限公司 | Netlist reduction method, time sequence verification method, electronic equipment and storage medium |
| CN116882329B (en) * | 2023-09-06 | 2023-12-19 | 杭州行芯科技有限公司 | Netlist reduction method, time sequence verification method, electronic equipment and storage medium |
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