CN1510733A - Transistor integrated circuit optimization method for process transplantation - Google Patents
Transistor integrated circuit optimization method for process transplantation Download PDFInfo
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- CN1510733A CN1510733A CNA021581843A CN02158184A CN1510733A CN 1510733 A CN1510733 A CN 1510733A CN A021581843 A CNA021581843 A CN A021581843A CN 02158184 A CN02158184 A CN 02158184A CN 1510733 A CN1510733 A CN 1510733A
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Abstract
The present invention relates to a technique for optimizing automatically an integrated circuit of transistor stage designed with respect to one process to be another integrated circuit of transistor stage adapted to the other process. The object of the invention is to provide a software which can optimize automatically the physical dimension, the area and the property of the integrated circuit of transistor stage transplanted with respect to the process. The invention comprises the following steps: ( 1 ) dividing the circuit; ( 2 ) optimizing the circuit in unit; ( 3 ) optimizing the circuit in entirety; ( 4 ) verifying the circuit. The invention converts the optimization of a large circuit to the same of the limited kinds of basic unit circuits; optimizes the basic unit circuits using analytical method; accelerates the simulation of the circuit according to the result of the division thereof, shortening the time required for optimizing the circuit in entirety and analyzes the mismatch of the matching signal path, optimizing the key signal path.
Description
Technical field
The present invention relates to a kind of optimizing integrated circuit technology of the transistor level towards process transplanting, more particularly, the present invention relates to the transistor level integrated circuit Automatic Optimal that on a kind of integrated circuit technology, to design technical field for the integrated circuit of the transistor level that is fit to another kind of integrated circuit technology.
Technical background
When integrated circuit is carried out technological change, need be under the prerequisite that guarantees the circuit performance index, be integrated circuit under the new process conditions with the optimizing integrated circuit that designs in the past, make the area minimum.It comprises that the transplanting of transistor level circuit and the circuit of physical layout level transplanted for two steps.Directly the physical layout optimisation technique towards process transplanting not may realize, it must through transistor level circuit extraction, transistor level circuit optimization and physical layout regenerate this three step, therefore towards the transistor level integrated circuit technique particular importance of process transplanting.Area when the transistor level circuit is transplanted minimizes the physical size parameter that is reflected as circuit and minimizes, this transistor level circuit redesign automatic technology is for digital circuit comparative maturity, redesign to simulation or radio circuit and mixed signal circuit still is in the exploratory stage, the redesign of simulation now or radio frequency integrated circuit and composite signal integrated circuits mainly is to rely on designer's craft to finish, the performance of novel circuit depends critically upon designer's experience, design cycle is long, and makes mistakes easily.
Also there is now the circuit Automatic Optimal instrument of some transistor levels can partly realize redesign function towards process transplanting, but this class instrument mainly adopts the method for equal proportion convergent-divergent integrated circuit or the integrated circuit methods of improved equal proportion convergent-divergent that the transistor physics size of integrated circuit is optimized, its theoretical foundation is the main electrical parameter of MOS transistor, relevant as channel current, mutual conductance with the ratio of grid width W and the long L of grid, scaled down grid width and grid are long can not to influence these electrical parameters, and precondition is that the main models parameter remains unchanged; The utilization circuit emulator carries out the analog simulation assessment to the circuit of possibility size in these class methods, according to the physical size parameter of optimizing the trend adjustment circuit element, attempts to approach optimal solution.
Under grid width and the grid long value is all bigger and the main models parameter remains unchanged situation, grid width and grid length that equal proportion is adjusted MOS transistor are very little to the influence of mutual conductance and channel current, can ignore, but when grid width and grid long value are all smaller, grid width and grid length that equal proportion is adjusted MOS transistor not only have bigger influence to mutual conductance and channel current, and parasitic parameter had very big influence, be directly reflected as influence, to the influence of circuit work frequency scope to circuit working point; Therefore towards undersized process transplanting the time, it is infeasible utilizing the equal proportion convergent-divergent that the transistor level integrated circuit is carried out physical size optimization.
The circuit simulation that integrated circuit is carried out transistor level needs the long time, and simulation time increases with the scale of circuit; Existing transistor level integrated circuit physical size optimization tool need carry out emulation to entire circuit under difference trial condition, utilize emulation tool that Performance Evaluation is carried out in each trial, judge good and bad, do like this and can make optimization time lengthening, but also might not restrain, not may be optimized larger circuit.
Circuit integral body is optimized simultaneously, and its purpose is to obtain the result of global optimum, because the importance of the different piece of circuit is different, though can distinguish the importance of circuit each several part in the mode of weight.But the method for this global optimization circuit might cause local optimum rather than global optimum.
Though circuit size optimum, and the circuit simulation result confirms that also circuit performance meets the demands, such circuit not necessarily can realize in the physical layout one-level, because when optimizing circuit, do not consider the Butut ghost effect that allows.
Summary of the invention
The object of the invention is: the transistor level integrated circuit physical size Automatic Optimal Software tool towards process transplanting of realization, can be under the prerequisite that guarantees original circuit performance, automatically transistor level simulation that will design on a kind of technology and radio frequency integrated circuit are optimized for transistor level simulation and the radio frequency integrated circuit that is fit to another kind of technology apace, and area and performance all are optimized.
Another object of the present invention is: provide rational physical layout maximum spurious restrictive condition and avoid iteration between circuit optimization and the Butut process, mandatory restrictive condition when generating Butut automatically in circuit optimization.
The present invention is achieved in that the transistor level method for optimizing integrated circuit towards process transplanting, may further comprise the steps: (1) circuit is divided; (2) circuit unit optimization; (3) circuit global optimization; (4) Circuit verification.
Described transistor level method for optimizing integrated circuit towards process transplanting, circuit is wherein divided and is comprised the steps:
(1) circuit is divided into digital circuit and simulation or radio circuit;
(2) digital circuit is divided into basic gate circuit;
(3) will simulate or radio circuit is divided into signal circuit and biasing circuit;
(4) signal circuit is carried out the path that signal flow analysis draws each key signal;
(5) matched signal path example is turned to same electronic circuit;
(6) entire circuit is carried out the stratification reorganization;
(7) each electronic circuit is divided into some basic circuits unit.
Described transistor level method for optimizing integrated circuit towards process transplanting, circuit unit optimization wherein comprises the steps:
(1) gate circuit storehouse or the analytic expression based on transistor level is optimized basic gate circuit;
(2) based on the optimization of the basic element circuit of analytic expression;
(3) based on the complicated circuit unit optimization in new technology transistor level circuit unit storehouse.
Described transistor level method for optimizing integrated circuit towards process transplanting, circuit global optimization wherein comprises the steps: the optimization of (1) circuit DC characteristic; (2) optimization of circuit AC characteristic.
Described transistor level method for optimizing integrated circuit towards process transplanting, Circuit verification wherein comprises the steps: the high-speed simulation of (1) digital circuit; (2) high-speed simulation of simulation or radio circuit.
Step 1. circuit division comprises that the comprehensive restrictive condition of physical layout generates automatically; Rule-based signal flow analysis.
Step 3. circuit global optimization comprises mismatch analysis between parasitic restrictive condition optimization of physical layout and the matched signal path; Wherein the comprehensive restrictive condition of physical layout generates automatically and comprises transverse branch and the vertically division of branch on the key signal path.
Step 1. circuit divides shared element and node division between the key signal path are come out, and is optimized separately.
Transistor level simulation that designs on a kind of technology or radio frequency integrated circuit itself just embodied the requirement of user to circuit performance, and this requirement has refine on concrete circuit structure and the circuit elementary cell.Basis of the present invention is to guarantee that in process transfer the topological structure of circuit is constant, guarantees that the performance of circuit elementary cell is better than the performance of former circuit elementary cell, thereby the overall performance of guaranteeing circuit is better than the performance of circuit in the past, and the circuit area minimum.Its key is to divide digital circuit and simulation or radio circuit, adopts different optimization methods to be optimized digital circuit with simulation or radio circuit; Digital circuit is divided into basic gate circuit, the optimization problem of digital circuit is converted into the optimization problem of basic gate circuit; Division signals circuit and biasing circuit separately are optimized signal circuit and biasing circuit; Signal circuit is divided into key signal path by key signal, for the same electronic circuit of critical path exampleization of coupling, so that adopt the optimal way of stratification to guarantee the key signal path coupling and the shortening optimization time of original circuit; Each electronic circuit is divided into some basic circuits unit, the optimization problem of big circuit is converted into the basic element circuit optimization problem of limited kinds, thereby simplified complicated originally optimization problem; Optimize original basic gate circuit based on the gate circuit library unit of new technology or the analytical expression of elementary gate; Based on the optimization of the basic circuit unit of analytic expression, need not when optimizing, to adopt the transistor level circuit simulation tools to carry out the circuit performance assessment; The optimization of the physical size by each basic circuit unit realizes the physical size optimization of entire circuit; The interface in basic element circuit storehouse is provided, and the user can self-defined basic element circuit and the analytic expression that is used to optimize, supports the optimization to comparatively complicated elementary cell; After each circuit unit all is optimized, circuit is carried out global optimization, optimize the DC characteristic and the AC characteristic of circuit; Transistor level circuit after utilization bandwidth estimation technology is guaranteed to optimize can be realized by physical layout; Accelerate circuit simulation speed according to division result, shorten the circuit global optimization time circuit; The mismatch analysis is carried out in the matched signal path, optimized key signal path; Mandatory restrictive condition when generating the physics layout synthesis automatically according to circuit division result, the circuit after the optimization of parasitic restrictive condition is guaranteed to optimize can be realized by physical layout.
The transistor level integrated circuit physical size optimization tool of realizing according to the present invention towards process transplanting, optimal speed is fast, support is optimized very large-scale circuit, also optimized circuit performance when optimizing circuit area, automatically the Butut restrictive condition that generates can be used for follow-up craft or automatic graph generation, and the parasitic restrictive condition of optimization can be avoided the iteration between circuit optimization and the Butut process.
In integrated circuit (IC) design, designing multiplexing is a very important problem, because the utilization again of design achievement can improve design efficiency, reduces design cost.Design and multiplexingly be divided into that high-rise design is multiplexing, gate leve design design multiplexing, transistor level design multiplexing and the physical layout level is multiplexing, its design on the middle and senior level is multiplexing and the gate leve design is multiplexing only at digital circuit, simulation/radio circuit and mixed signal circuit still are in the exploratory stage in the design of this two-stage, design multiplexing far from.There is not any technical problem under the multiplexing situation that does not have to change in integrated circuit technology of physical layout level, under the situation that process conditions change, need redesign physical layout, directly the redesign physical layout is very unrealistic, past, many trials all proved this point, therefore the redesign of physical layout must be taken a three-stage approach, promptly the circuit extraction of transistor level, optimize and the regeneration of physical layout towards the integrated circuit physical size of the transistor level of process transplanting.The regeneration of physical layout can finish by hand by the layout design personnel, the integrated circuit of optimizing good transistor level is carried out that Butut obtains or obtain by the above two combination by means of automatic placement and routing's instrument, relevant regenerate the method for physical layout automatically according to the integrated circuit of optimizing good transistor level can be with reference to other relevant document or patent.
The integrated circuit (IC) design of transistor level is multiplexing to comprise two aspects, and the design between the multiplexing and different integrated circuit technologies of design in the same integrated circuit technology is multiplexing.Transistor level in the same integrated circuit technology designs multiplexing fairly simple, and the circuit of transistor level can directly utilize again, and is fine as long as circuit design in the past gets, and need not to do any optimization.The multiplexing design that is reflected as more from old process transplanting to new technology of design between the different integrated circuit technologies is multiplexing, the benefit of this process transplanting is, less electric charge shifts to be needed and less signal distance, and less element has switch transition faster, thereby circuit speed is fast; The reduction of characteristic line breadth makes can make more chip on each silicon chip, and unit cost has reduced; On a production line, can make more products, improve the utilance of production line, thereby reduce the production cost relevant with the production line utilance.New integrated circuit technology is compared with old integrated circuit technology, except that model parameter changes, the most direct variation is that characteristic line breadth reduces, in order to effectively utilize the advantage of new technology, must utilize characteristic line breadth fully, dwindle the area of each element as much as possible, thereby reach the area that dwindles entire circuit, this is an area-optimized process.The area-optimized optimization that is directly reflected as the circuit element physical size is better than original circuit but precondition is a circuit performance, at least with suitable in the past.
Integrated circuit (IC) design develops to the chip system direction, Circuits System more than 60% contains simulation/radio circuit subsystem or mixed signal subsystem, the multiplexing design to chip system of the design of transistor level and domain level is most important, integrated circuit technology is also constantly advancing, and simulation in the past or radio frequency integrated circuit and the digital and analog mixed signal integrated circuit overwhelming majority design on old technology, so are necessary to realize the integrated circuit physical size optimization tool towards the transistor level of process transplanting fully.
Analyze existing instrument and list of references, the optimization method that carries out Performance Evaluation based on equal proportion convergent-divergent and circuit simulation can not solve the transistor level integrated circuit physical size optimization problem towards process transplanting practically.The present invention is with the transistor level integrated circuit physical size optimization problem of another approach solution towards process transplanting, be circuit element the geometric Parameters Optimization problem, its target is that speed is fast, support the optimization of large-scale circuit, the circuit area of optimization is little, circuit performance is high, in circuit optimization, provide rational physical layout maximum spurious restrictive condition and avoid iteration between circuit optimization and the Butut process, mandatory restrictive condition when generating Butut automatically.
Transistor level integrated circuit DC characteristic that designs and AC characteristic index are reflected on the component parameters of its circuit topological structure and basic circuit unit.If the performance of each basic circuit unit is better than former performance, the overall circuit performance after then optimizing must be better than former circuit.Therefore, redesign (optimization) problem of big circuit can be converted into the optimization problem of little circuit, big circuit can be decomposed into some basic element circuits, and the optimization of so big circuit finally is converted into the optimization of basic element circuit; The electrology characteristic of basic element circuit can be represented with fairly simple analytic expression, and this all can find on general integrated circuit reference book, adopts analytical expression to find the solution the optimal solution of basic element circuit.
Description of drawings:
Fig. 1 is a flow chart of the present invention.
Fig. 2 is the circuit stratification recombination structure schematic diagram that the present invention relates to.
Embodiment:
The present invention will be further described below in conjunction with accompanying drawing and following indefiniteness embodiment.
As shown in Figure 1, a kind of optimizing integrated circuit technology of the transistor level towards process transplanting, at first circuit is divided into digital circuit and simulation or radio circuit: a complete Circuits System generally includes digital circuit subsystem and simulation or radio circuit subsystem, because the operating characteristic of the characteristic of digital circuit and simulation or radio circuit is different, be necessary these two parts are taked different optimization methods, and the optimization of digital circuit relatively, the optimization more complicated of simulation or radio circuit, in order to optimize entire circuit better, this just must divide them and come.The digital circuit of transistor level is not seen relevant reported in literature with simulation or radio circuit division methods, and we adopt the division methods of the signal flow analysis of rule-based driving.
If a circuit element connects the power supply or the ground of simulation or radio circuit, then this element belongs to simulation or radio circuit;
If a circuit element connects simulation or radiofrequency signal node, then this element belongs to simulation or radio circuit;
If the grid of a field-effect transistor connects simulation or radiofrequency signal node, then the node that is connected with source electrode of the drain electrode of this element is simulation or radiofrequency signal node;
If the drain electrode of a field-effect transistor connects simulation or radiofrequency signal node, then the node that source electrode connected of this element is a simulation/radiofrequency signal node;
If the source electrode of a field-effect transistor connects simulation or radiofrequency signal node, then the node that the drain electrode of this element connected is simulation or radiofrequency signal node;
If the base stage of a bipolar transistor connects simulation or radiofrequency signal node, then the node that the collector and emitter of this element connected is simulation or radiofrequency signal node;
If the collector electrode utmost point of a bipolar transistor connects simulation or radiofrequency signal node, then the node that the emitter of this element connected is simulation or radiofrequency signal node;
If the emitter of a bipolar transistor connects simulation or radiofrequency signal node, then the node that the collector electrode of this element connected is simulation or radiofrequency signal node;
If resistance, electric capacity, an inductance belong to simulation/radio circuit, then the node that this element connected is simulation or radiofrequency signal node.
The power supply of the necessary given simulation/radio circuit of user and ground and input and output pin, partition program is determined to belong to the element of simulation or radio circuit and is propagated simulation or radiofrequency signal by above rule, until not finding new simulation or radiofrequency signal node, the element that will belong to simulation or radio circuit at last constitutes simulation or radio frequency electronic circuit, all the other elements then constitute digital sub-circuit, and so original top layer circuit just is divided into digital sub-circuit part and simulation or radio frequency sub-circuit portion.
Digital circuit is divided into basic gate circuit: basic gate circuit comprises inverter circuit, NAND gate circuit, OR-NOT circuit, same OR circuit, NOR gate circuit, various flip-flop circuits etc. in digital circuit, and basic gate circuit can find in the digital integrated circuit reference book.It is fairly simple that digital circuit is divided into elementary gate, adopts the isomorphism matching algorithm to search in digital circuit, digital circuit can be divided into basic gate circuit.Because the extractive technique from the circuit to the door is comparative maturity, does not describe in detail at this.
To simulate or radio circuit is divided into signal circuit and biasing circuit: in simulation or radio circuit, circuit element provides two big functions, the one, control and setting dc point, we claim that this part circuit is a biasing circuit, another part is to handle crucial simulation or radiofrequency signal, and we claim that this part circuit is a signal circuit.Because biasing circuit only is the dc point of control and initialization circuit, very little under the situation about satisfying condition in the working point to properties influence such as the speed of processing of circuit signal, amplification, filtering, its DC characteristic is satisfied in the optimization of biasing circuit to be required to get final product, optimization to signal circuit is quite different, and its DC characteristic and AC characteristic all must be met.Therefore, be necessary signal circuit and biasing circuit division are come, signal circuit and biasing circuit are adopted different optimization methods.Relevant bibliographical information is not seen in the division of signal circuit and biasing circuit, and we provide the division methods of the signal flow analysis of rule-based driving now.
Crucial simulation or the propagation rule of radiofrequency signal in field-effect transistor are: from the grid to the source electrode; From the grid to the drain electrode; From drain-to-source; From the source electrode to the drain electrode; Signal is propagated termination and power supply or ground, or output.
Crucial simulation or the propagation rule of radiofrequency signal in bipolar transistor are: from the base stage to the collector electrode; From the base stage to the emitter; From the collector electrode to the emitter; From the emitter to the collector electrode; Signal is propagated termination and power supply or ground, or output.
Crucial simulation or the propagation rule of radiofrequency signal in diode are: from anodal (P) to negative pole (N); Signal is propagated termination and power supply or ground, or output.
Crucial simulation or the propagation rule of radiofrequency signal in resistance, electric capacity and inductance are: from any end to end; Signal is propagated termination and power supply or ground, or output.
If any end of an element connect crucial simulation or radiofrequency signal the node of process, then this element belongs to signal circuit.When key signal is propagated the node of process, we are referred to as the key signal node, except power supply and the ground.
The user must given crucial simulation or radio-frequency input signals and output signal name.Signal circuit and analog circuit partition program according to given key simulation or radio-frequency input signals and output signal name from input propagation key signal, until no longer producing new key signal node, the element that the key signal node is connected belongs to signal circuit, all the other elements then belong to biasing circuit, have so just finished will simulate or radio circuit is divided into signal circuit and biasing circuit.
Signal circuit is carried out drawing by signal flow analysis the path of each key signal: signal circuit may be obtained by the mobile propagation of a plurality of key signals, each key signal the element of process only this signal is had very big influence, processing influence to all the other key signals is very little, complexity when simplifying circuit optimization, be necessary signal circuit is divided into some key signal path, key signal path by key signal the node of process and the set of the element that connected thereof.The present invention divides the difference that key signal path and the method for seeking the circuit critical path by circuit simulation tools have essence, and method of the present invention is not based on simulation calculation and is based on the flow analysis of key signal, is a kind of Graph-theoretical Approach of more broad sense.The signal flow analysis method of key signal path is the signal flow analysis of regular drive equally, and its rule also is that succession division signals circuit and biasing circuit carry out the rule that signal flow analysis adopted, but has following difference.1, to the propagation restriction of key signal in field-effect transistor: if the grid of field-effect transistor connects other key signal nodes, then key signal no longer flows to source electrode from drain electrode, also no longer flows to drain electrode from source electrode.2, to the propagation restriction of key signal in bipolar transistor: if the base stage of bipolar transistor connects other key signal nodes, then key signal no longer flows to emitter from collector electrode, also no longer flows to collector electrode from emitter.3, may share element and node between the key signal path, because shared portion all has bigger influence to two or more key signals, need the element of sharing be optimized separately, we divide them come out separately, be referred to as zipper unit, because it equally links together the coherent signal path to slide fastener.The part of each key signal path remainder constitutes electronic circuit respectively, is optimized separately, thus the optimization of simplification signal circuit.
Matched signal path example is turned to same electronic circuit: so far, signal circuit has been divided into zipper unit electronic circuit and a plurality of key signal path electronic circuit.In these a plurality of key signal path electronic circuits, may there be coupling between them, the inside connection and the component parameters that are two basic points or a plurality of key signal path electronic circuits are duplicate, this has embodied primary circuit designer's design philosophy and requirement, be that the multichannel function is just the same, this just needs the present invention when circuit optimization the key signal path of coupling to be appointed the maintenance coupling after optimizing.The key signal path example of coupling is turned to same electronic circuit, when optimizing, only need optimize wherein key signal path, the key signal path of all the other couplings only need be duplicated same optimization result, does like this and can accelerate optimal speed, simultaneously key signal path is mated fully.In this step, the present invention adopts the coupling between the circuit node connection matching technique judgement critical path.
Each electronic circuit is divided into some basic element circuits: in simulation/radio circuit, basic element circuit comprises that mainly common grid circuit, common source circuit, source are with device circuit, common sending out-common-base amplifier, differential pair, current mirror, current source, basic amplification grade circuit, operational amplifier, bandgap reference source circuit, mixting circuit and voltage-controlled oscillator circuit.For simple basic element circuit, basic element circuit is decomposed into certain characteristics, in electronic circuit, search for these features then, if all features of a basic element circuit all are met in electronic circuit, then Xiang Guan element can be designated this element circuit, and substitutes relevant elements with the exampleization of this basic element circuit.All basic element circuits are all searched for one time, thus identify the basic element circuit that might exist so that adopt corresponding optimization methods to be optimized to these basic circuit unit.For the element that is not designated basic element circuit, can adopt other optimization methods to be optimized.
The sign of the non-key element of sign in biasing circuit: there are some non-critical circuits elements in the biasing circuit, more simple for their optimization, therefore in order to accelerate the optimal speed of biasing circuit, be necessary to see that these non-critical circuitry element identifiers come out.The sign of non-key element is based on so rule: the field-effect transistor that is connected to electric capacity work is non-key element; The field-effect transistor that grid connects digital signal node is non-key element; The field-effect transistor that is connected to become inverter is if its grid connects digital signal node, and then its node that is connected that drains is the digital signal node.So propagate and find all possible digital signal node, thereby identify whole non-key elements by rule.
Entire circuit is carried out the stratification reorganization: the sign of elementary cell in the division of division, key signal path electronic circuit and the zipper unit circuit of division, signal circuit and the biasing circuit of process digital circuit and simulation or radio circuit, the extraction of digital gate circuit, the analog circuit, entire circuit has been reassembled as to stratification multistage electronic circuit, see accompanying drawing 2, its bottom is basic element circuit and digital gate circuit, also have the circuit element that some fail to identify in addition, but this can't influence the optimization of circuit.So far, the stratification of circuit is reassembled as and adopts different optimisation techniques to carry out the preparation of circuit piecemeal to the circuit different piece.
Gate circuit storehouse or analytic expression based on transistor level are optimized basic gate circuit: the optimization of basic gate circuit is fairly simple, mainly is to satisfy circuit performances such as rise time, fall time, driving force to get final product.According to this point, can be from satisfying the identical gate circuit of structure that circuit performance requires based on selecting the gate circuit storehouse of new technology, this method is the fastest.Not based on the gate circuit storehouse of new technology or can not find under the situation of gate circuit of Performance Match also the gate circuit physical size that can calculate optimum by the analytical expression of gate circuit and minimal characteristic live width and new model parameter.
Optimization based on the basic element circuit of analytic expression: for some simple basic element circuits, can provide the analysis expression of separating of describing its circuit performance, this can find in the relevant reference book of describing basic element circuit, does not list one by one at this.Basic parameter according to original basic element circuit utilizes analytical expression to calculate its circuit performance, require the performance equation group to be found the solution according to its electric property then with new characteristic line breadth and model parameter, in the hope of component parameters is as the initial value of optimizing again, adjust device parameter values and utilize analytic expression review performance whether improvement is arranged, until drawing optimum circuit element parameter.Solution procedure may be a direct solution procedure, also may be a numerical value solution procedure, and this structure with basic element circuit is relevant.
Complicated circuit unit optimization based on new technology transistor level circuit unit storehouse: the Automatic Optimal of complicated circuit unit is generally relatively more difficult, for the profuse engineer of some circuit design experiences, manual setting sometimes can make some complicated optimization problem oversimplify soon.Provide the new technology circuit unit bank interface of transistor level can give full play to the automatic calculating advantage of computer and designer's experience advantage, both advantage is perfectly combined, optimize circuit better.This storehouse can be provided or from the third party, the complicated circuit unit must be specified by the design engineer by design engineer oneself.
Basic element circuit optimization based on circuit simulation: adopt the analytical expression method can not solve the optimization problem of whole basic element circuits, because it is also very difficult sometimes to provide the analytical expression of circuit, this complexity with basic element circuit is relevant, at this moment can adopt the basic element circuit optimisation technique based on circuit simulation.Employing has based on the key step of the basic element circuit optimisation technique of circuit simulation: (1) carries out circuit simulation to original basic element circuit, obtains the performance index of basic element circuit and the electric property index of each element; (2) adjust by the physical geometry parameter to element of scaled down; (3) new basic element circuit is carried out circuit simulation, obtain the performance of circuit and the electric property of each element; (4) contrast basic element circuit performance and the electric property of counter element in each element comparison it and the primary circuit adjusted accordingly to component parameters; (5) repeat (3) and (4) performance until basic element circuit.
Circuit optimization technical speed based on circuit simulation is slow, when being used for small basic element circuit is optimized, though speed is fast not as good as analytic expression optimization speed, but because the quantity of element is fewer, directly adjust the component parameters of shadow, therefore can only need iteration of simulations number of times seldom just can finish optimization to circuit performance.In addition, it also can be used as a kind of useful the replenishing to the analytic expression optimization.
The optimization of the optimization of circuit DC characteristic and circuit AC characteristic: after the circuit various piece all is optimized, need carry out small adjustment to entire circuit, this is mainly finished by the optimization of DC characteristic and the optimization of AC characteristic.The small adjustment of circuit just mainly is the small adjustment of component parameters on the key signal path, adopts interval fine setting technology, and the assessment of characteristic utilizes follow-up quick verification technique and bandwidth estimation technology.
The quick checking of digital circuit: the digital circuit fast simulation technique of transistor level mainly is that the complex model that utilizes question blank to substitute single transistor calculates, stratification emulation substitutes individual layer emulation now, to accelerate simulation velocity; The quick verification step of our digital circuit is: (1) is each class gate circuit of emulation separately, and simulation result saves as the question blank of gate circuit; (2) with the gate circuit be the whole digital circuit of base unit emulation.Compare with the rapid simulation method of other digital circuits, it is advantageous that with the gate circuit to be that base unit has dwindled circuit scale and described the simulation velocity that the electricity behavior of gate circuit makes with question blank faster.
The high-speed simulation of simulation or radio circuit: the simulation of transistor level/radio frequency fast simulation technique also is that the complex model that utilizes question blank to substitute single transistor calculates basically; The quick verification step of our simulation/radio circuit is: (1) is the emulation basic element circuit separately, and simulation result saves as the question blank of basic element circuit; (2) biasing circuit is replaced with macro model; (3) with the basic element circuit be the whole simulation/radio circuit of base unit (but not transistor) emulation.Compare with the rapid simulation method of other simulation/radio circuits, it is advantageous that with the basic element circuit to be that base unit has dwindled circuit scale, substituted biasing circuit with macro model and accelerated the simulation velocity of non-critical circuitry especially and made simulation velocity faster with the electricity behavior that question blank is described basic element circuit.
The comprehensive restrictive condition of physical layout generates automatically: a complete transistor level circuit design is not represented in the design of only finishing circuit meshwork list, and it also must comprise the restrictive condition to follow-up physical layout design.These restrictive conditions were analysed circuit by physical layout design personnel hand work point and were obtained in the past, this is a mistake in fact, because the transistor level circuit designer will outclass the understanding of layout design personnel to this circuit to the understanding of self-designed circuit, therefore ought to provide the Butut restrictive condition by circuit designer.This Butut restrictive condition also comprises except that follow-up parasitic restrictive condition: the restrictive condition of functional block level; The device level restrictive condition; Connect restrictive condition.Wherein, the functional block level restrictive condition comprises pin positions and spacing, how much restrictive conditions, away from border or isolation, functional block symmetry, coupling or adjacency type, and the characteristic of functional block, as zipper unit, IP storehouse or inherit come the unit; The device level restrictive condition comprises the trend of grid of MOSFET and the kind of device, as whether on key signal path, on the transverse branch or in vertical branch, match-type be from symmetry, mirror image is symmetrical, or simply duplicate, match complexity is virtual coupling, basic coupling, common centroid coupling, the still coupling that crosses one another, and whether device top allows to connect up etc.; Connect restrictive condition and comprise and forbids wiring, node largest parasitic and resistance, maximum current, the line coupling, that disturbs mutually between line avoids etc.In fact when dividing, circuit implicitly identified most of restrictive condition, as the coupling of functional block, and the sign of signal path, the sign of device matching (sign of basic element circuit) etc.What need supplementary notes is transverse branch and the vertically division of branch on the signal path, and its rule is as follows:
1) signal path is from left to right imported on a left side, and output is on the right side, and positive supply is last, and negative supply and ground are following;
2) be transverse branch from being input to the node that output does the best;
3) node on the transverse branch is vertical branch to the path on power supply or ground.
The automatic generation of Butut restrictive condition helps the craft of the faster and better ground of layout design personnel or designs physical layout automatically.
The optimization of the parasitic restrictive condition of physical layout: check that the conventional method whether the transistor level circuit design adheres to specification is a circuit simulation, fact proved that this is not enough, because circuit simulation only considered element itself state-owned part ghost effect, do not consider to connect between the element ghost effect that causes, allow rational line ghost effect can avoid iteration between circuit design and the layout-design effectively, therefore be necessary to consider in circuit optimization the optimization of the parasitic restrictive condition of domain, the maximum that parasitic restrictive condition is expressed as on the connecting line allows electric capacity, resistance and inductance value.The optimization of the parasitic restrictive condition of physical layout: the calculating of (1) circuit working point; (2) based on the estimation of the bandwidth of open circuit time constant method; (3) the parasitic restrictive condition of estimation permission, and adjust bandwidth; (4) repetition (1), (2) and (3) can be realized until the parasitic restrictive condition that allows.
Mismatch analysis between the matched signal path: identified the coupling of functional block and the coupling of device level when circuit is divided, the circuit performance that utilizes circuit emulator to calculate under the various mismatch situations changes.Compare with circuit mismatch analysis in the past, the one, can Automatic Logos mismatch device, the 2nd, given maximum performance change is obtained the maximum mismatch permissible value automatically.
Claims (10)
1. towards the transistor level integrated circuit physical size optimization method of process transplanting, this method may further comprise the steps: 1. circuit is divided; 2. circuit unit optimization; 3. circuit global optimization; 4. the checking of circuit.
2. method according to claim 1 is characterized in that, described step 1. circuit division comprises the steps:
(1) circuit is divided into digital circuit and simulation or radio circuit,
(2) digital circuit is divided into basic gate circuit,
(3) will simulate or radio circuit is divided into signal circuit and biasing circuit,
(4) signal circuit is carried out the path that signal flow analysis draws each key signal,
(5) matched signal path example is turned to same electronic circuit,
(6) entire circuit is carried out the stratification reorganization,
(7) each electronic circuit is divided into some basic circuits unit.
3. method according to claim 1 and 2 is characterized in that, described step 2. circuit unit optimization comprises the steps:
(1) gate circuit storehouse or the analytic expression based on transistor level is optimized basic gate circuit,
(2) based on the optimization of the basic element circuit of analytic expression,
(3) based on the complicated circuit unit optimization in new technology transistor level circuit unit storehouse.
4. method according to claim 1 and 2 is characterized in that, described step 3. circuit global optimization comprises: the optimization of circuit DC characteristic, the optimization of circuit AC characteristic.
5. method according to claim 1 and 2 is characterized in that, the described step 4. checking of circuit comprises: the high-speed simulation of digital circuit; The high-speed simulation of simulation or radio circuit.
6. method according to claim 1 and 2 is characterized in that, described step 1. circuit division comprises that the comprehensive restrictive condition of physical layout generates automatically.
7. method according to claim 1 and 2 is characterized in that, described step 1. circuit division comprises rule-based signal flow analysis.
8. method according to claim 4 is characterized in that, described step 3. circuit global optimization comprises the optimization of the parasitic restrictive condition of physical layout and the mismatch analysis between the matched signal path.
9. method according to claim 6, the comprehensive restrictive condition of physical layout generate automatically and comprise transverse branch and the vertically division of branch on the key signal path.
10. method according to claim 1 and 2 is characterized in that, described step 1. circuit divides shared element and node division between the key signal path are come out, and is optimized separately.
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| CNA021581843A CN1510733A (en) | 2002-12-24 | 2002-12-24 | Transistor integrated circuit optimization method for process transplantation |
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| CNA021581843A CN1510733A (en) | 2002-12-24 | 2002-12-24 | Transistor integrated circuit optimization method for process transplantation |
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| CN102222599A (en) * | 2010-04-13 | 2011-10-19 | 中芯国际集成电路制造(上海)有限公司 | Method and device for optimizing technological process |
| CN102339341A (en) * | 2010-07-26 | 2012-02-01 | 中国科学院微电子研究所 | Method for automatically controlling extraction precision of parasitic parameters during physical layout simulation |
| CN102508977A (en) * | 2011-11-15 | 2012-06-20 | 中国科学院微电子研究所 | Circuit optimization method for artificial circuit transplant and circuit optimization device for artificial circuit transplant |
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| CN112560386A (en) * | 2020-12-09 | 2021-03-26 | 南京华大九天科技有限公司 | Large-scale complex layout resistance extraction acceleration method |
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