CN113971159B

CN113971159B - Programmable logic block based on improved lookup table structure

Info

Publication number: CN113971159B
Application number: CN202111265159.2A
Authority: CN
Inventors: 王彦林; 高丽江; 刘学刚; 秋小强; 贾一平; 杨海钢
Original assignee: Shandong Xinhui Microelectronics Technology Co ltd
Current assignee: Shandong Xinhui Microelectronics Technology Co ltd
Priority date: 2021-10-28
Filing date: 2021-10-28
Publication date: 2024-02-20
Anticipated expiration: 2041-10-28
Also published as: CN113971159A

Abstract

The invention discloses a programmable Logic block based on an improved lookup table structure, wherein each basic Logic unit of the programmable Logic block comprises two PLML (Programmable Logic Module-Logic) which are completely the same and mutually independent, and the programmable Logic block has independent input and output, a carry chain structure and a shift register chain structure; each PLML comprises an improved LUT module, a logic operation module, a trigger module, a multiplexer module and a shift register module; each PLML contains resources such as 4 modified double-output LUTs with three granularities, 4 adders, 4 triggers, a plurality of multiplexers and the like; each PLML can realize the LUT function, the sequential logic function, the logic operation function, the multiplexer function and the shift register function with stronger functions through the combination of the same or different resources, and can realize the register output. The invention has a plurality of input lookup table structures, can be mapped to the corresponding LUT according to the function requirement, avoids resource waste, and can realize more independent function functions with simple configuration.

Description

Programmable logic block based on improved lookup table structure

Technical Field

The invention relates to the field of programmable chip design, in particular to a programmable logic block based on an improved lookup table structure.

Background

A Field Programmable Gate Array (FPGA) is a semiconductor device that implements logic circuits required by a user through reprogramming, and is one type of Programmable Logic Device (PLD). Flash memory, antifuse and static memory (SRAM) are the most commonly used programmable technologies for modern FPGAs, with SRAM-based FPGA products up to 90% or more, becoming the most used programmable technology in current FPGA designs.

The FPGA mainly comprises three major elements of a programmable logic block, programmable interconnection resources, a programmable input/output module, a programmable IP module such as a DSP and a BRAM embedded for improving operation, and a PLL or DLL for generating a clock. The programmable logic blocks (Configurable Logic Block, CLBs) are the basis and core of the FPGA. From the development history, the CLB structure mode sequentially shows a plurality of forms based on NAND gates, multiplexers, lookup tables and the like. The most popular current commercial FPGAs are CLBs based on a look-up table structure whose basic structure is a plurality of basic logic units (BLE).

As shown in fig. 1, BLE is composed of a look-up table (LUT), a register, and a number of multiplexers. The lookup table is responsible for realizing a multi-input Boolean function, and the combination logic is realized; the register is responsible for registering the output of the combinational logic, thereby implementing sequential logic; the multiplexer is responsible for selecting the signal to determine whether the current output is a combined output or a registered output.

As shown in FIG. 2, the basic structure of a 4-input lookup table (4-LUT) comprises four-bit data terminals A <1> -A <4> and 16-bit SRAM, and can realize any 4-input combinational logic function, and the corresponding 6-LUT can realize any 6-input combinational logic function.

Look-up tables in commercial FPGAs fall into two categories: a fixed input number of look-up tables and an adaptive look-up table (ALM).

As shown in FIG. 3, the CLBs in the Xilinx FPGA adopt LUTs with fixed input number, the input number of the LUTs in the mainstream products is 6, each CLB comprises 8 6-LUTs, and the CLBs can be combined into two slices as required. The academic research shows that the 4-6 input LUT has better balance in area and speed, the 6-LUT structure of Xilinx has no sharing of the LUT input end, can realize more independent functions, has stronger performance, but causes excessive number of input ports, and has larger signal depth and increased delay. Since the logic of the tool map to a 6-LUT is only 45%, there is a significant waste of resources in implementing a less input function, with an increase in latency.

As shown in fig. 4, the Altera FPGA employs an adaptive look-up table structure (Adaptive Logic Module, ALM), each LAB consisting of 10 BLE. Each BLE consists of an ALM that can implement the part 8 input logic function and is configured as a LUT structure of various combinations. Although the 8-input ALM has a smaller number of inputs, the biggest problem is that there are more shared inputs, so that more common inputs will be needed when implementing different functions, and the constraint conditions will become very severe. At least three common inputs are required to configure an 8-LUT as 2 6-LUTs. The structure well avoids the waste of resources when fewer input functions are realized, but when a plurality of functions are realized, various constraint conditions such as a common input end is needed among different functions exist, the utilization rate of the resources is improved, the waste is avoided, but the packaging algorithm has higher requirements, and various ALM working modes can be fully configured.

Disclosure of Invention

In order to solve the defects existing in the prior art, the invention aims to provide a programmable logic block based on an improved lookup table structure.

In order to achieve the purpose of the invention, the technical scheme adopted by the invention is as follows:

a programmable logic block based on an improved lookup table structure, wherein each basic logic unit of the programmable logic block comprises two PLML which are identical and independent from each other, and has independent input and output, a carry chain structure and a shift register chain structure;

each PLML comprises an LUT module, a logic operation module, a trigger module, a multiplexer module and a shift register module; the multiplexer module comprises 9 2:1 MUXs and 11 one-to-one MUXs;

the LUT module comprises 1 improved five-input lookup table (improved 5-LUT), 1 improved six-input lookup table (improved 6-LUT) and 2 four-input lookup table (improved 4-LUT) which are independent from each other, and each LUT comprises two paths of output;

the logic operation module comprises 4 independent 2-input adders/subtractors Adder 1-4, each Adder/subtracter is provided with 1-path carry input end, 2-path Adder/subtracter input end, 1-path Adder/subtracter operation and output end and 1-path carry output end;

the input end of the 2-path adder is from 2 LUTs, the output ports of the 4-path adder are SUM 1-4 and CY 1-4 respectively, and SUM and CY of each path of adder are simultaneously output through two different registers;

the 4 adders/subtractors are cascaded into a multi-bit adder, the cascade input signal is carry_in or 0/1, and the cascade output signal is carry_out;

the trigger module comprises 4 triggers and comprises an input end D, an output end Q, a clock control end CLK, an enable end EN, a set reset end SR and an initialization signal end INIT, wherein the input end D is the output of the LUT, the adder operation and output end, a carry output end and the output end of the previous-stage trigger, and the trigger multiplexing mode is realized through the gating of a multiplexer;

the basic logic unit is provided with 2 mutually independent shift register chains, each PLML is provided with one shift register chain, and the highest 4-bit shift register can be realized;

each PLML fully invokes the LUT, the adder and the MUX of the whole PLML through the combination of the same or different resources, thereby realizing more complex LUT functions, sequential logic functions, logic operation functions, multiplexer functions and shift register functions.

Further, the improved 4-LUT comprises a configuration memory, 4 4:1 MUXs, 5 2:1 MUXs, forming 2-way outputs; the output of the first 4:1MUX is used as 2-way input of the same 2:1MUX, the output of the third 4:1MUX is used as 2-way input of the other 2:1MUX, and one-way output signal is obtained through the 2:1MUX; the outputs of the two 2:1 MUXs enter the 2-way input of the same 2:1MUX again, and the other way output signal is obtained by gating; and through multiplexing the address line of the last two-stage LUT, two independent LUTs can be configured;

the improved 5-LUT comprises a configuration memory, 4 8:1 MUXs and 5 2:1 MUXs, and forms 2-path output; the output of the first 8:1MUX is used as 2-way input of the same 2:1MUX, the output of the third 8:1MUX is used as 2-way input of the other 2:1MUX, and one-way output signal is obtained through the 2:1MUX; the outputs of the two 2:1 MUXs enter the 2-way input of the same 2:1MUX again, and the other way output signal is obtained by gating; and through multiplexing the address line of the last two-stage LUT, two independent LUTs can be configured;

the improved 6-LUT comprises a configuration memory, 4 16:1 MUXs and 5 2:1 MUXs, and forms 2-path output; the output of the first 16:1MUX is used as 2-way input of the same 2:1MUX, the output of the third 16:1MUX is used as 2-way input of the other 2:1MUX, and one-way output signal is obtained through the 2:1MUX; the outputs of the two 2:1 MUXs enter the 2-way input of the same 2:1MUX again, and the other way output signal is obtained by gating; and by multiplexing and selecting the address lines of the last two stages of LUTs, two independent LUTs can be configured.

Further, the LUT register output functional modes that can be implemented include:

1 independent 6-LUT,1 independent 5-LUT,2 independent 4-LUT register outputs;

2 independent 5-LUTs with 2 high-order bits of address lines, 2 4-LUTs and 4 3-LUTs;

register outputs of two independent 6-LUTs;

two 6-LUTs with a common input; two independent 5-LUTs, 1 independent 6-LUT register outputs;

two 5-LUTs with common input end, 1 register output of independent 6-LUTs;

a complete 7-LUT register output.

Further, the achievable sequential logic function mode includes:

registering and outputting the combination logic results of the LUT in various combination modes; registering and outputting 4 adder results; the registered outputs of the multiple bit width multiplexers.

Further, the register output of the logic operation function that can be implemented includes:

four independent 2-input adder/subtractor registered outputs; the registered outputs of two multiplexed 2-input adders/subtractors; a cascaded multi-bit adder/subtractor having a registered output;

wherein, the multiplexing mode of the 2-way trigger multiplexes Adder3 and Adder4; in this mode the carry out may bypass directly Adder1 and Adder2 is gated by Adder3.

Further, the available multiplexer functional modes include:

1 independent 4:1MUX,1 independent 3:1MUX,2 independent 2:1MUX register outputs;

2 independent 4:1 muxes, 1 independent 3:1 muxes;

the registered outputs of 2 independent 4:1 MUXs;

the registered outputs of 1 8:1MUX.

Further, the LUT configures the mode and the corresponding output port name:

a first LUT4, the input of which comprises A1/A2/A3/A4, and the output of which comprises LUT4OUT1 and LUT3OUT1; a second LUT4, the input of which comprises B1/B2/B3/B4, and the output of which comprises LUT4OUT2 and LUT3OUT2; LUT5, the input of which comprises C1/C2/C3/C4/C55, and the output of which comprises LUT5OUT1 and LUT4OUT3; LUT6, input comprising D1/D2/D3/D4/D5/D6, output comprising LUT6OUT1 and LUT5OUT2; MUX1, the input of which comprises C5 and L7in, and the output of which is connected to the selection end of L5 MUX; MUX2, the input of which comprises D6 and L7in, and the output of which is connected to the selection terminal of L6 MUX; MUX3, its input includes D6 and L7in, the output connects to the selective end of L7 MUX; the first input end of the L5MUX is connected with the O4 output of the first LUT4, the second input end of the L5MUX is connected with the O4 output of the second LUT4, and the output end of the L5MUX is connected with the LUT5OUT3; the first input end of the L6MUX is connected with the O5 output of the LUT5, the second input end of the L6MUX is connected with the output of the L5MUX, and the output end of the L6MUX is connected with the LUT6OUT2; and the first input end of the L7MUX is connected with the output of the LUT6, the second input end of the L7MUX is connected with the output of the L6MUX, and the output end of the L7MUX is connected with the LUT7OUT.

Further, the L5MUX adopts a C5 or L7in signal as a selection end to combine two 4-LUTs and concatenate the two 4-LUTs into 1 5-LUT;

the L6MUX combines two 4-LUTs and 1 5-LUT to form 1 independent 6-LUT by adopting a D6 or L7in signal as a selection end;

the L6MUX combines two 4-LUTs and 1 5-LUT to form 2 5-LUTs with a common input end by using a D6 or L7in signal as a selection end;

the L7MUX combines two 4-LUTs and 1 5-LUT with the L7in signal as a selection end, and the 1 6-LUT is cascaded into 2 6-LUTs with a shared input end;

the L7MUX combines two 4-LUTs and 1 5-LUT with the D6 or L7in signal as a selection end, and the 1 6-LUT is cascaded into 1 independent 7-LUT;

the 4/5/6-LUT is configured into an independent mode, so that the high 2 bits of the 4-LUT, the 5-LUT and the 6-LUT are independent, and 2 5-LUT,2 4-LUT and 4 3-LUT with partial independent functions are realized.

Further, the PLML structure can implement other smaller input combinational logic function combinations and their corresponding registered outputs.

Compared with the prior art, the structure provided by the invention has the advantages that compared with the traditional CLB structure, the lookup table structure with various inputs can be mapped onto the corresponding LUT according to the function requirement, so that the resource waste is avoided. Compared with the self-adaptive lookup table, the method can realize more independent function functions, is simpler to configure, and has no various limiting conditions when sharing port configuration.

Drawings

FIG. 1 is a schematic diagram of a basic logic cell structure in the prior art;

FIG. 2 is a schematic diagram of the internal structure of a prior art 4-LUT;

FIG. 3 is a schematic diagram of the composition of a Xilinx CLB in the prior art;

FIG. 4 is a schematic diagram of the composition of Altera ALM in the prior art;

FIG. 5 is a block diagram of a programmable logic block based on an improved lookup table structure in accordance with the present invention;

FIG. 6 is a schematic diagram of the internal structure of PLML according to the present invention;

FIG. 7 is a schematic diagram of the overall structure of the LUT of the invention;

FIG. 8 is a schematic diagram of the overall structure of the 4/5/6-LUT of the present invention, a is the overall structure of the 4/5/6-LUT, b is the normal mode of the 4/5/6-LUT, and c is the independent mode of the 4/5/6-LUT;

FIG. 9 is a diagram of various output modes and ports of the LUT of the invention;

FIG. 10 is a schematic diagram of four independent LUTs in LUT module mode 1 of the invention;

FIG. 11 is a schematic diagram of the improved independent mode of the 4/5/6-LUT of the invention with the upper 2 bits of the address line independent in LUT module mode 2;

FIG. 12 is a schematic diagram of 2 independent 6-LUTs in LUT module mode 3 of the invention;

FIG. 13 is a diagram of a second 6-LUT configuration in LUT module mode 3 of the invention;

FIG. 14 is a schematic diagram of a dual 6-LUT of the invention having 1 common input in LUT module mode 4;

FIG. 15 is a diagram of a second 6-LUT configuration in LUT module mode 4 of the invention;

FIG. 16 is a schematic diagram of 1 6-LUT and 2 independent 5-LUTs in LUT module mode 5 of the invention;

FIG. 17 is a diagram of a second 5-LUT configuration in LUT module mode 5 of the invention;

FIG. 18 is a schematic diagram of 1 6-LUT,1 independent 5-LUT, and 1 5-LUT sharing inputs in LUT module mode 6 of the invention;

FIG. 19 is a diagram of a second 5-LUT configuration in LUT module mode 6 of the invention;

FIG. 20 is a schematic diagram of 1 independent 7-LUT configuration in LUT module mode 7 of the invention;

FIG. 21 is a schematic circuit diagram of an arithmetic logic module of the present invention, a is an adder-module with register output diagram, b is an adder normal mode, c is an adder multiplexing mode;

FIG. 22 is a schematic diagram of a normal mode MUX configuration in a multiple bit wide Multiplexer (MUX) module mode 1 of the present invention;

FIG. 23 is a schematic diagram of 2 4:1 MUXs and 1 3:1 MUXs configuration in multiple bit wide Multiplexer (MUX) module mode 2 according to the present invention;

FIG. 24 is a schematic diagram of two 4:1MUX configurations in multiple bit wide Multiplexer (MUX) module mode 3 according to the present invention;

FIG. 25 is a schematic diagram of an 8:1MUX configuration in multiple bit wide Multiplexer (MUX) module mode 4 according to the present invention;

FIG. 26 is a schematic diagram of a normal mode LUT register output of the present invention;

FIG. 27 is a schematic diagram of LUT register outputs after cascading L5MUX, L6MUX, and L7MUX of the present invention;

fig. 28 is a schematic diagram of an SRL mode configuration of the present invention.

Detailed Description

The technical scheme of the invention is further described below with reference to the accompanying drawings and examples. The following examples are only for more clearly illustrating the technical solutions of the present invention and are not intended to limit the scope of protection of the present application.

As shown in FIG. 5, the programmable Logic block based on the improved lookup table structure of the invention consists of two PLML (Programmable Logic Module-Logic) which are identical, and the two PLML are mutually independent and have independent input and output and carry chain structures and shift register structures.

As shown in fig. 6, each PLML contains resources such as 4 modified dual-output LUTs (2 modified 4-LUTs, 1 modified 5-LUTs, 1 modified 6-LUTs), 4 adders, 4 flip-flops, and a plurality of multiplexers (9 2:1 muxes and 11 one-to-one muxes) with three granularity, so that a combinational logic function, a sequential logic function, and an arithmetic operation function can be realized. Each PLML includes the following resources:

(1) A plurality of input LUTs;

1 complete modified 6 input look-up table 6-LUT and inputs D1, D2, D3, D4, D5, D6; a complete modified 5-input look-up table 5-LUT, and its inputs C1, C2, C3, C4, C5; two complete modified 4-input look-up tables 4-LUTs, the first four-input look-up table inputs being B1, B2, B3, B4; the second four-input lookup table input is A1, A2, A3, A4; input L7in.

The specific structure of the improved dual output LUT is shown in fig. 8.

(2) A trigger;

the trigger input end D and the output end Q, the clock control end CLK, the enable end EN, the set reset end SR and the initialization signal INIT can realize the trigger functions of level triggering and edge triggering and the LATCH function; and the power-on initialization function of the FPGA is realized.

(3) Logic operation;

4 independent 2-input adders/subtractors ader 1-4, each having a 1-way carry input, a 2-Adder input, a 1-way Adder SUM (SUM) output, and a Carry (CY) output. The input end of the 2-path adder is from 2 LUTs, and preprocessing operation on input signals can be realized in the LUTs. The output ports of the 4-path adder are SUM 1-4 and CY 1-4 respectively. SUM and CY of each adder may be output simultaneously through two different registers.

2-way flip-flop multiplexing mode, multiplexing Adder3 and Adder4. The LUT of the whole PLML can be fully invoked in the multiplexing mode, the high input preprocessing capability of the 5-LUT and the 6-LUT can be exerted, and more complex logic operation can be processed. In this mode the carry out may bypass directly Adder1 and Adder2 is gated by Adder3.

The 4 adders are cascaded into a multi-bit adder/subtracter, and can be cascaded with other CLBLL, the cascade input signal is carry_in or 0/1, the cascade output signal is carry_out, and the two cascade adder input signals can also be preprocessed.

(4) A multiple bit wide Multiplexer (MUX);

the pair-way selector types that can be implemented by configuration of the LUT include 4:1MUX, 3:1MUX, 2:1MUX, and 8:1MUX.

(5) Shift Register (SRL);

the 4 register cascade can realize the highest 4bit shift register, each PLML has one and mutually independent, and a CLBLL has 2 shift register chains in total.

Each PLML can realize the functions of the LUT, the adder and the MUX with stronger functions through the combination of the same or different resources, can realize the register output, expands the application range and improves the resource utilization rate. The PLML can perform the following functions:

(1) LUT functionality;

1 independent 6-LUT,1 independent 5-LUT,2 independent 4-LUT; 2 independent 5-LUTs with 2 high-order bits of address lines, 2 4-LUTs and 4 3-LUTs; two 5-LUTs with 1 common input, 1 independent 6-LUT;1 6-LUT,2 independent 5-LUT; two 6-LUTs with common input and 1 2-to-1 multiplexers; two independent 6 LUTs; a complete 7-LUT.

(2) A sequential logic function;

a register output of the combination logic result from the LUT various combination modes; registering and outputting 4 adder results; register outputs of the multiple bit wide MUXs; and the signals such as bypass signals and the like are registered and output.

(3) A logic operation function;

four independent 2-input adders/subtractors; two multiplexed 2-input adders/subtractors; a cascaded multi-bit adder/subtractor.

(4) A multiple bit wide Multiplexer (MUX) function;

1 independent 4:1mux,1 independent 3:1mux,2 independent 2:1mux;2 independent 4:1 muxes, 1 independent 3:1 muxes; 2 independent 4:1 MUXs; 1 8:1MUX.

(5) A Shift Register (SRL) function;

2 independent shift register chains, each of which can realize up to 4bit shift registers SRL.

The detailed functions and expansion analysis of each module are as follows.

LUT module

As shown in FIG. 8, the improved structure of the 4/5/6-LUT in the invention is characterized in that a is the overall structural design of the 4/5/6-LUT, b is the common mode of the 4/5/6-LUT, and c is the independent mode of the 4/5/6-LUT. By multiplexing and selecting the address lines of the last two stages of LUTs, two independent LUTs can be configured, and the independence is improved.

The modified 4-LUT structure includes a configuration memory, 4 4:1 MUXs, 5 2:1 MUXs, forming a 2-way output modified 4-LUT. The output of the first 4:1MUX is used as 2-way input of the same 2:1MUX, the output of the third 4:1MUX is used as 2-way input of the other 2:1MUX, and one-way output signal is obtained through the 2:1MUX; the outputs of the two 2:1 MUXs enter the 2-way input of the same 2:1MUX again, and the other way output signal is obtained by gating.

The modified 5-LUT structure includes a configuration memory, 4 8:1 MUXs, 5 2:1 MUXs, forming a 2-way output modified 5-LUT. The output of the first 8:1MUX is used as 2-way input of the same 2:1MUX, the output of the third 8:1MUX is used as 2-way input of the other 2:1MUX, and one-way output signal is obtained through the 2:1MUX; the outputs of the two 2:1 MUXs enter the 2-way input of the same 2:1MUX again, and the other way output signal is obtained by gating.

The modified 6-LUT structure includes a configuration memory, 4 16:1 MUXs, 5 2:1 MUXs, forming a 2-way output modified 6-LUT. The output of the first 16:1MUX is used as 2-way input of the same 2:1MUX, the output of the third 16:1MUX is used as 2-way input of the other 2:1MUX, and one-way output signal is obtained through the 2:1MUX; the outputs of the two 2:1 MUXs enter the 2-way input of the same 2:1MUX again, and the other way output signal is obtained by gating.

Based on this, a programmable logic block structure as shown in fig. 7 is constructed. As shown in fig. 7, the overall structure of the LUT module when implementing the function is mainly divided into two main categories: the combinational logic output and the register output correspond to the combinational logic output and the timing output, respectively. The register output of the LUT results is detailed in the flip-flop module. The output result of the combination logic is divided into two types, and the LUT result is directly output and several LUTs are combined into a higher input LUT and then output.

As shown in fig. 9, the LUT combinations and corresponding output port names for various configuration modes: a first LUT4, the input of which comprises A1/A2/A3/A4, and the output of which comprises LUT4OUT1 and LUT3OUT1; a second LUT4, the input of which comprises B1/B2/B3/B4, and the output of which comprises LUT4OUT2 and LUT3OUT2; LUT5, the input of which comprises C1/C2/C3/C4/C55, and the output of which comprises LUT5OUT1 and LUT4OUT3; the input of LUT6 comprises D1/D2/D3/D4/D5/D6, and the output comprises LUT6OUT1 and LUT5OUT2; MUX1, the input of which comprises C5 and L7in, and the output of which is connected to the selection end of L5 MUX; MUX2, the input of which comprises D6 and L7in, and the output of which is connected to the selection terminal of L6 MUX; MUX3, its input includes D6 and L7in, the output connects to the selective end of L7 MUX; the first input end of the L5MUX is connected with the O4 output of the first LUT4, the second input end of the L5MUX is connected with the O4 output of the second LUT4, and the output end of the L5MUX is connected with the LUT5OUT3; the first input end of the L6MUX is connected with the O5 output of the LUT5, the second input end of the L6MUX is connected with the output of the L5MUX, and the output end of the L6MUX is connected with the LUT6OUT2; and the first input end of the L7MUX is connected with the output of the LUT6, the second input end of the L7MUX is connected with the output of the L6MUX, and the output end of the L7MUX is connected with the LUT7OUT.

The LUT with 4-7 inputs is realized from a type point of view, and various configuration modes thereof will be analyzed in detail below.

(1) Mode 1, as shown in fig. 10, 4 completely independent LUTs can be directly configured in the normal mode of the whole PLML: 1 6-LUT,1 5-LUT,2 4-LUT, which is also the most common mode at mapping time.

(2) Mode 2, as shown in FIG. 11, the 4/5/6-LUT of the whole PLML is configured as an independent mode, and at this time, the 4/5/6-LUT independent structure as shown in FIG. 8c is adopted, so that the high 2 bits of the 4-LUT, the 5-LUT and the 6-LUT are independent, thereby realizing a partially functional independent LUT:2 5-LUTs, 2 4-LUTs, 4 3-LUTs, and up to 8 logic functions can be implemented in this mode.

(3) Mode 3, as shown in fig. 12, the entire PLML may be configured as 2 independent 6-LUTs, with the first 6-LUT directly employing LUT6 in the PLML. As shown in FIG. 13, the second 6-LUT is formed by combining two 4-LUTs and 1 5-LUT, and the control terminal selects L7in signals.

(4) Mode 4, as shown in fig. 14, the whole PLML may be configured as 2 6-LUTs with common inputs, where the first 6-LUT directly uses LUT6 in PLML, and as shown in fig. 15, the second 6-LUT is formed by combining two 4-LUTs and 1 5-LUT, and the final stage control terminal selects D6 signal as the common input signal.

(5) Mode 5, as shown in FIG. 16, the entire PLML can be configured as 1 6-LUT,2 independent 5-LUTs. The 6-LUT and the first 5-LUT directly adopt LUT provided in PLML, as shown in figure 17, the second 5-LUT is formed by combining two 4-LUTs, and the control end of the last stage selects L7in signals.

(6) Mode 6, as shown in FIG. 18, the entire PLML can be configured as 1 6-LUT,1 independent 5-LUT, and 1 5-LUT sharing an input. The 6-LUT and the first 5-LUT directly adopt LUTs provided in PLML, as shown in figure 19, the second 5-LUT is formed by combining two 4-LUTs, and the control terminal of the last stage selects a C5 signal as a common input signal.

(7) Mode 7, as shown in fig. 20, the entire PLML may be configured as 1 LUT capable of implementing all 7 input functions, in which mode the L5MUX select terminal multiplexes the C5 signal and the L6MUX select terminal multiplexes the D6 signal.

(II) logic operation module

As shown in fig. 21 (a), the whole PLML includes 4 independent adders ader 1 to 4, SUM1 to 4 and CY1 to 4 as output ports, and a cascade input signal carry_in and a cascade output signal carry_out, respectively.

In the normal mode, each adder can realize a 2-input 1-bit adder, and SUM and carry output CY can be directly selected and output by D1 from D2-4 and the next stage PLML through CY4_P or registered and output through a trigger. The SUM and CY of each adder are now independent, and can be output simultaneously in a 1bit adder implementing 1 and 2 inputs. The 4 adders can implement the addition and subtraction operations by making a 0/1 selection of the carry input.

In the trigger multiplexing mode, the first input end of the Adder3 is the data preprocessed by the 5-LUT, and the second input end is the data preprocessed by the 1 st 4-LUT; the first input end of the Adder4 is data which is preprocessed by the 6-LUT, and the second input end is data which is preprocessed by the 2 nd 4-LUT. Meanwhile, the O5 output of the 6-LUT may be output from QB and DB ports, and the O4 output of the 5-LUT may be output from QA and DA ports. In multiplexing mode, 4 LUTs with different granularities in the whole PLML can be fully utilized, and the high input preprocessing capability of the 5-LUT and the 6-LUT is exerted for processing more complex and independent logic operation. Meanwhile, the second output end O5 of the 6-LUT and the second output end O4 of the 5-LUT can also realize logic functions, and the highest resource utilization rate is ensured. In this mode, input carry_in can bypass Adder1 and Adder2 directly to send data to Adder3. Multiplexing Adder3 and Adder4 can reduce output delay to some extent.

(III) multiple bit-wide Multiplexer (MUX)

(1) Mode 1, as shown in FIG. 22, four separate LUTs of the entire PLML may implement 1 4:1MUX,1 3:1MUX, and 2:1MUX, while either direct output or register output may be selected.

(2) In mode 2, as shown in FIG. 23, the 2:1MUX implemented by two 4-LUTs can be implemented by L5MUX to 4:1MUX, wherein L7in is selected for the L5MUX control terminal, and the input signals of A3 and B3 are fixed to 0 or 1.

(3) In mode 3, as shown in FIG. 24, two 4-LUTs are combined with a 5-LUT to form a 4:1MUX, at this time, the control end of the L5MUX is C5, the control end of the L6MUX is L7in, at this time, A1-A4 and B1-B460 of the 4-LUR are configured as the same data, and the input signals of A3, B3 and C3 are fixed to be 0 or 1.

(4) Mode 4, as shown in FIG. 25, selecting L7MUX to select two 4:1MUX is cascaded into 1 8:1MUX, at the moment, the control end of the L5MUX is selected to be C5 or L7in, the control end of the L6MUX is selected to be D6, the control end of the L7MUX is selected to be L7in, at the moment, the A1-A4 and the B1-B4 of the 4-LUT are configured to be the same data, and the input signals of A3, B3 and C3 are fixed to be 0 or 1.

(IV) trigger

The trigger can realize the functions of level triggering, edge triggering and LATCH, and simultaneously can realize the function of initializing the FPGA, and the main ports are a trigger input port D, an output end Q, a clock control end CLK, an enable end EN, a setting reset end SR and an initialization signal INIT; the register output of signals of the combined circuit modules such as LUTs, MUXs, adders and the like can be realized. The configuration method of the register outputs of the adder and the multi-selector may refer to the correspondence of the second portion and the third portion. As shown in fig. 26, the register output of the LUT in the normal mode is enumerated, and as shown in fig. 27, the register output mode when the LUT of higher input is cascade-connected with L5MUX, L6MUX and L7MUX is enumerated.

Fifth Shift Register (SRL) mode

In the invention, each output of 4 flip-flops can be gated by the D input end of the flip-flop with one lower bit, and the four flip-flops are sequentially cascaded as shown in figure 28, and the connection mode is RCASIN- > QD- > QC- > QB- > QA- > RCASOUT, so that a 4-bit shift register is formed under the action of a clock.

To further verify the performance of the inventive solution, the solution of the present invention was compared with the areas of the three reference structures as shown in table 1. The invention is advantageous in balancing performance and area (cost), achieving stronger performance with less area.

TABLE 1

Comparing the performance of the reference structure 1 with the scheme of the present invention, as shown in table 2, it can be seen that, compared with the CLBLL structure composed of 8 4-LUTs with smaller area, the area of the scheme is increased, but the LUT can be realized with stronger function, more 6-LUTs and even 7-MUX can be realized, and the scheme is more suitable for the use of modern commercial FPGAs. And a plurality of bit-wide muxes have a better range of use.

TABLE 2

Comparing the performance of the reference structure 2 with the scheme of the present invention, as shown in table 3, it can be known that the CLBLL structure with 8 complete 6-LUTs consumes larger resources and occupies a larger area, but in practical use, the mapping proportion of the 6-LUTs is less than 50%, so that the area overhead is geometrically multiplied compared with that of the CLBLL structure mapped to 4-LUTs and 5-LUTs, and meanwhile, the logic depth is larger, the time delay is increased, the working frequency of the CLBLL structure is reduced, compared with the LUT structure of the present invention, the CLBLL structure is more flexible, multiple input logic functions can be realized, and the LUT function module area is saved by nearly 50%.

TABLE 3 Table 3

Comparing the performance of the reference structure 3 with the scheme of the present invention, as shown in table 4, it can be seen that the LAB structure of Altera Stratix can only realize 10 4-LUTs, and cannot realize higher input LUTs, and in the present invention, the flexibility of the structure is greatly increased, the group can realize 2 complete 7-input LUTs, and has two independent carry chains, so that more arithmetic operations can be performed simultaneously in one programmable logic block.

TABLE 4 Table 4

While the applicant has described and illustrated the embodiments of the present invention in detail with reference to the drawings, it should be understood by those skilled in the art that the above embodiments are only preferred embodiments of the present invention, and the detailed description is only for the purpose of helping the reader to better understand the spirit of the present invention, and not to limit the scope of the present invention, but any improvements or modifications based on the spirit of the present invention should fall within the scope of the present invention.

Claims

1. The programmable logic block based on the improved lookup table structure is characterized in that each basic logic unit of the programmable logic block comprises two PLML which are completely identical and mutually independent, and has independent input and output, a carry chain structure and a shift register chain structure;

the LUT module comprises 1 improved five-input lookup table, namely an improved 5-LUT,1 improved six-input lookup table, namely an improved 6-LUT, and 2 improved four-input lookup tables, namely an improved 4-LUT, which are independent of each other, wherein each LUT comprises two paths of outputs;

the basic logic unit is provided with 2 mutually independent shift register chains, and each PLML is provided with one shift register chain to realize a highest 4-bit shift register;

each PLML invokes the LUT, the adder and the MUX of the whole PLML through the combination of the same or different internal resources to realize the LUT function, the sequential logic function, the logic operation function, the multiplexer function and the shift register function;

the improved 4-LUT comprises a configuration memory, 4 4:1 MUXs and 5 2:1 MUXs, and forms 2 paths of output; the output of the first 4:1MUX is used as 2-way input of the same 2:1MUX, the output of the third 4:1MUX is used as 2-way input of the other 2:1MUX, and one-way output signal is obtained through the 2:1MUX; the outputs of the two 2:1 MUXs enter the 2-way input of the same 2:1MUX again, and the other way output signal is obtained by gating; the address lines of the last two stages of LUTs are multiplexed and selected, so that two independent LUTs are configured;

the improved 5-LUT comprises a configuration memory, 4 8:1 MUXs and 5 2:1 MUXs, and forms 2-path output; the output of the first 8:1MUX is used as 2-way input of the same 2:1MUX, the output of the third 8:1MUX is used as 2-way input of the other 2:1MUX, and one-way output signal is obtained through the 2:1MUX; the outputs of the two 2:1 MUXs enter the 2-way input of the same 2:1MUX again, and the other way output signal is obtained by gating; the address lines of the last two stages of LUTs are multiplexed and selected, so that two independent LUTs are configured;

the improved 6-LUT comprises a configuration memory, 4 16:1 MUXs and 5 2:1 MUXs, and forms 2-path output; the output of the first 16:1MUX is used as 2-way input of the same 2:1MUX, the output of the third 16:1MUX is used as 2-way input of the other 2:1MUX, and one-way output signal is obtained through the 2:1MUX; the outputs of the two 2:1 MUXs enter the 2-way input of the same 2:1MUX again, and the other way output signal is obtained by gating; and two independent LUTs are configured by multiplexing and selecting address lines of the last two stages of LUTs.

2. The programmable logic block based on an improved look-up table structure according to claim 1, wherein the LUT register output functional mode comprises:

1 independent 6-LUT,1 independent 5-LUT,2 independent 4-LUT register outputs;

register outputs of two independent 6-LUTs;

two 5-LUTs with common input end, 1 register output of independent 6-LUTs;

a complete 7-LUT register output.

3. The programmable logic block based on an improved look-up table structure of claim 1, wherein the sequential logic functional mode comprises:

4. The programmable logic block based on an improved look-up table structure according to claim 1, wherein the registered output of the logic operation function comprises:

wherein, the multiplexing mode of the 2-way trigger multiplexes Adder3 and Adder4; in this mode the carry out bypasses directly Adder1 and Adder2 being gated by Adder3.

5. The programmable logic block based on an improved look-up table structure of claim 1, wherein the multiplexer function mode comprises:

2 independent 4:1 muxes, 1 independent 3:1 muxes;

the registered outputs of 2 independent 4:1 MUXs;

the registered outputs of 1 8:1MUX.

6. The programmable logic block based on an improved look-up table structure according to claim 1, wherein the LUT configures a pattern and corresponding output port name:

7. The programmable logic block based on an improved look-up table structure of claim 6,

the L5MUX adopts a C5 or L7in signal as a selection end to combine two 4-LUTs and concatenate the two 4-LUTs into 1 5-LUTs;

8. The programmable logic block based on an improved look-up table structure according to claim 1, wherein the PLML structure is used to implement other smaller input combinational logic function combinations and their corresponding registered outputs.