CN106649905A - Technology mapping method by utilizing carry chain - Google Patents
Technology mapping method by utilizing carry chain Download PDFInfo
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- CN106649905A CN106649905A CN201510738809.9A CN201510738809A CN106649905A CN 106649905 A CN106649905 A CN 106649905A CN 201510738809 A CN201510738809 A CN 201510738809A CN 106649905 A CN106649905 A CN 106649905A
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention relates to a technology mapping method by utilizing a carry chain. According to the method, an FPGA comprises multiple logical units, and one logical unit comprises multiple logical pieces; the output end of a multi-input lookup table in a logical piece LP on a logical element LE of the FPGA is connected to the input end of a second addend of a first summator; one bit signal is input to the carry input end of the first summator and one bit signal is input to the input end of a first addend; a carry output signal is output through the carry output end of the first addend. According to the technology mapping method by utilizing the carry chain, by utilizing the technology mapping method which combines the lookup table and the addend, technology mapping with a long width and/or logic is achieved, chip logical resources can be saved, and time delaying of achieving the logic can be sharply reduced at the same time.
Description
Technical field
The present invention relates to the IC design technical field in microelectronic, particularly a kind of technique of utilization carry chain
Mapping method.
Background technology
FPGA is a kind of logical device with abundant hardware resource, powerful parallel processing capability and flexible reconfigurable ability.
These features cause FPGA to obtain increasing extensively application in many fields such as data processing, communication, network.
At present, at the scene in programmable gate array (Field Programmable Gate Array, FPGA) application, it is desirable to
Integrated circuit has programmable or configurable interference networks, and gate is connected to each other by configurable interference networks.Make
Extensively it has been applied in a large amount of microelectronic devices for the FPGA that core in individual chips or system is worked.Broad sense
FPGA gate definition, singly do not refer to simple NAND gate, also refer to the combinational logic with configurable functionality and sequential
The logical block (LE, Logic Element) of logic or the logical block for being interconnected and being constituted by multiple logical blocks.
The process mapping method of prior art can by with or logical mappings on look-up table, as shown in figure 1, Fig. 1 is for existing
In technology by with or logical mappings to look-up table on schematic diagram.In figure a1, a2, a3, a4, a5, a6 with or patrol
Volume, they are connected respectively with the input of the look-up table (Lookup table-LUT) of 6 inputs, and export and or logic
As a result X.But for longer width with or logic, the implementation method of this utilization look-up table is relative to take it is more
The longer time delay of logical resource and needs.
The content of the invention
The purpose of the present invention is the defect for prior art, there is provided a kind of process mapping method of utilization carry chain.This
Invention by using look-up table process mapping method in combination with adder realize to longer width with or the technique of logic reflect
Penetrate, chip logic resource can be saved, while the time delay for realizing the logic can be greatly reduced.
The present invention provides a kind of process mapping method of utilization carry chain, and methods described includes：FPGA includes multiple logic lists
Unit a, logical block includes multiple logic chips；Will be many in a logic chip LP in logical block LE of FPGA
The output end of input look-up table is connected to the second addend input of first adder；The carry of the first adder is input into
End and the first addend input are each input into 1 bit signal；The first adder carry output output carry output letter
Number.
Preferably, methods described also includes：The carry output of the first adder is connected into the carry of second adder
Input；Second addend input of the second adder is connected to the output end of the look-up table of another multi input；And
First addend input of the second adder is input into 1 bit signal；The carry output of the second adder is defeated
Go out carry output signals.
Preferably, one logical block LE includes multiple logic chip LP.
Preferably, one logic chip LP includes the look-up table of multiple multi inputs, multiple adders；Wherein, addition
The carry output of device is connected with the carry input of another adder and constitutes the carry chain of 2, multiple adders phase successively
Even constitute the carry chain of multidigit.
Preferably, the look-up table and adder combination in one or more described logic chip LP realize long width with or patrol
Volume.
Preferably, 1 bit signal is 0 or 1.
Preferably, the FPGA is specially the device of CME-C1 series.
Preferably, the look-up table of the multi input is 6 inputs.
Preferably, the second adder with the look-up table of another multi input with a logic chip；The logic chip
The logic chip being located from the first adder can be same logic chip, or different logic chips.
By the present invention in that with look-up table process mapping method in combination with adder realize to longer width with or logic work
Skill maps, and chip logic resource can be saved, while the time delay for realizing the logic can be greatly reduced.
Description of the drawings
In order to be illustrated more clearly that the technical scheme of the embodiment of the present invention, embodiment will be described below needed for be used it is attached
Figure is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for ability
For the those of ordinary skill of domain, on the premise of not paying creative work, can be attached to obtain others according to these accompanying drawings
Figure.
Fig. 1 be prior art in by with or logical mappings to look-up table on schematic diagram；
Fig. 2 is look-up table provided in an embodiment of the present invention and adder combination schematic diagram；
Fig. 3 is PLBR schematic diagrames in CME-C1 frameworks provided in an embodiment of the present invention；
Fig. 4 is a kind of basic logic unit schematic diagram provided in an embodiment of the present invention；
Fig. 5 is the schematic diagram of 48 logical ANDs in prior art；
Fig. 5-1 is using the schematic diagram of 48 logical ANDs of look-up tables'implementation in existing Technology Mapping technology；
Fig. 5-2 is the schematic diagram that utilization look-up table provided in an embodiment of the present invention and adder realize 48 logical ANDs；
Fig. 6 be prior art in 48 logics or schematic diagram；
Fig. 6-1 be existing Technology Mapping technology in using 48 logics of look-up tables'implementation or schematic diagram；
Fig. 6-2 be utilization look-up table provided in an embodiment of the present invention and adder realize 48 logics or schematic diagram.
Specific embodiment
To make purpose, technical scheme and the advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
Accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
The a part of embodiment of the present invention, rather than the embodiment of whole.
The invention provides a kind of process mapping method of utilization carry chain.By the present invention in that with look-up table and adder phase
With reference to process mapping method realize to longer width with or logic Technology Mapping, chip logic resource can be saved, while
The time delay for realizing the logic can be greatly reduced.
Method in the following embodiments of the present invention is realized based on CME-C1 Series FPGAs device, to be better understood from this
The technical scheme that inventive embodiments are provided, is briefly described first to the framework of FPGA device.
It is divided into programmed logical module PLB (Programmable Logic Block) in CME-C1 model fpga chips
With programmed logical module PLBR with local storage (Programmable Logic BlockLocal memory lram),
In the chips the ratio shared by PLBR and PLB is 1:1, but the area shared by PLBR is big.
Fig. 3 is PLBR schematic diagrames in CME-C1 frameworks provided in an embodiment of the present invention.As illustrated, a band is locally deposited
In the programmable logic block PLBR of reservoir, including 86 input look-up table be respectively LUT0, LUT1, LUT2, LUT3,
LUT4、LUT5、LUT6、LUT7.Wherein have 4 to be the look-up table with local storage, respectively LUT0, LUT2,
LUT4、LUT6；Also include 8 adders, 16 registers, register be respectively Q0, Q1, Q2, Q3, Q4,
Q5、Q6、Q7、Q8、Q9、Q10、Q11、Q12、Q13、Q14、Q15.As illustrated, PLBR also includes looking into
The interconnection resources looked between the elementary cells such as table LUT, register, adder.
Specifically, as scheme LUT0, LUT1 line relation shown in, look-up table LUT inside include two 5 input look into
Look for table LUT5；There are tri- output ends of x, xy, shiftout, wherein xy output ends are the output end of LUT, and x is 5 inputs
Look-up table output end.When LUT modules are used as a bit register, using shiftout output ends.LUT0's
Xy output ports line is connected on the second acceleration input b0 of adder by multiplexer mux_b0；Adder
Carry output output carry signal C1.The xy output ports line of LUT1 is connected to by multiplexer mux_b1 and is added
On second acceleration input b1 of musical instruments used in a Buddhist or Taoist mass, the carry input signal of the adder is C1, carry output output carry signal
C2。
The technical scheme that for a better understanding of the present invention embodiment is provided, Fig. 4 is patrolled substantially for one kind provided in an embodiment of the present invention
Collect cell schematics.As shown in figure 4, field programmable gate array (the Field Programmable of CME-C1 models
Gate Array, FPGA) framework in, the schematic diagram of a basic logic unit.One basic logic unit (Logic Element,
LE) 4 basic programmable logic chips (LP, Logic Parcel) are included, that is, LP0, LP1, LP2, LP3.
One basic logic chip include the look-up table (Lookup table-LUT) of 26 inputs, 2 adders (Adder-ADD),
4 registers (Register-Reg).
Fig. 2 is look-up table provided in an embodiment of the present invention and adder combination schematic diagram.As shown in Fig. 2 look-up table LUT
6 inputs, respectively be input into a1, a2, a3, a4, a5, a6；The output end of look-up table is defeated with the second addend of adder
Enter to hold a ports to be connected.
Specifically, the first addend input b ports are each input into 1 bit signal with carry input Ci.The 1 bit letter
Number be 0 or 1.And output carry output signal Co and sum sum.It should be noted that in following embodiments of the invention
Sum ports are not used, therefore, and be not drawn into.
The present invention provides a kind of process mapping method of utilization carry chain, and methods described includes：By a logic list of FPGA
The first output end of multi input look-up table is connected to the second addend input of first adder in a logic chip LP on first LE
End；The carry input of the first adder and the first addend input are each input into 1 bit signal；Described first
Adder carry output output carry output signal.
Specifically, said method also includes：The carry output of the first adder is connected into the carry of second adder
Input；Second addend input of the second adder is connected to the first output end of the look-up table of another multi input；
And the first addend input of the second adder is input into 1 bit signal；The carry output of the second adder
Output carry output signal.
By the present invention in that with look-up table process mapping method in combination with adder realize to longer width with or logic work
Skill maps, and chip logic resource can be saved, while the time delay for realizing the logic can be greatly reduced.
The embodiment of the present invention illustrates the technique that the present invention is combined using look-up table with adder and reflects with the look-up table LUT of 6 inputs
Thought is penetrated, but is not limited look-up table one and is set to 6 inputs.LUT can for 4 input look-up tables, 5 input look-up tables, 7
Input look-up table etc..
Fig. 5 is the schematic diagram of 48 logical ANDs in prior art.As illustrated, a [47:0] it is input to the input of logical AND
Mouthful, output result O.O=a [0] ＆＆a [1]s ＆＆ ... ＆＆a [47]；Do for 48 1 with logic budget, O=1.
Fig. 5-1 is using the schematic diagram of 48 logical ANDs of look-up tables'implementation in existing Technology Mapping technology.As illustrated,
The logic and operation of 48 1 is realized using the look-up table LUT of 6 inputs.
Specifically, it is divided into 8 groups by 48, a [5:0]、a[11:6]、a[17:12]、a[23:18]、a[29:24]、a[35:30]、a[41:36]、
a[47:42], it is separately input to the input of 8 LUT；Then the input of the output end per 4 LUT and LUT
Be connected, 2 LUT are at this moment needed again (such as AND4 in figure)；Define 2 logical layers (Logic Level).This 2
The output end of the LUT of individual logical layer forms the 3rd logical layer again in the input of a LUT (AND2 in such as figure)
Logic Level.The output end of AND2 exports result O of the logical AND of 48 1.
The now realization of 48 logical ANDs contains 11 6 input look-up tables, and logical layer Logic Level are 3 grades.Due to
There are 8 LUT in one logical block LE, therefore realize that the logical AND of 48 needs 2 LE.Company between 2 LE
Line can all use the common coiling resource on XBAR, also there is certain time delay.
Fig. 5-2 is the schematic diagram that utilization look-up table provided in an embodiment of the present invention and adder realize 48 logical ANDs.
In fpga chip, adder is connected and constitutes carry chain Carry chain.As illustrated, the computing of 48 logical ANDs equally divides
For 8 groups, respectively a [5:0]、a[11:6]、a[17:12]、a[23:18]、a[29:24]、a[35:30]、a[41:36]、a[47:42], divide
Not Lian Jie a LUT input, the output end of each LUT is connected respectively with the second addend input of adder,
With a [47:42] carry input of connected adder 1 is input into 1 bit signal 0, the input input 1 of its first addend
Individual bit signal 1, and output carry output signal is used as the input signal of next adder 2.
Adder 2, adder 3, adder 4, adder 5, adder 6, adder 7 the first addend input it is each
From the 0 of 1 bit of input, the carry output signals of adder 2 as adder 3 carry input signal, adder 3
Carry output signals as adder 4 carry input signal, the carry output signals of adder 4 are used as adder 5
Carry input signal, the carry output signals of adder 5 as adder 6 carry input signal, the carry of adder 6
Output signal is used as the carry input signal of adder 7, and the carry output signals of adder 7 are defeated as the carry of adder 8
Enter signal.Final output carry output result O by adder 8.
The logic and operation of a+8 ' b00000001, it is all 1 that carry condition is all positions of a；Any one position of a is 0,
Cannot carry.Do logic and operation for 48 1, meet carry condition, output result O=1.
The embodiment of the present invention realizes the logic and operation of 48 1, it is only necessary to 8 LUT, carry chain (the 8-bit carry of 8
Chain), not only save look-up table resource, at the same look-up table, adder these logical resources all can layout LE's
Inside, the line inside logical resource can also be realized all by LE interconnectors, it is not necessary to take XBAR around
Line resource；Decrease time delay simultaneously.
It should be noted that the implementation of logical AND provided in an embodiment of the present invention is as a example by 48, but the present invention is simultaneously
The digit of logical AND is not limited.
Fig. 6 be prior art in 48 logics or schematic diagram.a[47:0] be input to logic or input, do 48
Logic or computing, output result O.O=a [1] | | a [2] | | ... | | a [47].At least one is 1, O=1 in a.
Fig. 6-1 be existing Technology Mapping technology in using 48 logics of look-up tables'implementation or schematic diagram.As in Figure 6-1,
By 48 logics or computing, it is divided into 8 groups, respectively a [5:0]、a[11:6]、a[17:12]、a[23:18]、a[29:24]、a[35:30]、
a[41:36]、a[47:42].Per group of input for connecting a LUT respectively, now needs 8 LUT.4 LUT's is defeated
Go out end to be connected with the input of LUT (such as OR4 in figure), now need 2 LUT (such as OR4 in figure), be exactly 2
Individual logical layer.The output end of the two LUT connects the input of a LUT (such as OR2 in figure), forms the 3rd logic
Layer.LUT (such as OR2 in figure) exports the result of logical AND.
Now 48 logics or realization contains 11 6 input look-up tables, and logical layer Logic Level are 3 grades.Due to one
There are 8 LUT in individual logical block LE, therefore realize that the logical AND of 48 needs 2 LE.Line between 2 LE
The common coiling resource on XBAR will be used, also there is certain time delay.
Now optimum to realize containing 11 6 input look-up tables, logical layer Logic Level are 3 grades.Due to a logic
There are 8 LUT in unit LE, therefore realize the logic of 48 or need 2 LE.Line between 2 LE all can make
With the common coiling resource on XBAR, also there is certain time delay.
Fig. 6-2 be utilization look-up table provided in an embodiment of the present invention and adder realize 48 logics or schematic diagram.As schemed
It is shown, 48 logics or computing be equally divided into 8 groups, respectively a [5:0]、a[11:6]、a[17:12]、a[23:18]、a[29:24]、
a[35:30]、a[41:36]、a[47:42], connect the input of a LUT respectively, the output end of each LUT respectively with plus
Second addend input of musical instruments used in a Buddhist or Taoist mass is connected, with a [47:42] carry input of connected adder 1 is input into 1 bit signal 0,
The input of its first addend is input into 1 bit signal 1, and output carry output signal is used as the defeated of next adder 2
Enter signal.
Adder 2, adder 3, adder 4, adder 5, adder 6, adder 7 the first addend input it is each
From the 1 of 1 bit of input, the carry output signals of adder 2 as adder 3 carry input signal, adder 3
Carry output signals as adder 4 carry input signal, the carry output signals of adder 4 are used as adder 5
Carry input signal, the carry output signals of adder 5 as adder 6 carry input signal, the carry of adder 6
Output signal is used as the carry input signal of adder 7, and the carry output signals of adder 7 are defeated as the carry of adder 8
Enter signal.Final output carry output result O by adder 8.
The logic of a+8 ' b11111111 or computing, it is 1 that carry condition is at least one of a；All positions of a are 0, just
It is unable to carry.48 logics or computing, at least one is 1 in a, then meet carry condition, output result O=1.
The embodiment of the present invention realizes the logic of 48 or computing, it is only necessary to 8 LUT, carry chain (the 8-bit carry of 8
Chain), not only save look-up table resource, at the same look-up table, adder these logical resources all can layout LE's
Inside, the line inside logical resource can also be realized all by LE interconnectors, it is not necessary to take XBAR around
Line resource；Decrease time delay simultaneously.
It should be noted that logic provided in an embodiment of the present invention or implementation as a example by 48, but the present invention is simultaneously
Do not limit logic or digit.
By the present invention in that with look-up table process mapping method in combination with adder realize to longer width with or logic work
Skill maps, and chip logic resource can be saved, while the time delay for realizing the logic can be greatly reduced.
Professional should further appreciate that, with reference to the list of each example of the embodiments described herein description
Unit and algorithm steps, can with electronic hardware, computer software or the two be implemented in combination in, it is hard in order to clearly demonstrate
The interchangeability of part and software, according to function has generally described the composition and step of each example in the above description.
These functions are performed with hardware or software mode actually, depending on the application-specific and design constraint of technical scheme.
Professional and technical personnel can use different methods to realize described function to each specific application, but this realization
It is not considered that beyond the scope of this invention.
With reference to the method for the embodiments described herein description or the step of algorithm can with hardware, computing device it is soft
Part module, or the combination of the two is implementing.Software module can be placed in random access memory (RAM), internal memory, read-only deposit
Reservoir (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM,
Or in technical field in known any other form of storage medium.
Above-described specific embodiment, has been carried out further in detail to the purpose of the present invention, technical scheme and beneficial effect
Describe in detail it is bright, should be understood that the foregoing is only the present invention specific embodiment, be not intended to limit the present invention
Protection domain, all any modification, equivalent substitution and improvements within the spirit and principles in the present invention, done etc. all should
It is included within protection scope of the present invention.
Claims (8)
1. a kind of process mapping method of utilization carry chain, it is characterised in that methods described includes：
FPGA includes multiple logical blocks, and a logical block includes multiple logic chips；By a logical block of FPGA
The output end of multi input look-up table is connected to the second addend input of first adder in a logic chip LP on LE；
The carry input of the first adder and the first addend input are each input into 1 bit signal；
The first adder carry output output carry output signal.
2. method according to claim 1, it is characterised in that methods described also includes：
The carry output of the first adder is connected into the carry input of second adder；
Second addend input of the second adder is connected to the output end of the look-up table of another multi input；And by institute
The the first addend input for stating second adder is input into 1 bit signal；
The carry output output carry output signal of the second adder.
3. method according to claim 1, it is characterised in that one logical block LE includes multiple described
Logic chip LP.
4. method according to claim 3, it is characterised in that one logic chip LP includes multiple multi inputs
Look-up table, multiple adders；Wherein, the carry output of adder is connected structure with the carry input of another adder
Into the carry chain of 2, multiple adders are sequentially connected the carry chain for constituting multidigit.
5. method according to claim 4, it is characterised in that the look-up table in one or more described logic chip LP
With adder combination realize long width with or logic.
6. the method according to right will go 1, it is characterised in that 1 bit signal is 0 or 1.
7. method according to claim 1, it is characterised in that the FPGA is specially the device of CME-C1 series.
8. method according to claim 1, it is characterised in that the look-up table of the multi input is 6 inputs.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113705135A (en) * | 2021-07-20 | 2021-11-26 | 深圳市紫光同创电子有限公司 | Circuit structure optimization method and system based on FPGA carry chain |
| CN113971159A (en) * | 2021-10-28 | 2022-01-25 | 山东芯慧微电子科技有限公司 | Programmable logic block based on improved lookup table structure |
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| CN103762974A (en) * | 2014-01-26 | 2014-04-30 | 中国电子科技集团公司第五十八研究所 | Multifunctional and configurable six-input lookup table structure |
| US20150295664A1 (en) * | 2014-04-09 | 2015-10-15 | Panasonic Intellectual Property Management Co., Ltd. | Calibration device and calibration method |
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| CN102375906A (en) * | 2010-08-27 | 2012-03-14 | 雅格罗技（北京）科技有限公司 | Pattern matching based FPGA (field-programmable gate array) logic synthesis method |
| CN103762974A (en) * | 2014-01-26 | 2014-04-30 | 中国电子科技集团公司第五十八研究所 | Multifunctional and configurable six-input lookup table structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113705135A (en) * | 2021-07-20 | 2021-11-26 | 深圳市紫光同创电子有限公司 | Circuit structure optimization method and system based on FPGA carry chain |
| WO2023001192A1 (en) * | 2021-07-20 | 2023-01-26 | 深圳市紫光同创电子有限公司 | Circuit structure optimization method and system based on fpga carry chain |
| CN113705135B (en) * | 2021-07-20 | 2023-11-07 | 深圳市紫光同创电子有限公司 | Circuit structure optimization method and system based on FPGA carry chain |
| CN113971159A (en) * | 2021-10-28 | 2022-01-25 | 山东芯慧微电子科技有限公司 | Programmable logic block based on improved lookup table structure |
| CN113971159B (en) * | 2021-10-28 | 2024-02-20 | 山东芯慧微电子科技有限公司 | Programmable logic block based on improved lookup table structure |
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