CN113971159A

CN113971159A - Programmable logic block based on improved lookup table structure

Info

Publication number: CN113971159A
Application number: CN202111265159.2A
Authority: CN
Inventors: 王彦林; 高丽江; 刘学刚; 秋小强; 贾一平; 杨海钢
Original assignee: Shandong Xinhui Microelectronics Technology Co ltd
Current assignee: Shandong Xinhui Microelectronics Technology Co ltd
Priority date: 2021-10-28
Filing date: 2021-10-28
Publication date: 2022-01-25
Anticipated expiration: 2041-10-28
Also published as: CN113971159B

Abstract

The invention discloses a Programmable Logic block based on an improved lookup table structure, wherein each basic Logic unit of the Programmable Logic block comprises two identical mutually independent PLMLs (Programmable Logic modules-Logic) and has independent input and output, carry chain structures and shift register chain structures; each PLML comprises an improved LUT module, a logic operation module, a trigger module, a multiplexer module and a shift register module; each PLML comprises resources of 4 improved double-output LUTs with three granularities, 4 adders, 4 triggers, a plurality of multiplexers and the like; each PLML can realize the LUT function, the sequential logic function, the logic operation function, the multiplexer function and the shift register function with stronger function through the combination of the same or different internal resources, and can realize the register output. The invention has a plurality of input lookup table structures, can be mapped to the corresponding LUT according to the function requirements, avoids resource waste, and can realize simple configuration of more independent function functions at the same time.

Description

Programmable logic block based on improved lookup table structure

Technical Field

The invention relates to the field of programmable chip design, in particular to a programmable logic block based on an improved lookup table structure.

Background

A Field Programmable Gate Array (FPGA) is a semiconductor device that implements a logic circuit required by a user by reprogramming, and is one of Programmable Logic Devices (PLDs). Flash memory, antifuse and static memory (SRAM) are the most common programmable technologies used in modern FPGAs, wherein SRAM-based FPGA products account for more than 90%, and are the mainly used programmable technologies in current FPGA design.

The FPGA mainly comprises three major elements of a programmable logic block, programmable interconnection resources and a programmable input/output module, as well as programmable IP modules such as a DSP, a BRAM and the like embedded for improving operation and a PLL or a DLL for generating a clock. Programmable Logic blocks (CLBs) are the foundation and core of FPGAs. In the development history, the CLB construction mode successively appears in various forms based on NAND gates, multiplexers, lookup tables and the like. The most popular of the current commercial FPGAs are CLBs based on a look-up table structure, the basic structure of which is a plurality of basic logic cells (BLE).

As shown in fig. 1, BLE is composed of a look-up table (LUT), a register, and some multiplexers. The lookup table is responsible for realizing a multi-input Boolean function, and the realization is combinational logic; the register is responsible for carrying out register on the output of the combinational logic, so that sequential logic is realized; the multiplexer is responsible for selecting the signal to decide the current output as a combined output or a registered output.

As shown in FIG. 2, a basic structure of a 4-input lookup table (4-LUT) comprises four-bit data terminals A <1> -A <4> and a 16-bit SRAM, and can realize any 4-input combinational logic function, and a corresponding 6-LUT can realize any 6-input combinational logic function.

The look-up tables in commercial FPGAs are divided into two categories: fixed input number lookup tables and adaptive lookup tables (ALM).

As shown in fig. 3, the CLBs in the Xilinx FPGA adopt LUTs with fixed input numbers, the input number of the LUTs in the current mainstream product is 6, and each CLB includes 8 6-LUTs, and can also be combined into two slices as required. Academic research shows that 4-6 input LUTs have good balance in the aspects of area and speed, and the 6-LUT structure of Xilinx can realize more independent functions and has strong performance although the input ends of the LUTs are not shared, but causes excessive input ports and large signal depth, and the delay is increased accordingly. Since the logic of the tool mapping to 6-LUT is only 45%, there is a great waste of resources in implementing functions with fewer inputs, and the delay is increased.

As shown in fig. 4, the Altera FPGA employs an Adaptive Logic Module (ALM) structure, and each LAB is composed of 10 BLE. Each BLE consists of an ALM that can implement part 8 input logic functions and is configured as a LUT structure in various combinations. Although the number of 8-input ALM inputs is small, the biggest problem is that the shared inputs are more, so that more common inputs are needed to implement different function functions, and the constraint condition becomes very strict. To configure an 8-LUT as 2 6-LUTs requires at least three common inputs. The structure well avoids the waste of resources when fewer input functions are realized, but when a plurality of functions are realized, various constraint conditions such as a public input end and the like need to exist among different functions, the resource utilization rate is improved to avoid waste, but a packing algorithm is required to meet higher requirements, and various working modes of ALM can be fully configured.

Disclosure of Invention

To overcome the disadvantages of the prior art, an object of the present invention is to provide a programmable logic block based on an improved lookup table structure.

In order to realize the purpose of the invention, the technical scheme adopted by the invention is as follows:

a programmable logic block based on an improved lookup table structure is disclosed, wherein each basic logic unit of the programmable logic block comprises two identical PLMLs which are mutually independent and have independent input and output, carry chain structure and shift register chain structure;

each PLML comprises an LUT module, a logic operation module, a trigger module, a multiplexer module and a shift register module; the multiplexer module comprises 9 2:1 MUXs and 11 multi-selection MUXs;

the LUT module comprises 1 improved five-input lookup table (improved 5-LUT), 1 improved six-input lookup table (improved 6-LUT) and 2 four-input lookup tables (improved 4-LUT) which are mutually independent, and each LUT comprises two paths of outputs;

the logic operation module comprises 4 independent 2-input adders/subtractors Adder 1-4, wherein each Adder/subtracter is provided with a 1-path carry input end, a 2-path Adder/subtracter input end, a 1-path Adder/subtracter operation and output end and a 1-path carry output end;

the input end of the 2-path adder is from 2 LUTs, the output ends of the 4-path adder are SUM 1-4 and CY 1-4 respectively, and the SUM and CY of each path of adder are output simultaneously through two different registers;

the 4 adders/subtractors are cascaded to form a multi-bit adder, the cascade input signal is Carry _ in or 0/1, and the cascade output signal is Carry _ out;

the trigger module comprises 4 triggers, and comprises an input end D, an output end Q, a clock control end CLK, an enable end EN, a set reset end SR and an initialization signal end INIT, wherein the input end D is the output of an LUT, the operation and output end of an adder, the carry output end and the output end of a previous trigger, and realizes the multiplexing mode of the triggers through the gating of a multiplexer;

the basic logic unit is provided with 2 mutually independent shift register chains, each PLML is provided with one shift register chain, and the maximum 4-bit shift register can be realized;

each PLML fully calls the LUT, the adder and the MUX of the whole PLML through the combination of internal same or different resources, and realizes the more complicated LUT function, sequential logic function, logic operation function, multiplexer function and shift register function.

Further, the improved 4-LUT comprises a configuration memory, 4:1 MUXs and 5 2:1 MUXs, and 2 paths of outputs are formed; wherein, the output of the first 4:1MUX is used as the 2-way input of the same 2:1MUX, the output of the third 4:1MUX is used as the 2-way input of another 2:1MUX, and one-way output signal is obtained through the 2:1 MUX; the outputs of the two 2:1 MUXs enter the 2-path input of the same 2:1MUX, and the other path of output signal is obtained through gating; two independent LUTs can be configured by multiplexing and selecting address lines of the last two levels of LUTs;

the improved 5-LUT comprises a configuration memory, 4 8:1 MUXs and 5 2:1 MUXs, and 2 paths of outputs are formed; wherein, the output of the first 8:1MUX is used as the 2-way input of the same 2:1MUX, the output of the third 8:1MUX is used as the 2-way input of another 2:1MUX, and one-way output signal is obtained through the 2:1 MUX; the outputs of the two 2:1 MUXs enter the 2-path input of the same 2:1MUX, and the other path of output signal is obtained through gating; two independent LUTs can be configured by multiplexing and selecting address lines of the last two levels of LUTs;

the improved 6-LUT comprises a configuration memory, 4 16:1 MUXs and 5 2:1 MUXs, and 2 paths of outputs are formed; wherein, the output of the first 16:1MUX is used as the 2-way input of the same 2:1MUX, the output of the third 16:1MUX is used as the 2-way input of another 2:1MUX, and one-way output signal is obtained through the 2:1 MUX; the outputs of the two 2:1 MUXs enter the 2-path input of the same 2:1MUX, and the other path of output signal is obtained through gating; and two independent LUTs can be configured by multiplexing and selecting address lines of the final two levels of LUTs.

Further, the LUT register output functional modes that can be implemented include:

registered outputs of 1 independent 6-LUT, 1 independent 5-LUT, and 2 independent 4-LUT;

2 independent 5-LUTs with 2 high address lines, 2 4-LUTs and 4 register outputs with 3-LUTs;

registered outputs of two independent 6-LUTs;

two 6-LUTs having a common input; two independent 5-LUTs, 1 registered output of an independent 6-LUT;

two 5-LUTs with common inputs, 1 registered output of an independent 6-LUT;

the registered output of a complete 7-LUT.

Further, the sequential logic function modes that can be realized include:

the register output of the combined logic result of various combination modes of the LUT; 4 register outputs of adder results; register outputs of the multi-bit-width multiplexers.

Further, the register output of the logic operation function can be realized by:

registered outputs of four independent 2-input adders/subtractors; registered outputs of two multiplexed 2-input adders/subtractors; a register output of a cascaded multi-bit adder/subtractor;

wherein, the 2-way trigger multiplexing mode is used for multiplexing the Adder3 and the Adder 4; the carry output in this mode can directly bypass the Adder1 and the Adder2 to be gated by the Adder 3.

Further, the multiplexer functional modes that can be implemented include:

register outputs of 1 independent 4:1MUX, 1 independent 3:1MUX, 2 independent 2:1 MUX;

2 independent 4:1 MUXs, 1 independent 3:1MUX register output;

register outputs of 2 independent 4:1 MUXs;

the register output of the 1 8:1 MUX.

Further, LUT configuration mode and corresponding output port name:

a first LUT4 with inputs comprising a1/a2/A3/a4 and outputs comprising LUT4OUT1 and LUT3OUT 1; a second LUT4, the input of which comprises B1/B2/B3/B4 and the output of which comprises LUT4OUT2 and LUT3OUT 2; LUT5, the input of which comprises C1/C2/C3/C4/C55, and the output of which comprises LUT5OUT1 and LUT4OUT 3; the LUT6 comprises D1/D2/D3/D4/D5/D6 as input and LUT6OUT1 and LUT5OUT2 as output; a MUX1, whose inputs include C5 and L7in, and whose output is connected to the select terminal of the L5 MUX; a MUX2, whose inputs include D6 and L7in, and whose output is connected to the select terminal of the L6 MUX; a MUX3, the inputs of which include D6 and L7in, the output of which is connected to the select terminal of the L7 MUX; an L5MUX having a first input connected to the O4 output of the first LUT4, a second input connected to the O4 output of the second LUT4, and an output connected to LUT5OUT 3; an L6MUX, the first input end of which is connected with the O5 output of the LUT5, the second input end of which is connected with the output of the L5MUX, and the output end of which is connected with the LUT6OUT 2; and the first input end of the L7MUX is connected with the output of the LUT6, the second input end of the L7MUX is connected with the output of the L6MUX, and the output end of the L7MUX is connected with the LUT7 OUT.

Further, the L5MUX adopts a C5 or L7in signal as a selection end to combine two 4-LUTs to form 1 5-LUT in a cascade mode;

the L6MUX combines two 4-LUTs and 1 5-LUT to form 1 independent 6-LUT by using a D6 or L7in signal as a selection end;

the L6MUX adopts a D6 or L7in signal as a selection end to combine two 4-LUTs and 1 5-LUT to form 2 5-LUTs with a common input end;

the L7MUX combines two 4-LUTs and 1 5-LUT and 1 6-LUT into 2 6-LUTs with a shared input end by using a D6 or L7in signal as a selection end;

the L7MUX combines two 4-LUTs and 1 5-LUT and 1 6-LUT to form 1 independent 7-LUT by using a D6 or L7in signal as a selection end;

4/5/6-LUT is configured in independent mode, so that the upper 2 bits of 4-LUT, 5-LUT and 6-LUT are all independent, and 2 5-LUTs, 2 4-LUTs and 4 3-LUTs with independent partial functions are realized.

Further, the PLML structure can implement combinational logic function combinations of other smaller inputs and their corresponding registered outputs.

Compared with the prior art, the structure provided by the invention has a lookup table structure with various inputs, can be mapped to a corresponding LUT according to functional requirements, and avoids resource waste. Compared with the self-adaptive lookup table, the method can realize more independent function functions, is simpler to configure, and has no multiple limiting conditions during port configuration.

Drawings

FIG. 1 is a diagram illustrating a basic logic cell structure in the prior art;

FIG. 2 is a schematic diagram of the internal structure of a prior art 4-LUT;

FIG. 3 is a schematic representation of the composition of a prior art Xilinx CLB;

FIG. 4 is a schematic representation of the Altera ALM composition of the prior art;

FIG. 5 is a block diagram of a programmable logic block based on an improved look-up table structure of the present invention;

FIG. 6 is a schematic diagram of the internal structure of the PLML of the present invention;

FIG. 7 is a schematic diagram of the overall LUT structure of the present invention;

FIG. 8 is a schematic diagram of the overall structure of 4/5/6-LUT of the present invention, where a is the overall structure of 4/5/6-LUT, b is the common mode of 4/5/6-LUT, and c is the independent mode of 4/5/6-LUT;

FIG. 9 is a diagram of various output modes and ports of the LUT of the present invention;

FIG. 10 is a schematic diagram of four independent LUTs in LUT module mode 1 of the present invention;

FIG. 11 is a schematic diagram of address line high 2-bit independent, 4/5/6-LUT modified independent mode in LUT module mode 2 of the present invention;

FIG. 12 is a schematic diagram of 2 independent 6-LUTs in LUT module mode 3 of the present invention;

FIG. 13 is a schematic diagram of a second 6-LUT configuration in LUT module mode 3 of the present invention;

FIG. 14 is a schematic diagram of a dual 6-LUT with 1 common input in LUT module mode 4 of the present invention;

FIG. 15 is a schematic diagram of a second 6-LUT configuration in LUT module mode 4 of the present invention;

FIG. 16 is a schematic diagram of 1 6-LUT and 2 independent 5-LUTs in LUT module mode 5 of the present invention;

fig. 17 is a schematic diagram of a second 5-LUT configuration in LUT module mode 5 of the present invention;

FIG. 18 is a schematic diagram of 1 6-LUT, 1 independent 5-LUT and 1 shared input 5-LUT in LUT module mode 6 of the present invention;

FIG. 19 is a schematic diagram of a second 5-LUT configuration in LUT module mode 6 of the present invention;

FIG. 20 is a schematic diagram of a1 independent 7-LUT configuration in LUT module mode 7 of the present invention;

FIG. 21 is a circuit schematic of an arithmetic logic block of the present invention, a being a block output with register of an adder, b being a normal mode of the adder, c being a multiplexing mode of the adder;

FIG. 22 is a schematic diagram of a normal mode MUX configuration in multiple bit wide Multiplexer (MUX) module mode 1 of the present invention;

FIG. 23 is a schematic diagram of the configuration of 2 4:1 MUXs and 1 3:1MUX in multi-bit-width Multiplexer (MUX) module mode 2 of the present invention;

FIG. 24 is a schematic diagram of two 4:1MUX configurations in multi-bit wide Multiplexer (MUX) module mode 3 of the present invention;

FIG. 25 is a schematic diagram of the 8:1MUX configuration in multi-bit wide Multiplexer (MUX) module mode 4 of the present invention;

FIG. 26 is a diagram illustrating the common mode LUT register output of the present invention;

FIG. 27 is a schematic diagram of the LUT register output after the L5MUX, the L6MUX, and the L7MUX have been cascaded in accordance with the present invention;

fig. 28 is a schematic diagram of an SRL mode configuration according to the present invention.

Detailed Description

The technical solution of the present invention is further described below with reference to the accompanying drawings and examples. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present application is not limited thereby.

As shown in fig. 5, the Programmable Logic block based on the improved lookup table structure of the present invention is composed of two identical PLMLs (Programmable Logic modules-Logic), and the two PLMLs are independent from each other and have independent input/output, carry chain structure and shift register structure.

As shown in fig. 6, each PLML includes resources of 4 advanced dual-output LUTs (advanced 4-LUT2, advanced 5-LUT 1, advanced 6-LUT 1), 4 adders, 4 flip-flops, and a plurality of multiplexers (9 2:1 muxes and 11 MUX-ones), which have three granularities, and can implement a combinational logic function, a sequential logic function, and an arithmetic operation function. Each PLML includes the following resources:

(1) a LUT of multiple inputs;

1 complete modified 6-input look-up table 6-LUT, and its inputs D1, D2, D3, D4, D5, D6; a complete modified 5-input look-up table 5-LUT, with its inputs C1, C2, C3, C4, C5; two complete modified 4-input look-up tables 4-LUT, the first four-input look-up table inputs being B1, B2, B3, B4; the second four-input lookup table inputs are a1, a2, A3, a 4; input L7 in.

The specific structure of the improved dual-output LUT is shown in fig. 8.

(2) A trigger;

the trigger comprises a trigger input end D, a trigger output end Q, a clock control end CLK, an enable end EN, a set reset end SR and an initialization signal INIT, and can realize the trigger function and the LATCH function of level triggering and edge triggering; and realizing the power-on initialization function of the FPGA.

(3) Performing logic operation;

4 independent 2-input Adder/subtracter adders 1-4, each Adder having 1-way carry input, 2-Adder input, 1-way Adder operation SUM (SUM) output and Carry (CY) output. The input end of the 2-path adder is from 2 LUTs, and preprocessing operation on the input signal can be realized in the LUTs. Output ports of the 4-path adder are SUM 1-4 and CY 1-4 respectively. SUM and CY of each way adder may be output simultaneously through two different registers.

2-way flip-flop multiplexing mode, multiplexing Adder3 and Adder 4. In the multiplexing mode, the LUT of the whole PLML can be fully called, and the high input preprocessing capacity of the 5-LUT and the 6-LUT is exerted, so that more complex logic operation can be processed. The carry output in this mode can directly bypass the Adder1 and the Adder2 to be gated by the Adder 3.

The 4 adders are cascaded to form a multi-bit adder/subtracter and can be cascaded with other CLBLLs, the cascade input signal is Carry _ in or 0/1, the cascade output signal is Carry _ out, and the input signals of the two cascaded adders can also be preprocessed.

(4) A Multiplexer (MUX) of a plurality of bit widths;

the types of pair-way selectors that may be implemented by configuring the LUT include 4:1MUX, 3:1MUX, 2:1MUX, and 8:1 MUX.

(5) A Shift Register (SRL);

the cascade connection of 4 registers can realize the highest 4-bit shift register, each PLML has one and is mutually independent, and 2 shift register chains are total to one CLBLL.

Each PLML can realize the functions of LUT, adder and MUX with stronger functions through the combination of internal same or different resources, and can realize register output, thereby expanding the application range and improving the resource utilization rate. The PLML may implement the following functions:

(1) a LUT function;

1 independent 6-LUT, 1 independent 5-LUT, 2 independent 4-LUT; 2 high independent 5-LUTs 2 of address line, 2 of 4-LUTs and 4 of 3-LUTs; two 5-LUTs with 1 common input, 1 independent 6-LUT; 1 6-LUT, 2 independent 5-LUTs; two 6-LUTs with common inputs and 1-out-of-2 multiplexer; two independent 6 LUTs; a complete 7-LUT.

(2) A sequential logic function;

registered outputs of the combinatorial logic results from the various combinatorial modes of the LUT; 4 register outputs of adder results; register output of the MUX with various bit widths; and (4) register output of signals such as bypass signals.

(3) A logical operation function;

four independent 2-input adders/subtractors; two multiplexed 2-input adders/subtractors; a cascaded multi-bit adder/subtractor.

(4) A multi-bit wide Multiplexer (MUX) function;

1 independent 4:1MUX, 1 independent 3:1MUX, 2 independent 2:1 MUX; 2 independent 4:1 MUXs, 1 independent 3:1 MUXs; 2 independent 4:1 MUXs; 1 8:1 MUX.

(5) A Shift Register (SRL) function;

2 independent shift register chains, each of which can realize 4bit shift register SRL at most.

The detailed functions and expansions of the modules are analyzed as follows.

LUT module

As shown in FIG. 8, the improved structure of 4/5/6-LUT in the invention, a is 4/5/6-LUT overall structure design, b is 4/5/6-LUT common mode, and c is 4/5/6-LUT independent mode. By multiplexing and selecting the address lines of the final two levels of LUTs, two independent LUTs can be configured, and the independence is improved.

The improved 4-LUT structure comprises a configuration memory, 4:1 MUXs, 5 2:1 MUXs, and an improved 4-LUT forming a 2-way output. Wherein, the output of the first 4:1MUX is used as the 2-way input of the same 2:1MUX, the output of the third 4:1MUX is used as the 2-way input of another 2:1MUX, and one-way output signal is obtained through the 2:1 MUX; the outputs of the two 2:1 MUXs enter the 2-way input of the same 2:1MUX, and the other output signal is obtained through gating.

The improved 5-LUT structure comprises a configuration memory, 4 8:1 MUXs and 5 2:1 MUXs, and forms a 2-path output improved 5-LUT. Wherein, the output of the first 8:1MUX is used as the 2-way input of the same 2:1MUX, the output of the third 8:1MUX is used as the 2-way input of another 2:1MUX, and one-way output signal is obtained through the 2:1 MUX; the outputs of the two 2:1 MUXs enter the 2-way input of the same 2:1MUX, and the other output signal is obtained through gating.

The improved 6-LUT structure comprises a configuration memory, 4 16:1 MUXs, 5 2:1 MUXs, and an improved 6-LUT forming a 2-way output. Wherein, the output of the first 16:1MUX is used as the 2-way input of the same 2:1MUX, the output of the third 16:1MUX is used as the 2-way input of another 2:1MUX, and one-way output signal is obtained through the 2:1 MUX; the outputs of the two 2:1 MUXs enter the 2-way input of the same 2:1MUX, and the other output signal is obtained through gating.

Based on this, a programmable logic block structure as shown in fig. 7 is constructed. As shown in fig. 7, the overall structure of the LUT module when implementing the function is mainly divided into two categories: and the combinational logic output and the register output respectively correspond to the combinational logic output and the time sequence output. The register output of the LUT result is detailed in the flip-flop module. The output result of the combinational logic is divided into two types, and the LUT result is directly output and combined with a plurality of LUTs to form a higher input LUT to be output.

As shown in fig. 9, the combination of LUTs and corresponding output port names in various configuration modes: a first LUT4 with inputs comprising a1/a2/A3/a4 and outputs comprising LUT4OUT1 and LUT3OUT 1; a second LUT4, the input of which comprises B1/B2/B3/B4 and the output of which comprises LUT4OUT2 and LUT3OUT 2; LUT5, the input of which comprises C1/C2/C3/C4/C55, and the output of which comprises LUT5OUT1 and LUT4OUT 3; the input of the LUT6 comprises D1/D2/D3/D4/D5/D6, and the output comprises LUT6OUT1 and LUT5OUT 2; a MUX1, whose inputs include C5 and L7in, and whose output is connected to the select terminal of the L5 MUX; a MUX2, whose inputs include D6 and L7in, and whose output is connected to the select terminal of the L6 MUX; a MUX3, the inputs of which include D6 and L7in, the output of which is connected to the select terminal of the L7 MUX; an L5MUX having a first input connected to the O4 output of the first LUT4, a second input connected to the O4 output of the second LUT4, and an output connected to LUT5OUT 3; an L6MUX, the first input end of which is connected with the O5 output of the LUT5, the second input end of which is connected with the output of the L5MUX, and the output end of which is connected with the LUT6OUT 2; and the first input end of the L7MUX is connected with the output of the LUT6, the second input end of the L7MUX is connected with the output of the L6MUX, and the output end of the L7MUX is connected with the LUT7 OUT.

The LUT with 4-7 inputs is realized from the type, and various configuration modes of the LUT are analyzed in detail below.

(1) Mode 1, as shown in fig. 10, 4 completely independent LUTs can be directly configured in the normal mode of the entire PLML: 1 6-LUT, 1 5-LUT, 2 4-LUTs, which are also the most common modes when mapping.

(2) Mode 2, as shown in fig. 11, 4/5/6-LUTs of the entire PLML are configured in an independent mode, in which case a 4/5/6-LUT independent structure as shown in fig. 8c is adopted, so that the upper 2 bits of the 4-LUT, 5-LUT, 6-LUT are all independent of each other, thereby realizing a partially function independent LUT: 2 5-LUTs, 2 4-LUTs, 4 3-LUTs, up to 8 logic functions can be implemented in this mode.

(3) Mode 3, as shown in FIG. 12, the entire PLML can be configured as 2 independent 6-LUTs, with the first 6-LUT directly employing LUT6 in the PLML. As shown in fig. 13, the second 6-LUT is a combination of two 4-LUTs and 1 5-LUT, and the control terminal uses the L7in signal.

(4) Mode 4, as shown in fig. 14, the entire PLML may be configured as 2 6-LUTs with common input terminals, wherein the first 6-LUT directly adopts LUT6 in PLML, as shown in fig. 15, the second 6-LUT is formed by combining two 4-LUTs and 1 5-LUT, and the control terminal of the last stage selects D6 signal as the common input signal.

(5) Mode 5, as shown in FIG. 16, the entire PLML can be configured as 1 6-LUT, 2 independent 5-LUTs. The 6-LUT and the first 5-LUT directly use the LUT provided in PLML, as shown in fig. 17, the second 5-LUT is formed by combining two 4-LUTs, and the final stage control terminal uses the L7in signal.

(6) Mode 6, as shown in FIG. 18, the entire PLML can be configured as 1 6-LUT, 1 independent 5-LUT and 1 shared input 5-LUT. The 6-LUT and the first 5-LUT directly use the LUT provided in PLML, as shown in fig. 19, the second 5-LUT is formed by combining two 4-LUTs, and the control terminal of the last stage uses the C5 signal as a common input signal.

(7) Mode 7, as shown in FIG. 20, the entire PLML may be configured as 1 LUT that implements the full 7 input function, with the L5MUX select terminal multiplexing the C5 signal and the L6MUX select terminal multiplexing the D6 signal.

(II) logical operation module

As shown in FIG. 21(a), the whole PLML includes 4 independent adders Adder 1-4, SUM 1-4 and CY 1-4 as output ports, and a cascade input signal Cary _ in and a cascade output signal Cary _ out.

In the normal mode, each adder can implement a 2-input 1-bit adder, and SUM and carry outputs CY can be selected and output directly from D2-4 and in the next stage PLML via CY4_ P by D1 or via flip-flop register. At this time, SUM and CY of each adder are independent, and 1bit adder realizing 1 input 2 can output simultaneously. The 4 adders may implement addition and subtraction operations by making 0/1 selections on the carry inputs.

In the flip-flop multiplexing mode, the first input of the adapter 3 is the data pre-processed by the 5-LUT and the second input is the data pre-processed by the 1 st 4-LUT; the Adder4 has a first input terminal for data pre-processed by a 6-LUT and a second input terminal for data pre-processed by a2 nd 4-LUT. At the same time, the O5 output of the 6-LUT may be output from the QB and DB ports, and the O4 output of the 5-LUT may be output from the QA and DA ports. In the multiplexing mode, 4 LUTs with different granularities in the whole PLML can be fully utilized, and the high input preprocessing capacity of the 5-LUT and the 6-LUT is exerted so as to process more complicated and independent logic operation. Meanwhile, the second output end O5 of the 6-LUT and the second output end O4 of the 5-LUT can also realize a logic function, so that the highest resource utilization rate is ensured. In this mode, the input Carry _ in can directly bypass the Adder1 and the Adder2 to send data to the Adder 3. Multiplexing the

adders

3 and 4 can reduce the output delay to some extent.

(III) Multi-bit wide Multiplexer (MUX)

(1) Mode 1, as shown in fig. 22, four independent LUTs for the entire PLML can implement 1 4:1MUX, 1 3:1MUX, and 2:1 muxes, while direct output or register output can be selected.

(2) Mode 2, as shown in fig. 23, the 2:1MUX implemented by two 4-LUTs can implement 4:1MUX by L5MUX, and at this time, the control terminal of L5MUX selects L7in, and at this time, the input signals of A3 and B3 are fixed to 0 or 1.

(3) In mode 3, as shown in fig. 24, two 4-LUTs and 5-LUTs are combined into a 4:1MUX, in which case the control terminal of the L5MUX is C5, the control terminal of the L6MUX is L7in, the a1 to a4 and B1 to B460 of the 4-LUR are configured to have the same data, and the input signals of A3, B3, and C3 are fixed to 0 or 1.

(4) Mode 4, as shown in FIG. 25, two 4:1MUX is cascaded into 1 8:1MUX, the control end of the L5MUX can be C5 or L7in, the control end of the L6MUX can be D6, the control end of the L7MUX can be L7in, the A1-A4 and B1-B4 of the 4-LUT are configured into the same data, and the input signals of A3, B3 and C3 are fixed to be 0 or 1.

(IV) trigger

The flip-flop can realize the functions of level triggering, edge triggering and LATCH, and can realize the power-on initialization function of the FPGA at the same time, and the main ports are an input port D, an output port Q, a clock control port CLK, an enable port EN, a set reset port SR and an initialization signal INIT; the register output of the signals of the combined circuit modules such as LUT, MUX, adder and the like can be realized. The configuration method of the register output of the adder and the multi-selector can refer to the corresponding contents of the second part and the third part. As shown in fig. 26, the register output of the LUT in the normal mode is listed, and as shown in fig. 27, the register output mode when the LUT having a higher input is cascaded by the L5MUX, the L6MUX, and the L7MUX is listed.

(V) Shift Register (SRL) mode

In the present invention, each output of a total of 4 flip-flops can be gated by the D input of the flip-flop with a lower bit, and the four flip-flops are sequentially cascaded as shown in fig. 28, and are connected in a manner of RCASIN- > QD- > QC- > QB- > QA- > RCASOUT, thereby forming a 4-bit shift register under the clock action.

To further verify the performance of the solution of the present invention, the area of the solution of the present invention was compared with the area of three reference structures, as shown in table 1. The present invention is advantageous in balancing performance and area (cost), and achieves greater performance with less area.

TABLE 1

Comparing the performance of the reference structure 1 with that of the scheme of the present invention, as shown in table 2, it can be seen that, compared with the CLBLL structure composed of 8 4-LUTs with a smaller area, although the area of the scheme is increased, the LUT that can be implemented is more functional, and more 6-LUTs and even 7-muxes can be implemented, which is more suitable for the use of modern commercial FPGAs. And MUXs with various bit widths have better use range.

TABLE 2

Comparing the performance of the reference structure 2 with that of the solution of the present invention, as shown in table 3, it can be seen that the resource consumption and the occupied area of the CLBLL structure with 8 complete 6-LUTs are relatively large, but the mapping ratio of the 6-LUT is less than 50% in practical use, so that the area overhead is increased geometrically compared with the mapping to 4-LUT and 5-LUT, and meanwhile, because the logic depth is large, the delay is increased, the operating frequency of the CLBLL structure is reduced, compared with the LUT structure of the present solution, the present invention is more flexible, and can implement logic functions with various inputs, and the area of the LUT functional module is saved by nearly 50%.

TABLE 3

Comparing the performance of the reference structure 3 with that of the scheme of the present invention, as shown in table 4, it can be seen that the LAB structure of Altera Stratix can only implement 10 4-LUTs, but cannot implement LUTs with higher inputs, the flexibility of the structure in the present invention is greatly increased, 2 complete 7-input LUTs can be implemented in many groups, and two independent carry chains are provided, so that more arithmetic operations can be performed simultaneously in one programmable logic block.

TABLE 4

The present applicant has described and illustrated embodiments of the present invention in detail with reference to the accompanying drawings, but it should be understood by those skilled in the art that the above embodiments are merely preferred embodiments of the present invention, and the detailed description is only for the purpose of helping the reader to better understand the spirit of the present invention, and not for limiting the scope of the present invention, and on the contrary, any improvement or modification made based on the spirit of the present invention should fall within the scope of the present invention.

Claims

1. A programmable logic block based on an improved lookup table structure is characterized in that each basic logic unit of the programmable logic block comprises two identical mutually independent PLMLs with independent input and output and carry chain structures and shift register chain structures;

2. The improved lookup table structure based programmable logic block of claim 1 wherein,

the improved 4-LUT comprises a configuration memory, 4:1 MUXs and 5 2:1 MUXs, and 2 paths of outputs are formed; wherein, the output of the first 4:1MUX is used as the 2-way input of the same 2:1MUX, the output of the third 4:1MUX is used as the 2-way input of another 2:1MUX, and one-way output signal is obtained through the 2:1 MUX; the outputs of the two 2:1 MUXs enter the 2-path input of the same 2:1MUX, and the other path of output signal is obtained through gating; two independent LUTs can be configured by multiplexing and selecting address lines of the last two levels of LUTs;

3. The improved look-up table structure based programmable logic block of claim 1, wherein the LUT register output functional modes that can be implemented comprise:

registered outputs of two independent 6-LUTs;

two 5-LUTs with common inputs, 1 registered output of an independent 6-LUT;

the registered output of a complete 7-LUT.

4. The programmable logic block based on the improved lookup table structure of claim 1 wherein the achievable sequential logic function modes include:

5. The programmable logic block based on the improved lookup table structure as claimed in claim 1, wherein the register output of the logic operation function that can be realized comprises:

6. The programmable logic block based on the improved lookup table structure of claim 1 wherein the multiplexer function modes that can be implemented include:

2 independent 4:1 MUXs, 1 independent 3:1MUX register output;

register outputs of 2 independent 4:1 MUXs;

the register output of the 1 8:1 MUX.

7. The programmable logic block based on the improved lookup table structure of claim 1 wherein LUT configuration modes and corresponding output port names:

8. The improved lookup table structure based programmable logic block of claim 7 wherein,

the L5MUX adopts a C5 or L7in signal as a selection end to combine two 4-LUTs to cascade into 1 5-LUT;

9. The programmable logic block based on the improved lookup table structure of claim 1 wherein the PLML structure can implement combinational logic function combinations of other smaller inputs and their corresponding registered outputs.