JP3923672B2 - Computing unit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a temporary data storage device such as a latch circuit and a flip-flop circuit, which is mainly realized by a semiconductor integrated circuit.Arithmetic unit havingIt is about.
[0002]
[Prior art]
In recent years, the progress of semiconductor integrated circuits has been remarkable, and the development for higher performance has been promoted such as higher integration, higher speed operation, and lower power consumption. From the viewpoint of developing a circuit that operates at higher speed, various types of circuits have been devised and studied.
[0003]
Currently, almost all semiconductor integrated circuits that operate at high speed have a clock synchronous circuit configuration that operates in synchronization with a clock signal. For example, a data processing device that operates in synchronization with a clock mounted in a microcomputer or the like. And the like, the logic operation circuit is sandwiched by a data temporary storage device such as a flip-flop (hereinafter referred to as FF) that writes / holds data in synchronization with the clock signal, and the clock signal is supplied to the data temporary storage device. Thus, a configuration that operates in synchronization with a clock signal is widely used.
[0004]
In order to increase the operation speed of the data processing device having such a configuration, the operation time of the logic operation circuit is shortened, and the operation in the logic circuit is completed within a shorter clock cycle period. This is realized by increasing the frequency of the clock signal supplied to the.
[0005]
In order to shorten the operation time of the logic operation circuit toward increasing the operating frequency, a technique using a logic circuit having a circuit configuration that performs a dynamic operation such as a domino logic circuit instead of a static circuit configuration is also known.
[0006]
As an example of such a prior art, there is a Manchester carry adder described on page 281 of “CMOS VLSI design principle: from a system viewpoint” published by Maruzen Co., Ltd. This Manchester carry adder is a kind of domino logic circuit, and is a circuit that propagates carry signals at high speed by adopting a circuit configuration that performs dynamic operation.
[0007]
Hereinafter, the Manchester carry adder will be described with reference to the drawings. FIG. 7 is a circuit diagram showing an example of a carry chain unit of a Manchester carry adder which is a kind of conventional domino logic circuit.
[0008]
In FIG. 7, reference numerals 1015 to 1019 denote P-channel transistors (hereinafter referred to as P-Tr) whose gates are connected to the clock signal CK, which are turned on when the clock signal CK is 0 and precharge the nodes X0 to X4. . Reference numerals 1010 to 1014 denote N-channel transistors (hereinafter referred to as N-Tr) whose gates are connected to the clock signal CK, which are turned on when the clock signal CK is 1. Reference numerals 1001 to 1009 denote N-Tr, which are turned on when the gate signal is 1, respectively.
[0009]
The carry chain part of this Manchester carry adder includes 4-bit carry propagation signals (propagation signals) P1 to P4, 4-bit carry generation signals (generation signals) G1 to G4, and lower-order digits. This is a circuit for generating a carry signal C4 for the upper digit using the carry signal C0.
[0010]
In the operation, first, during a period when the clock signal CK is 0, the P-Trs 1015 to 1019 are turned on, and the nodes X0 to X4 are precharged. Next, during the period when the clock signal CK is 1, the N-Trs 1010 to 1014 are turned on, and the N-Trs 1001 to 1009 are turned on and off to open a path to the ground among the nodes X0 to X4. Discharge is performed for nodes that are present, and no discharge is performed for nodes that are not open to the ground. At this time, if the node of X4 is discharged, the carry signal C4 to the upper digit is 1 and is 0 if not discharged.
[0011]
For example, when the carry signal G1 of the first bit and the carry propagation signals P2 to P4 of the second to fourth bits are 1, when the clock signal CK becomes 1, the node X4 becomes N-Tr 1004 It is discharged through the paths 1003, 1002, 1006, 1011. When X4 becomes 0, the carry signal C4 becomes 1, and a carry signal to the upper digit is generated. Similarly, when the clock signal CK becomes 1, C4 is determined to be 0 or 1 depending on the combination of the input signals P1 to P4, G1 to G4, and C0.
[0012]
  In this circuit, when the carry signal C4 to the upper digit changes from 0 to 1, when the delay time is the slowest, the carry signal C0 from the lower digit and the first to fourth bits When only the carry propagation signals P1 to P4 are 1 and the other carry generation signals G1 to G4 are 0, and the CK changes from 0 to 1 in this state, the precharged node X4 is , N-Tr1004, 1003, 1002, 1001, 1005, 1010 through a path in which six transistors are connected in series.CIt is supposed to be discharged to the terminal.
[0013]
As described above, when the carry chain circuit of the conventional Manchester carry adder described above is used, the 4-bit propagation signals P1 to P4, the 4-bit generation signals G1 to G4, and the carry signal C0 from the lower digits are used. Is used to generate the carry signal C4 to the upper digit, the worst delay time is to discharge the node X4 through the six N-Trs 1004, 1003, 1002, 1001, 1005, 1010 connected in series, It was a delay time until the inverted signal of the node X4 was created by the inverter composed of the P-Tr 1021 and the N-Tr 1020.
[0014]
Further, regarding a data temporary storage device that is arranged before and after the above-described domino logic type dynamic circuit and operates in synchronization with the clock signal, the data is taken in at the rising or falling edge of the clock signal, and the other F. that data is retained for the period. F. Circuits are widely used.
[0015]
Hereinafter, referring to the drawings, the above-described F.I. F. The circuit will be described. FIG. F. A type of F.C. that is connected to a level latch, which is a type of circuit, in series, and captures data at the rising edge of the clock. F. The circuit is shown.
[0016]
In FIG. 8, reference numeral 1101 denotes a level latch which writes data when the clock signal CK is 0, and holds data when the clock signal CK is 1, 1102 is a level latch which holds data when the clock signal CK is 1, and holds data when the clock signal CK is 0 The output of the level latch 1101 is input to the level latch 1102.
[0017]
For this reason, while the clock signal CK is 0, the value of DIN is written to the level latch 1101. However, since the level latch 1102 is a data holding period, the output of the level latch 1102 does not change.
[0018]
When the clock signal CK changes from 0 to 1 (at the rising edge), the value of DIN immediately before the rising edge of the clock signal CK is stored in the level latch 1101, and the output of the level latch 1101 immediately after the rising edge of CK. Is written to the level latch 1102 and output.
[0019]
Since the level latch 1101 is a data holding period when the clock signal CK is 1, the input data of the level latch 1102 does not change, so the output of the level latch 1102 does not change. Further, when the clock signal CK changes from 1 to 0 (at the falling edge), the output of the level latch 1102 does not change as in the period when the clock signal CK is 1.
[0020]
In order to perform such an operation, F. of FIG. F. Indicates that the DIN data is written at the timing of the rising edge of CK, and the data is held during other periods. F. Performs circuit operation. FIG. F. An operation timing chart of the circuit is shown.
[0021]
In addition, the conventional F.I. F. From the addend and algend stored in the circuit, the carry generation signal of each bit, which is the input signal of the carry chain unit of the above-described conventional Manchester carry adder, and the carry propagation signal of each bit are obtained. In order to generate them, the logical product circuit of the addend and the algend of each bit and the exclusive OR circuit of the addend and the addend of each bit were created. FIG. 10 shows an example of a conventional AND circuit, and FIG. 11 shows an example of an exclusive OR circuit.
[0022]
[Problems to be solved by the invention]
However, the conventional F.D. F. The carry generation signal for each bit and the carry propagation signal for each bit created using the above AND circuit and exclusive OR circuit are input to the addend and algend stored in In FIG. 7, the nodes X0 to X4 are precharged during the period when the clock signal CK is 0 in FIG. When the discharge path to the ground is connected, the precharge state is destroyed, so that N-Trs 1010 to 1014 that are turned off during the period when the clock signal CK is 0 have to be arranged at the positions shown in FIG. .
[0023]
For this reason, the path for discharging the node X4 that is the inverted signal of the carry signal to the upper digit must always pass through any one of the N-Trs 1010 to 1014. In the path where the operation becomes slow, it is necessary to pass through the sixth N-Tr 1010 that inputs CK in addition to the five N-Tr that inputs essentially five signals P1 to P4 and C0. In addition, there is a problem that the worst operation time becomes a delay time for passing six N-Trs, which is one more than the essential delay time for passing five N-Trs.
[0024]
  Therefore, in view of the above problems, the present invention is turned off when the clock signal is 0, which is necessary in the domino logic circuit represented by the carry chain portion of the Manchester carry adder having the above-described configuration. Temporary data storage device which eliminates N-Tr for preventing destruction of precharge state of precharge node and improves operation delay time of domino logic circuitArithmetic unit havingThe purpose is to provide.
[0025]
[Means for Solving the Problems]
  In order to achieve the above object, claim 1 is provided.~ 3Data temporary storage device described inArithmetic unit havingInputs a clock signal and a data signal, data is written when the clock signal is in the first phase, and data is held when the clock signal is in the opposite phase to the first phase.FirstA level latch, the clock signal and theFirstAn output signal of a level latch is input, and 0 is output during a period in which the clock signal is in the first phase, and a period in which the clock signal is in an opposite phase to the first phaseFirstOutputs the value of the input signal from the level latchFirstWith decoding circuitAn input signal of the first decoding circuit, and a first transistor connected to the first node and the ground,
  Furthermore, a clock signal and a data signal are input, data writing is performed during a period in which the clock signal is in the first phase, and data is retained in a period in which the clock signal is in a phase opposite to the first phase. The level latch, the clock signal, and the output signal of the second level latch are input, and 0 is output during a period in which the clock signal is in the first phase, and the clock signal is opposite to the first phase. During the phase period, the second decode circuit that outputs the value of the input signal from the second level latch and the output signal of the second decode circuit are input and connected to the second node and ground. A third transistor that receives the clock signal, and a fourth transistor that precharges the second node during a period in which the clock signal is in the first phase; The clock signal and the data signal are input, data writing is performed during the period in which the clock signal is in the first phase, and data is retained in the period in which the clock signal is in the opposite phase to the first phase. The latch, the clock signal, and the output signal of the third level latch are input, and 0 is output during a period in which the clock signal is in the first phase, and the clock signal is in phase opposite to the first phase. And a third decode circuit that outputs the value of the input signal from the third level latch, and an output signal of the third decode circuit, and inputs the first node and the second node Consisting of a fifth transistor connected to the
  The input of the first transistor and the input of the third transistor are signals for generating a carry of a carry chain of a Manchester carry adder, and the input of the fifth transistor is the signal This signal propagates the carry signal from the carry chain of the Manchester carry adder, and outputs the carry signal to the upper digit.It is characterized by.
[0026]
  thisComputing unitAccording to the data temporary storage device, the value of the data signal is written at a timing when the clock signal changes from the period of the first phase to the period of the phase opposite to the first phase, and the clock signal is changed to the first phase. The written value can be output from the data output terminal during the period that is opposite phase, and 0 can be output when the clock signal is in the first phase.As a result, the clock signal is turned off during the period of 0, which is necessary in the domino logic circuit represented by the carry chain of the conventional Manchester carry adder, and the precharge state of the precharge node is destroyed. N-Tr for avoiding stuttering can be eliminated, and the operation delay time of the Domino logic circuit can be improved.The
[0027]
  Further, the claims of the present invention4-6Data temporary storage device described inArithmetic unit havingEach of which receives a clock signal and a data signal, writes data when the clock signal is in the first phase, and holds data when the clock signal is in the opposite phase to the first phase. ofFirstLevel latch and saidFirstIt has the same number of data input terminals and any number of output terminals as the number of level latches, and the clock signal and the plurality of output terminals.FirstDuring the period in which each output signal of the level latch is input and the clock signal is in the first phase, each of the output terminals outputs 0, and the clock signal is in phase opposite to the first phase. Each of the output terminals has the plurality of periods.FirstOutput different logical operation results for each input signal value from the level latchFirstWith decoding circuitThe output signal of the first decoding circuit is input, the first transistor connected to the first node and ground, the clock signal is input, and the period in which the clock signal is in the first phase is A second transistor for precharging the first node;
  Further, each of the plurality of clock signals and the data signal is input, data is written during a period in which the clock signal is in the first phase, and data is held in a period in which the clock signal is in the opposite phase to the first phase. Second level latches, the same number of data input terminals as the number of the second level latches, and an arbitrary plurality of output terminals, and the clock signal and the output signals of the plurality of second level latches. When the clock signal is in the first phase, each output terminal outputs 0, and when the clock signal is in the opposite phase to the first phase, each output terminal Respectively input a second decoding circuit that outputs a different logical operation result of each input signal value from the plurality of second level latches, and an output signal of the second decoding circuit. A third transistor connected to a second node and ground; a fourth transistor that receives the clock signal and precharges the second node during a period in which the clock signal is in a first phase; , Each of which receives a clock signal and a data signal, data writing is performed during a period in which the clock signal is in the first phase, and data is retained in a period in which the clock signal is in the opposite phase to the first phase. A third level latch, the same number of data input terminals as the number of the third level latches, and an arbitrary plurality of output terminals, and the clock signal and the output signals of the plurality of third level latches are input. Then, during the period in which the clock signal is in the first phase, each output terminal outputs 0, and the clock signal is in the opposite phase to the first phase. During the period, each output terminal outputs a third decoding circuit that outputs a different logical operation result of each input signal value from each of the plurality of third level latches, and the output signal of the third decoding circuit And comprising a fifth transistor connected to the first node and the second node;
  The input of the first transistor and the input of the third transistor are signals for generating a carry of a carry chain of a Manchester carry adder, and the input of the fifth transistor is the signal This signal propagates the carry signal from the carry chain of the Manchester carry adder and outputs the carry signal to the upper digit.It is characterized by that.
[0028]
  the aboveComputing unitAccording to the data temporary storage device, the values of the plurality of data signals are written at the timing when the clock signal changes from the period in which the clock signal is in the first phase to the period in phase opposite to the first phase, and the clock signal is in the first phase. During the period that is opposite to the phase, the different logical operation results of the written multiple values are output from any of the plurality of data output terminals, respectively, and when the clock signal is in the first phase, the multiple data output Both terminals can output 0As a result, the clock signal is turned off during the period of 0, which is necessary in the domino logic circuit represented by the carry chain of the conventional Manchester carry adder, and the precharge state of the precharge node is destroyed. N-Tr for avoiding stuttering can be eliminated, and the operation delay time of the Domino logic circuit can be improved.The
[0029]
  Further, as a specific configuration, the claims of the present invention7-9Data temporary storage device described inArithmetic unit havingEach receives a clock signal and a data signal, data is written when the clock signal is in the first phase, and data is held when the clock signal is in the opposite phase to the first phase 2 HornFirstLevel latch and the twoFirstEach of the level latches has two data input terminals for inputting each output signal and two output terminals, and the clock signal and the twoFirstEach of the output signals of the level latch is input, and during the period in which the clock signal is in the first phase, the two output terminals output 0 respectively, and the clock signal is in an opposite phase to the first phase. During a certain period, one output terminalFirstThe logical product of the input signals from the level latch is output, and the other output terminalFirstOutput logical sum of input signals from level latchFirstWith decoding circuitThe output signal of the first decoding circuit is input, the first transistor connected to the first node and ground, the clock signal is input, and the period in which the clock signal is in the first phase is A second transistor for precharging the first node;
  Further, each receives a clock signal and a data signal, data is written when the clock signal is in the first phase, and data is held when the clock signal is in the opposite phase to the first phase. Two second level latches, two data input terminals for inputting respective output signals of the two second level latches, and two output terminals, the clock signal and the two second level latches In the period when the clock signal is in the first phase, the two output terminals output 0, and the clock signal is in a phase opposite to the first phase. One output terminal outputs a logical product of the input signals from the two second level latches, and the other output terminal outputs a logical sum of the input signals from the two second level latches. A second decode circuit, an output signal of the second decode circuit, a third transistor connected to a second node and ground, the clock signal, and the clock signal A period that is one phase is a fourth transistor that precharges the second node, each receiving a clock signal and a data signal, and a period in which the clock signal is in the first phase is data writing, Two third level latches for holding data during a period in which the clock signal is in the opposite phase to the first phase, and two data input terminals for inputting the respective output signals of the two third level latches, Two output terminals, the clock signal and the output signals of the two third level latches are input, and the clock signal is in the first phase In the period when the two output terminals each output 0 and the clock signal is in the opposite phase to the first phase, one output terminal is the logic of the input signal from the two third level latches. A third decode circuit that outputs a logical sum of input signals from the two third level latches, and an output signal of the third decode circuit. A first transistor and a fifth transistor connected to the second node;
  The input of the first transistor and the input of the third transistor are signals for generating a carry of a carry chain of a Manchester carry adder, and the input of the fifth transistor is the signal This signal propagates the carry signal from the carry chain of the Manchester carry adder and outputs the carry signal to the upper digit.It is characterized by this.
[0030]
  the aboveComputing unitAccording to the data temporary storage device, the values of the two data signals are written at a timing when the clock signal changes from the period of the first phase to the period of the phase opposite to the first phase, and the clock signal is During a period opposite to the phase, one of the two data output terminals outputs a logical product of the two written values, the other output terminal outputs a logical sum, and the clock signal is During the period of one phase, both data output terminals can output 0.As a result, the clock signal is turned off during the period of 0, which is necessary in the domino logic circuit represented by the carry chain of the conventional Manchester carry adder, and the precharge state of the precharge node is destroyed. N-Tr for avoiding stuttering can be eliminated, and the operation delay time of the Domino logic circuit can be improved.The
[0031]
  Claims10-12Data temporary storage device described inArithmetic unit havingEach receives a clock signal and a data signal, data is written when the clock signal is in the first phase, and data is held when the clock signal is in the opposite phase to the first phase 2 HornFirstLevel latch and the twoFirstEach of the level latch has two data input terminals for inputting each output signal, two inverted signal input terminals for inputting an inverted signal of each output signal, and two output terminals, and the clock signal and each output signal. And the respective inverted signals are input, and during the period in which the clock signal is in the first phase, the two output terminals each output 0, and the clock signal is in phase opposite to the first phase. During the period, one output terminalFirstThe logical product of the input signals from the level latch is output, and the other output terminalFirstOutput exclusive OR of input signals from level latchFirstWith decoding circuitThe output signal of the first decoding circuit is input, the first transistor connected to the first node and ground, the clock signal is input, and the period in which the clock signal is in the first phase is A second transistor for precharging the first node;
  Further, each receives a clock signal and a data signal, data is written when the clock signal is in the first phase, and data is held when the clock signal is in the opposite phase to the first phase. Two second level latches, two data input terminals for inputting the respective output signals of the two second level latches, two inverted signal input terminals for inputting the inverted signals of the respective output signals, and two An output terminal for inputting the clock signal, the output signals, and the inverted signals, and the two output terminals each outputting 0 during a period in which the clock signal is in the first phase; During a period in which the clock signal is opposite in phase to the first phase, one output terminal outputs a logical product of input signals from the two second level latches, and the other output terminal A second decoding circuit that outputs an exclusive OR of the input signals from the two second level latches, and an output signal of the second decoding circuit are input and connected to the second node and ground. A third transistor that receives the clock signal, and a fourth transistor that precharges the second node during a period in which the clock signal is in the first phase, each receiving a clock signal and a data signal Two third level latches in which data is written during a period in which the clock signal is in the first phase, and data is held in a period in which the clock signal is in a phase opposite to the first phase; Two data input terminals for inputting the respective output signals of the third level latch, two inverted signal input terminals for inputting the inverted signals of the respective output signals, and two An output terminal for inputting the clock signal, the output signals, and the inverted signals, and the two output terminals each outputting 0 during a period in which the clock signal is in the first phase; During a period in which the clock signal is in phase opposite to the first phase, one output terminal outputs a logical product of input signals from the two third level latches, and the other output terminal outputs the two second phases. A third decode circuit that outputs an exclusive OR of the input signals from the third level latches, and an output signal of the third decode circuit is input and connected to the first node and the second node. Consisting of a fifth transistor,
  The input of the first transistor and the input of the third transistor are signals for generating a carry of a carry chain of a Manchester carry adder, and the input of the fifth transistor is the signal This signal propagates the carry signal from the carry chain of the Manchester carry adder and outputs the carry signal to the upper digit.It is characterized by this.
[0032]
  the aboveComputing unitAccording to the data temporary storage device, the values of the two data signals are written at a timing when the clock signal changes from the period of the first phase to the period of the phase opposite to the first phase, and the clock signal is During the period opposite to the phase, one of the two data output terminals outputs a logical product of the two written values, and the other output terminal outputs an exclusive logical sum, and the clock signal During the first phase, both data output terminals can output 0As a result, the clock signal is turned off during the period of 0, which is necessary in the domino logic circuit represented by the carry chain of the conventional Manchester carry adder, and the precharge state of the precharge node is destroyed. N-Tr for avoiding stuttering can be eliminated, and the operation delay time of the Domino logic circuit can be improved.The
[0033]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0034]
(Embodiment 1)
FIG. 1 shows the configuration of a temporary data storage device according to the first embodiment of the present invention. In FIG. 1, reference numeral 101 denotes a tri-state inverter, which receives a clock signal CK as a control signal. The output is in a high impedance state when CK = 1, and the inverter operates when CK = 0.
[0035]
Reference numeral 103 denotes a tri-state inverter, which receives CK as a control signal. The output is in a high impedance state when CK = 0, and the inverter operates when CK = 1. Reference numeral 102 denotes an inverter.
[0036]
By connecting the tri-state inverter 101, the inverter 102, and the tri-state inverter 103 as shown in the figure, a level latch 108 is formed that writes data when CK = 0 and holds data when CK = 1. The level latch 108 corresponds to the level latch described in claim 1.
[0037]
Reference numeral 104 denotes a P-channel transistor (hereinafter referred to as P-Tr), and a clock signal CK is input to its gate. Reference numerals 105 and 106 denote N-channel transistors (hereinafter referred to as N-Tr). The output of the level latch 108 is input to the gate of the N-Tr 105, and the clock signal CK is input to the gate of the N-Tr 106. Reference numeral 107 denotes an inverter which, together with the P-Tr 104, N-Tr 105, and N-Tr 106, constitutes a decode circuit 109. The decode circuit 109 corresponds to the decode circuit described in claim 1.
[0038]
The operation of the temporary data storage device in the first embodiment will be described below. The level latch 108 outputs the value of the input terminal DIN from the inverter 102 during the period of CK = 0 (corresponding to the period of the first phase described in claim 1), and the period of CK = 1 (claim 1). In the period of the first phase and the opposite phase of the first phase, the value immediately before the change from CK = 0 to CK = 1 is output from the inverter 102.
[0039]
  Decode circuit109, the P-Tr 104 is turned on and the inverter 107 outputs 0 during the period of CK = 0, and the N-Tr 106 is turned on and the output of the inverter 102, that is, the output of the level latch 108 is output during the period of CK = 1. If 1, the N-Tr 105 is turned on, and the charge of the input gate of the inverter 107 is discharged through the N-Tr 105, 106 to become 0, so that the inverter 107 outputs 1 and the output of the inverter 102 That is, if the output of the level latch 108 is 0, the N-Tr 105 is turned off, and the charge at the input gate of the inverter 107 remains 1 without being discharged, so the inverter 107 outputs 0.
[0040]
That is, in the operation of the temporary data storage device according to the first embodiment of the present invention, during the period of the clock signal CK = 1, the DIN value at the timing of the rising edge of the clock signal CK is output from DOUT, and the clock signal CK = 0. During this period, 0 is output. FIG. 2 shows an operation timing chart thereof.
[0041]
  The data temporary storage device according to the first embodiment configured as described above includes the level latch 108 configured as described above and the configuration configured as described above.Decode circuit109 is arranged and connected as shown in FIG. 1, the DIN value at the timing of the rising edge of the clock signal CK is output from DOUT during the period of the clock signal CK = 1, and 0 during the period of the clock signal CK = 0. Can be output.
[0042]
  Level latch andDecode circuitMay have a configuration other than the circuit configuration described above.
[0043]
(Embodiment 2)
FIG. 3 shows a circuit of the data temporary storage device according to the second embodiment of the present invention. In FIG. 3, reference numeral 301 denotes a tri-state inverter, to which a clock signal CK is input as a control signal. When CK = 1, the output is in a high impedance state, and when CK = 0, the inverter operates. Reference numeral 303 denotes a tri-state inverter, which receives CK as a control signal. The output is in a high impedance state when CK = 0, and the inverter operates when CK = 1. 302 is an inverter.
[0044]
By connecting the tri-state inverter 301, the inverter 302, and the tri-state inverter 303 as shown in the figure, a level latch 317 is configured to write data when CK = 0 and hold data when CK = 1.
[0045]
A tri-state inverter 305 receives a clock signal CK as a control signal. When CK = 1, the output is in a high impedance state, and when CK = 0, the inverter operates. Reference numeral 307 denotes a tri-state inverter which receives CK as a control signal. The output is in a high impedance state when CK = 0, and the inverter operates when CK = 1. Reference numeral 306 denotes an inverter.
[0046]
By connecting the tri-state inverter 305, the inverter 306, and the tri-state inverter 307 as shown in the figure, a level latch 318 is formed which writes data when CK = 0 and holds data when CK = 1.
[0047]
  Level latch 317 and level latch 318 are claimed.7Corresponds to the two level latches described in 1).
[0048]
Reference numeral 309 denotes a P channel transistor (hereinafter referred to as P-Tr), which receives a clock signal CK at its gate. Reference numerals 310, 311 and 312 denote N-channel transistors (hereinafter referred to as N-Tr). The output of the level latch 317 is output to the N-Tr 310, the output of the level latch 318 is output to the N-Tr 311, and the clock signal is output to the N-Tr 312. CK is input to each gate.
[0049]
Reference numeral 313 denotes a P-Tr, and the clock signal CK is input to the gate. Reference numerals 314, 315, and 316 denote N-Tr. The output of the level latch 317 is input to the N-Tr 315, the output of the level latch 318 is input to the N-Tr 314, and the clock signal CK is input to the gate of the N-Tr 316. Is done.
[0050]
  Reference numerals 304 and 308 denote inverters, which together with the P-Trs 309 and 313, N-Trs 310, 311, 312, 312, 314, 315, and 316 constitute a decoding circuit 319. The decode circuit 319 is claimed7It corresponds to the decoding circuit described in 1.
[0051]
  The operation of the data temporary storage device in the second embodiment will be described below. The level latch 317 has a period of CK = 0, that is, the claim7In the period corresponding to the first phase described in the above, the value of the input terminal DIN1 is output from the inverter 302, and the period of CK = 1, that is,7In the period of the phase opposite to the first phase described in (1), the value immediately before the change from CK = 0 to CK = 1 is output from the inverter 302.
[0052]
Similarly to the level latch 317, the level latch 318 outputs the value of the input terminal DIN2 from the inverter 306 during the period CK = 0, and immediately before the change from CK = 0 to CK = 1 during the period CK = 1. The value is output from the inverter 306.
[0053]
  Decode circuitIn the period 319, CK = 0, the P-Tr 309 is turned on and the inverter 304 outputs 0, the P-Tr 313 is turned on and the inverter 308 outputs 0.
[0054]
During the period of CK = 1, if the N-Trs 312 and 316 are on, the output of the inverter 302, that is, the output of the level latch 317 is 1, and the output of the inverter 306, that is, the output of the level latch 318 is 1, Since the N-Tr 310 and Tr 311 are turned on and the charge of the input gate of the inverter 304 is discharged through the N-Tr 310, 311 and 312 to 0, the inverter 304 outputs 1 and the output of the inverter 304, that is, the level latch If the output of 317 or the output of the inverter 306, that is, the output of the level latch 318 is 0, the N-Tr 310 or N-Tr 311 is turned off, and the charge of the input gate of the inverter 304 remains 1 without being discharged. The inverter 304 outputs 0.
[0055]
On the other hand, if the output of the inverter 302, that is, the output of the level latch 317 or the output of the inverter 306, that is, the output of the level latch 318 is 1, N-Tr 314 or N-Tr 315 is turned on, and the charge of the input gate of the inverter 308 is N -Tr 314 or N-Tr 315 and N-Tr 316 are discharged and become 0, so that the inverter 308 outputs 1, the output of the inverter 302, that is, the output of the level latch 317 is 0, and the inverter 306 If the output, that is, the output of the level latch 318 is 0, the N-Tr 314 and 315 are turned off, and the charge of the input gate of the inverter 308 remains 1 without being discharged, so the inverter 308 outputs 0.
[0056]
That is, the operation of the data temporary storage device according to the second embodiment of the present invention is such that, during the period of the clock signal CK = 1, the logical product signal of the DIN1 value and the DIN2 value at the rising edge timing of the clock signal CK is And outputs a logical sum signal of DIN1 value and DIN2 value at the timing of the rising edge of the clock signal CK from POUT, and outputs 0 from GOUT and 0 from POUT during the period of the clock signal CK = 0. Become.
[0057]
FIG. 4 shows an operation timing chart of the data temporary storage device according to the second embodiment.
[0058]
  The data temporary storage device according to the second embodiment configured as described above includes the level latch 317 and the level latch 318 configured as described above.Decode circuitBy arranging and connecting 319 as shown in FIG. 3, during the period of the clock signal CK = 1, the logical product of the values of DIN1 and DIN2 at the timing of the rising edge of the clock signal CK is output from GOUT, and the logical sum is output from POUT. In the period when the clock signal CK = 0, both GOUT and POUT can be output as 0.
[0059]
  The level latch 317, the level latch 318,Decode circuit319 may have a configuration other than the circuit configuration described above. In the second embodiment, the case where the number of level latches is two is shown as an example, but the number of level latches may be other than two. Further, although the configuration in which the logical product signal and the logical sum signal of the input terminal are output during the period of CK = 1 has been described, a configuration in which a logical operation result other than this is output may be employed.
[0060]
(Embodiment 3)
FIG. 5 shows a circuit of the temporary data storage device according to the third embodiment of the present invention. In FIG. 5, reference numeral 501 denotes a tri-state inverter which receives a clock signal CK as a control signal. The output is in a high impedance state when CK = 1, and the inverter operates when CK = 0. Reference numeral 503 denotes a tri-state inverter, to which CK is input as a control signal. The output is in a high impedance state when CK = 0, and the inverter operates when CK = 1. Reference numeral 502 denotes an inverter.
[0061]
By connecting the tri-state inverter 501, the inverter 502 and the tri-state inverter 503 as shown in the figure, a level latch 519 is formed which writes data when CK = 0 and holds data when CK = 1.
[0062]
A tri-state inverter 505 receives a clock signal CK as a control signal. When CK = 1, the output is in a high impedance state, and when CK = 0, the inverter operates. Reference numeral 507 denotes a tri-state inverter, to which CK is input as a control signal. The output is in a high impedance state when CK = 0, and the inverter operates when CK = 1. Reference numeral 506 denotes an inverter.
[0063]
By connecting the tri-state inverter 505, the inverter 506, and the tri-state inverter 507 as shown in the figure, a level latch 520 is formed that writes data when CK = 0 and holds data when CK = 1.
[0064]
  Level latch 519 and level latch 520 are claimed.10Corresponds to the two level latches described in 1).
[0065]
Reference numeral 509 denotes a P-channel transistor (hereinafter referred to as P-Tr), which receives a clock signal CK at its gate. Reference numerals 510, 511 and 512 denote N-channel transistors (hereinafter referred to as N-Tr). The output of the level latch 519 is output to the N-Tr 510, the output of the level latch 520 is output to the N-Tr 511, and the clock signal is output to the N-Tr 512. CK is input to each gate.
[0066]
Reference numeral 513 denotes a P-Tr, and the clock signal CK is input to the gate. Reference numerals 514, 515, 516, 517, and 518 denote N-Tr, and the N-Tr 514 has an output of the level latch 519, and the N-Tr 515 has an output of the output of the tri-state inverter 505, that is, an inverted signal of the output of the level latch 520. , N-Tr 516 receives the output of level latch 520, N-Tr 517 receives the output of tri-state inverter 501, that is, the inverted signal of level latch 519, and N-Tr 518 receives the clock signal CK. .
[0067]
  Reference numerals 504 and 508 denote inverters, which together with P-Trs 509 and 513, N-Trs 510, 511, 512, 514, 515, 516, 517, and 518 constitute a decoding circuit 521. The decode circuit 521 is claimed10It corresponds to the decoding circuit described in 1.
[0068]
  The operation of the data temporary storage device in the third embodiment will be described below. The level latch 519 has a period of CK = 0, that is, the claim10In the period corresponding to the first phase described in the above, the value of the input terminal DIN1 is output from the inverter 502, and the period of CK = 1, that is,10In the period of the phase opposite to the first phase described in (1), the value immediately before the change from CK = 0 to CK = 1 is output from the inverter 502.
[0069]
Similarly to the level latch 519, the level latch 520 outputs the value of the input terminal DIN2 from the inverter 506 during the period CK = 0, and immediately before the change from CK = 0 to CK = 1 during the period CK = 1. The value is output from the inverter 506.
[0070]
  Decode circuitIn the period 521, CK = 0, the P-Tr 509 is turned on and the inverter 504 outputs 0, the P-Tr 513 is turned on and the inverter 508 outputs 0.
[0071]
During the period of CK = 1, if the N-Tr 512, 518 is on, the output of the inverter 502, that is, the output of the level latch 519 is 1, and the output of the inverter 506, that is, the output of the level latch 520 is 1, N-Tr 510 and 511 are turned on, and the charge of the input gate of inverter 504 is discharged through N-Tr 510, 511 and 512 to become 0, so that inverter 504 outputs 1 and the output of inverter 504, that is, the level latch If the output of 519 or the output of the inverter 506, that is, the output of the level latch 520 is 0, the N-Tr 510 or N-Tr 511 is turned off, and the charge of the input gate of the inverter 504 remains 1 without being discharged. The inverter 504 outputs 0.
[0072]
On the other hand, when the output of the inverter 502, ie, the output of the level latch 519 is 1, and the output of the tri-state inverter 505, ie, the inverted signal of the output of the level latch 520, is 1, or the output of the inverter 506, ie, the level latch When the output of 520 is 1 and the output of the output of the tri-state inverter 501, that is, the inverted signal of the output of the level latch 520 is 1, N-Tr 514 515 or N-Tr 516 517 is turned on and the inverter 508 Is discharged through the N-Tr 514, 515, 518 or the N-Tr 516, 517, 518 and becomes 0, so the inverter 508 outputs 1. When the output of the inverter 502, that is, the output of the level latch 519 is 0, or when the inverted signal of the output of the tri-state inverter 505, that is, the output of the level latch 520 is 0, and when the output of the inverter 506, that is, the output of the level latch 520 is 0 Alternatively, if the inverted signal of the output of the tri-state inverter 501, that is, the output of the level latch 519 is 0, the path from the input gate of the inverter 508 to the ground is turned off, so that the charge of the input gate of the inverter 508 is discharged. Instead, it remains 1 and therefore inverter 508 outputs 0.
[0073]
That is, the operation of the data temporary storage device according to the third embodiment of the present invention is such that, during the period of the clock signal CK = 1, the logical product signal of the DIN1 value and the DIN2 value at the rising edge timing of the clock signal CK is The exclusive OR signal of the DIN1 value and DIN2 value at the timing of the rising edge of the clock signal CK is output from POUT, and 0 is output from GOUT and 0 from POUT during the period of the clock signal CK = 0. It will be.
[0074]
FIG. 6 shows an operation timing chart of the data temporary storage device according to the third embodiment.
[0075]
  The data temporary storage device according to the third embodiment configured as described above includes the level latch 519 and the level latch 520 configured as described above.Decode circuitBy arranging and connecting 521 as shown in FIG. 5, during the period of the clock signal CK = 1, the logical product of the values of DIN1 and DIN2 at the timing of the rising edge of the clock signal CK is output from GOUT, and the exclusive OR is calculated. During the period when the clock signal CK = 0 is output from POUT, both GOUT and POUT can output 0.
[0076]
  The level latch 519, the level latch 520,Decode circuit521 may have a configuration other than the circuit configuration described above. In the third embodiment, the case where the number of level latches is two is shown as an example, but the number of level latches may be other than two. Further, although the configuration in which the logical product signal and the exclusive logical sum signal of the input terminal are output during the period of CK = 1 has been described, a configuration in which a logical operation result other than this is output may be used.
[0077]
  In general,Decode circuitThe number of data output terminals need not be the same as the number of level latches. For example, two level latches are provided, and the decoding circuit has three data output terminals: a circuit for extracting the logical product and logical sum in FIG. 3 and a circuit for extracting the exclusive logical sum in FIG.Decode circuitIt is also possible to configure.
[0078]
【The invention's effect】
  As explained above, the present inventionHave in the calculatorData temporary storage is
  (1) A level latch in which a clock signal and a data signal are input, data is written during a period in which the clock signal is in the first phase, and data is held in a period in which the clock signal is in a phase opposite to the first phase. The clock signal and the output signal of the level latch are input, 0 is output during the period in which the clock signal is in the first phase, and the input signal from the level latch is in the period in which the clock signal is in the opposite phase to the first phase. And a decoding circuit that outputs the value of
  (2) A plurality of levels each of which receives a clock signal and a data signal, writes data when the clock signal is in the first phase, and holds data when the clock signal is in the opposite phase to the first phase. A period having the same number of latches and data input terminals and any number of output terminals as the number of level latches, and inputting the clock signal and each output signal of the plurality of level latches, and the clock signal is in the first phase Each output terminal outputs 0 respectively, and during the period when the clock signal is in the opposite phase to the first phase, each output terminal outputs a different logical operation result of each input signal value from the plurality of level latches. And a decoding circuit for outputting.
[0079]
  ThisThe computing unit of the present invention isIn the conventional technology, the clock signal is turned off during the period of 0, which is necessary in the domino logic circuit represented by the carry chain of the Manchester carry adder, and the precharge state of the precharge node is destroyed. This eliminates the N-Tr that is not present, and improves the operation delay time of the domino logic circuit.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a data temporary storage device according to a first embodiment of the present invention.
FIG. 2 is an operation timing chart of the temporary data storage device according to the first embodiment of the present invention.
FIG. 3 is a circuit diagram of a data temporary storage device according to a second embodiment of the present invention.
FIG. 4 is an operation timing chart of the temporary data storage device according to the second embodiment of the present invention.
FIG. 5 is a circuit diagram of a temporary data storage device according to a third embodiment of the present invention.
FIG. 6 is an operation timing chart of the temporary data storage device according to the third embodiment of the present invention.
FIG. 7 is a circuit diagram of an example of a carry chain unit of a Manchester carry adder, which is a kind of conventional domino logic circuit.
FIG. 8 is a circuit diagram of a flip-flop, which is an example of a conventional temporary data storage device.
FIG. 9 is an operation timing chart of a flip-flop as an example of a conventional temporary data storage device.
FIG. 10 is a circuit diagram of an example of a conventional AND circuit.
FIG. 11 is a circuit diagram of an example of a conventional exclusive OR circuit;
[Explanation of symbols]
101, 103, 301, 303, 305, 307, 501, 503, 505, 507 Tristate inverter
102,107,302,304,306,308,502,504,506,508 Inverter
104, 309, 313, 509, 513 P-channel transistor
105, 106, 310, 311, 312, 314, 315, 316, 510, 511, 512, 514, 515, 516, 517, 518 N-channel transistors
108, 317, 318, 519, 520 Level latch
109,319,521Decode circuit

Claims (12)

A first level latch that receives a clock signal and a data signal, writes data while the clock signal is in the first phase, and holds data when the clock signal is in a phase opposite to the first phase. When,
Inputting the clock signal and the output signal of the first level latch, outputting 0 when the clock signal is in the first phase, and period when the clock signal is opposite in phase to the first phase Is a first decode circuit that outputs the value of the input signal from the first level latch ;
Input an output signal of the first decoding circuit, a first transistor connected to the first node and ground; and
An arithmetic unit comprising: a second transistor that inputs the clock signal and precharges the first node during a period in which the clock signal is in a first phase . The arithmetic unit according to claim 1, wherein
A second level latch that receives a clock signal and a data signal, writes data when the clock signal is in the first phase, and holds data when the clock signal is in a phase opposite to the first phase. When,
Before Symbol clock signal and inputs the output signal of said second level latch period the clock signal is in the first phase outputs 0, the clock signal is the first phase and antiphase a period of time and a second decoding circuit for outputting a value of the input signal from the second level latch,
Input the output signal of the second decoding circuit, a third transistor connected to the second node and ground; and
A fourth transistor that inputs the clock signal and precharges the second node during a period in which the clock signal is in a first phase;
A third level latch that receives a clock signal and a data signal, writes data when the clock signal is in the first phase, and holds data when the clock signal is in the opposite phase to the first phase. When,
Inputting the clock signal and the output signal of the third level latch, outputting 0 when the clock signal is in the first phase, and period when the clock signal is in phase opposite to the first phase Is a third decoding circuit that outputs the value of the input signal from the third level latch;
An arithmetic unit comprising an output signal of the third decoding circuit and a fifth transistor connected to the first node and the second node . The arithmetic unit according to claim 1, wherein:
The input of the first transistor and the input of the third transistor are signals for generating a carry of a carry chain of a Manchester carry adder,
The input of the fifth transistor is a signal for propagating the carry signal of the carry chain portion of the Manchester carry adder,
An arithmetic unit that outputs a carry signal to the upper digit . Each receives a clock signal and a data signal, data writing is performed during a period in which the clock signal is in the first phase, and data holding is performed in a period in which the clock signal is in the opposite phase to the first phase . A level latch,
The first has a first level the plurality of output terminals the number of the same number as the data input terminal and any of the latches, and inputs each output signal of said clock signal and said plurality of first level latch, the clock signal period but is the first phase, the respective output terminals outputs a 0, respectively, the period the clock signal is in the first phase and opposite phase, the first output terminals of the plurality respectively respectively first decoding circuit for outputting different logic operation result of the value of each input signal from the level latch,
Input an output signal of the first decoding circuit, a first transistor connected to the first node and ground; and
An arithmetic unit comprising: a second transistor that inputs the clock signal and precharges the first node during a period in which the clock signal is in a first phase . The arithmetic unit according to claim 4, wherein
Each receives a clock signal and a data signal, data writing is performed during a period in which the clock signal is in the first phase, and data holding is performed in a period in which the clock signal is in the opposite phase to the first phase. A second level latch,
It has the same number of data input terminals and any number of output terminals as the number of the second level latches, inputs the clock signal and each output signal of the plurality of second level latches, and the clock signal In the period that is the first phase, each of the output terminals outputs 0, and in the period in which the clock signal is in the opposite phase to the first phase, each of the output terminals has the plurality of second phases. A second decoding circuit for outputting a different logical operation result of each input signal value from the level latch;
Input the output signal of the second decoding circuit, a third transistor connected to the second node and ground; and
A fourth transistor that inputs the clock signal and precharges the second node during a period in which the clock signal is in a first phase;
Each receives a clock signal and a data signal, data writing is performed during a period in which the clock signal is in the first phase, and data holding is performed in a period in which the clock signal is in the opposite phase to the first phase. Three level latches,
It has the same number of data input terminals and any number of output terminals as the number of the third level latches, inputs the clock signal and each output signal of the plurality of third level latches, and the clock signal In the period that is the first phase, each of the output terminals outputs 0, and in the period in which the clock signal is in the opposite phase to the first phase, each of the output terminals is each of the plurality of third phases. A third decoding circuit for outputting a different logical operation result of each input signal value from the level latch;
A fifth transistor that receives an output signal of the third decoding circuit and is connected to the first node and the second node;
An arithmetic unit comprising: The arithmetic unit according to claim 4 or 5, wherein
The input of the first transistor and the input of the third transistor are signals for generating a carry of a carry chain of a Manchester carry adder,
The input of the fifth transistor is a signal for propagating the carry signal of the carry chain portion of the Manchester carry adder,
An arithmetic unit that outputs a carry signal to the upper digit. Each receives a clock signal and a data signal, data is written when the clock signal is in the first phase, and data is held when the clock signal is in the opposite phase to the first phase. A level latch,
Two data input terminals for inputting the output signals of the two first level latches and two output terminals, respectively, for inputting the clock signal and the output signals of the two first level latches In the period in which the clock signal is in the first phase, the two output terminals each output 0, and in the period in which the clock signal is in the opposite phase to the first phase, A first decoding circuit that outputs a logical product of input signals from two first level latches, and whose other output terminal outputs a logical sum of input signals from the two first level latches;
Input an output signal of the first decoding circuit, a first transistor connected to the first node and ground; and
The clock signal is input, and the period in which the clock signal is in the first phase is the first node. A second transistor that precharges the node and
An arithmetic unit comprising: The arithmetic unit according to claim 7, wherein
Each receives a clock signal and a data signal, data is written when the clock signal is in the first phase, and data is held when the clock signal is in the opposite phase to the first phase. A second level latch,
Two data input terminals for inputting the output signals of the two second level latches and two output terminals, respectively, and the clock signal and the output signals of the two second level latches are inputted. In the period in which the clock signal is in the first phase, the two output terminals each output 0, and in the period in which the clock signal is in the opposite phase to the first phase, A second decoding circuit that outputs a logical product of the input signals from the two second level latches, and whose other output terminal outputs a logical sum of the input signals from the two second level latches;
Input the output signal of the second decoding circuit, a third transistor connected to the second node and ground; and
A fourth transistor that inputs the clock signal and precharges the second node during a period in which the clock signal is in a first phase;
Each receives a clock signal and a data signal, data is written when the clock signal is in the first phase, and data is held when the clock signal is in the opposite phase to the first phase. Three level latches,
Two data input terminals and two output terminals for inputting the output signals of the two third level latches, respectively, and receiving the clock signal and the output signals of the two third level latches In the period in which the clock signal is in the first phase, the two output terminals each output 0, and in the period in which the clock signal is in the opposite phase to the first phase, A third decoding circuit that outputs a logical product of the input signals from the two third level latches, and whose other output terminal outputs a logical sum of the input signals from the two third level latches;
A fifth transistor that receives an output signal of the third decoding circuit and is connected to the first node and the second node;
An arithmetic unit comprising: The arithmetic unit according to claim 7 or 8, wherein
The input of the first transistor and the input of the third transistor are signals for generating a carry of a carry chain of a Manchester carry adder,
The input of the fifth transistor is a signal for propagating the carry signal of the carry chain portion of the Manchester carry adder,
An arithmetic unit that outputs a carry signal to the upper digit. Each receives a clock signal and a data signal, data is written when the clock signal is in the first phase, and data is held when the clock signal is in the opposite phase to the first phase. A level latch,
The clock signal having two data input terminals for inputting the output signals of the two first level latches, two inverted signal input terminals for inputting inverted signals of the output signals, and two output terminals, respectively; Signal, each output signal, and each inverted signal are input, and during the period in which the clock signal is in the first phase, the two output terminals each output 0, and the clock signal is in the first phase. During the period opposite to the phase, one output terminal outputs a logical product of the input signals from the two first level latches, and the other output terminal inputs the input signals from the two first level latches. A first decoding circuit that outputs an exclusive OR of
Input an output signal of the first decoding circuit, a first transistor connected to the first node and ground; and
A second transistor that inputs the clock signal and precharges the first node during a period in which the clock signal is in a first phase;
An arithmetic unit comprising: The arithmetic unit according to claim 10, wherein
Each receives a clock signal and a data signal, data is written when the clock signal is in the first phase, and data is held when the clock signal is in the opposite phase to the first phase. A second level latch,
The clock signal having two data input terminals for inputting the output signals of the two second level latches, two inverted signal input terminals for inputting inverted signals of the output signals, and two output terminals, respectively. Signal, each output signal, and each inverted signal are input, and during the period in which the clock signal is in the first phase, the two output terminals each output 0, and the clock signal is in the first phase. During a period opposite to the phase, one output terminal outputs a logical product of the input signals from the two second level latches, and the other output terminal inputs the input signals from the two second level latches. A second decoding circuit that outputs an exclusive OR of
Input the output signal of the second decoding circuit, a third transistor connected to the second node and ground; and
A fourth transistor that inputs the clock signal and precharges the second node during a period in which the clock signal is in a first phase;
Each receives a clock signal and a data signal, data is written when the clock signal is in the first phase, and data is held when the clock signal is in the opposite phase to the first phase. Three level latches,
The clock signal having two data input terminals for inputting the output signals of the two third level latches, two inverted signal input terminals for inputting inverted signals of the output signals, and two output terminals, respectively. Signal, each output signal, and each inverted signal are input, and during the period in which the clock signal is in the first phase, the two output terminals each output 0, and the clock signal is in the first phase. During a period that is opposite to the phase, one output terminal outputs a logical product of the input signals from the two third level latches, and the other output terminal inputs an input signal from the two third level latches. A third decoding circuit that outputs an exclusive OR of
A fifth transistor that receives an output signal of the third decoding circuit and is connected to the first node and the second node;
An arithmetic unit comprising: The arithmetic unit according to claim 10 or 11, comprising:
The input of the first transistor and the input of the third transistor are signals for generating a carry of a carry chain of a Manchester carry adder,
The input of the fifth transistor is a signal for propagating the carry signal of the carry chain portion of the Manchester carry adder,
An arithmetic unit that outputs a carry signal to the upper digit.

Images