JP2000165247A - Data backup storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance an operation delay time of a domino logic circuit by excluding an N channel transistor(TR) that has been required for a domino logic circuit represented as a carry chain for a Manchester carry adder in a conventional technology and is turned off when a clock signal is zero and used for avoiding destruction of a pre-charge state of a pre-charge node. SOLUTION: A data backup storage is configured with a level latch 108 that receives a clock signal CK, a data signal DIN and transits to a data write state when the clock CK is zero and reaches a data storage state when the clock CK is logical 1 and with a decode circuit 109 that receives the clock CK and an output signal from the level latch 108, outputs zero when the clock CK is zero and outputs an input signal from the level latch 108 when the clock CK is logical 1. Thus, the data backup storage outputs zero when the CK is zero or outputs a value DIN in a timing of a leading edge of the clock CK when the clock CK is logical 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a temporary data storage device such as a latch circuit and a flip-flop circuit which is mainly realized by a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent years, the development of semiconductor integrated circuits has been remarkable, and the development of higher performance, such as higher integration, higher speed operation and lower power consumption, has been promoted. From the viewpoint of developing circuits that operate at higher speeds, various types of circuits have been devised and studied.

At present, almost all semiconductor integrated circuits that operate at high speed have a clock synchronous circuit configuration that operates in synchronization with a clock signal. For example, they operate in synchronization with a clock mounted on a microcomputer or the like. A data processing device or the like uses a logic operation circuit as a flip-flop (hereinafter referred to as F.F.
F. ), And the like, is sandwiched between data temporary storage devices that write / hold data in synchronization with a clock signal, and a clock signal is supplied to the data temporary storage device to operate in synchronization with the clock signal. Is widely used.

In order to increase the operation speed of the data processing device having such a configuration, the operation time of the logical operation circuit is shortened, and the operation in the logical circuit is completed within a shorter clock cycle. This is realized by increasing the frequency of the clock signal supplied to the temporary storage device.

[0005] In order to shorten the operation time of the logical operation circuit to increase the operating frequency, there is also known a method using a logic circuit having a circuit configuration such as a domino logic circuit which performs dynamic operation instead of a static circuit configuration. ing.

An example of such a prior art is the Manchester carry adder described on page 281 of "Principles of CMOS VLSI Design-From a System Viewpoint" published by Maruzen Co., Ltd. The Manchester carry adder is a kind of domino logic circuit and is a circuit that propagates a carry signal at a high speed by adopting a circuit configuration for performing a dynamic operation.

Hereinafter, the above-mentioned Manchester carry adder will be described with reference to the drawings. FIG. 7 is a circuit diagram showing an example of a carry chain unit of a Manchester carry adder which is a kind of a conventional domino logic circuit.

In FIG. 7, reference numerals 1015 to 1019 denote P-channel transistors (hereinafter, P-Tr) whose gates are connected to a clock signal CK, which are turned on when the clock signal CK is 0, and the nodes X0 to X4 are pre-connected. Charged. 1010 to 1014 have a gate whose clock signal CK
N-channel transistor (hereinafter referred to as NT)
r), and turns on when the clock signal CK is 1.
Reference numerals 1001 to 1009 denote N-Trs, each of which is turned on when the gate signal is 1.

The carry chain portion of the Manchester carry adder includes 4-bit carry propagation signals (propagation signals) P1 to P4, 4-bit carry generation signals (generation signals) G1 to G4, and lower bits. Using the carry signal C0 from the digit, the carry signal C4 to the upper digit is used.
Is a circuit that generates

[0010] The operation is as follows.
, P-Trs 1015 to 1019 are turned on,
The nodes X0 to X4 are precharged. Next, during the period when the clock signal CK is 1, the N-Trs 1010 to 101
4 is turned on, the N-Trs 1001 to 1009 are turned on,
Due to the OFF state, of the nodes X0 to X4, a node whose path to the ground is open is discharged, and a node whose path to the ground is not open is not discharged. At this time, if the node of X4 is discharged,
The carry signal C4 for the upper digit becomes 1 and becomes 0 when the signal is not discharged.

For example, the first bit carry generation signal G1
And the carry propagation signals P2 to P4 of the second to fourth bits
Is 1, when the clock signal CK becomes 1, the node X4 becomes N-Tr 1004, 1003, 1002, 1
It is discharged through the path of 006, 1011. When X4 becomes 0, the carry signal C4 becomes 1, and a carry signal for the upper digit is generated. Similarly, when the clock signal CK becomes 1, the input signals P1 to P4, G1
C4 is determined to be 0 or 1 depending on the combination of ＧG4, C0.

In this circuit, when the carry signal C4 to the upper digit changes from 0 to 1 and the delay time is the longest, the carry signal C0 from the lower digit and the first to fourth bits When only the carry propagation signals P1 to P4 of the bit are 1 and the other carry generation signals G1 to G4 are 0, and when CK changes from 0 to 1 in this state, the precharge is performed. Node X4 is N-Tr 1004
In this case, six transistors 1003, 1002, 1001, 1005, and 1010 are discharged to ground through a path connected in series.

As described above, when the circuit of the carry chain of the above-mentioned conventional Manchester carry adder is used, the 4-bit propagation signals P1 to P4 and the 4-bit generation signals G1 to G4, Raising signal C
When using 0 to generate a carry signal C4 to the upper digit,
The worst delay time is determined by six N-Trs 10 connected in series.
04,1003,1002,1001,1005,10
10 to discharge the node X4, and the P-Tr
This is the delay time until the inverted signal of the node X4 is created by the inverter configured by the inverter 1021 and the N-Tr 1020.

Further, regarding a data temporary storage device which is arranged before and after the above-described domino logic type dynamic circuit and operates in synchronization with a clock signal, data is fetched at the rising or falling edge of the clock signal. F. that data is retained for other periods. F. Circuits are widely used.

Hereinafter, the above F.S.
F. The circuit will be described. FIG. F. F. A type in which a level latch, which is a type of a circuit, is connected in series and takes in data at the rising edge of a clock.
F. 2 shows a circuit.

In FIG. 8, reference numeral 1101 denotes a clock signal C.
A level latch 1102 is for data writing when K is 0, and holds data when it is 1, and a level latch 1102 is for data writing when the clock signal CK is 1 and holds data when it is 0. The output is input to the level latch 1102.

For this reason, while the clock signal CK is 0, the value of DIN is written in the level latch 1101.
Since the level latch 1102 is in the data holding period, the output of the level latch 1102 does not change.

When the clock signal CK changes from 0 to 1 (at the rising edge), the value of DIN immediately before the rising edge of the clock signal CK is the level latch 1101.
And the output of the level latch 1101 is written and output to the level latch 1102 immediately after the rising edge of CK.

During the period when the clock signal CK is 1, the level latch 1101 is in the data holding period, so that the input data of the level latch 1102 does not change, so that the output of the level latch 1102 does not change. Also, the clock signal CK
When the clock signal CK changes from 1 to 0 (at the time of the falling edge), the level latch 110 is turned on in the same manner as during the period when the clock signal CK is 1.
The output of 2 does not change.

In order to perform such an operation, the operation shown in FIG.
F. Is the timing of the rising edge of CK and DIN
F. that data is written and data is retained during other periods. F. Perform circuit operation. FIG. F. 4 shows an operation timing chart of the circuit.

In addition, the conventional F.S. F. From the addend and the augend stored in the circuit, the carry generation signal of each bit, which is the input signal of the carry chain unit of the above-mentioned conventional Manchester carry adder, and the carry propagation signal of each bit are calculated. In order to generate the bits, an adder and an addend of each bit and an exclusive-OR circuit of the addend and the addend of each bit are created. FIG. 10 shows an example of a conventional AND circuit.
FIG. 11 shows an example of an exclusive OR circuit.

[0022]

However, the conventional F.I. F. The carry generation signal for each bit and the carry propagation signal for each bit are input to the addend and the augend stored in the above using the AND circuit and the exclusive OR circuit. Considering the operation of the carry chain of the Manchester carry adder having the above configuration,
In FIG. 7, the nodes X0 to X4 are precharged during the period when the clock signal CK is 0. However, if the discharge path to the ground is connected during this period, the precharge state is destroyed. , The N-Trs 1010 to 101 that are turned off when the clock signal CK is 0
4 had to be placed in the position of FIG.

For this reason, a path for discharging the node X4 which is an inverted signal of the carry signal to the upper digit must pass through any one of the N-Trs 1010 to 1014. In the path of the slowest operation described above, five signals P1 to P
4. In addition to the five N-Trs having C0 as an input, it is necessary to pass through a sixth N-Tr 1010 having CK as an input, and the worst operation time is essentially five N-Trs required. There is a problem that the delay time is equal to the delay time passing six N-Trs, which is one more than the delay time passing.

Accordingly, the present invention has been made in view of the above problems, and has been required in a domino logic circuit represented by a carry chain of a Manchester carry adder having the above-described structure. It is an object of the present invention to provide a data temporary storage device in which an N-Tr for preventing the precharge state of a precharge node from being turned off and destroying the precharge node is eliminated, and an operation delay time of a domino logic circuit is improved. .

[0025]

According to a first aspect of the present invention, there is provided a data temporary storage device according to the first aspect of the present invention, wherein a clock signal and a data signal are input, and a period in which the clock signal is in a first phase. During data writing, the clock signal is in a phase opposite to the first phase, and a level latch for holding data, the clock signal and the output signal of the level latch are input, and the clock signal is the first signal. And a decoding circuit for outputting a value of an input signal from the level latch during a period when the clock signal is in a phase opposite to the first phase. is there.

According to the data temporary storage device of this configuration,
At the timing when the clock signal transitions from the period of the first phase to the period of the opposite phase to the first phase, the value of the data signal is written, and the period during which the clock signal is in the opposite phase to the first phase is written. The output value is output from the data output terminal, and 0 can be output while the clock signal is in the first phase.

According to a second aspect of the present invention, in the data temporary storage device, each of which receives a clock signal and a data signal, writes data while the clock signal is in the first phase, During the period in which the phase is opposite to the first phase, a plurality of level latches for holding data, the same number of data input terminals as the number of the level latches and an arbitrary plurality of output terminals, the clock signal and the Each output signal of a plurality of level latches is input, and during the period in which the clock signal is in the first phase, each of the output terminals outputs 0, and the clock signal has an opposite phase to the first phase. During this period, each of the output terminals includes a decode circuit that outputs a different logical operation result of the value of each of the input signals from the plurality of level latches. To.

According to the data temporary storage device having the above configuration,
At the timing when the clock signal transitions from the period of the first phase to the period of the opposite phase to the first phase, the values of the plurality of data signals are written, and the period when the clock signal is in the opposite phase to the first phase is Different logical operation results of a plurality of written values are respectively output from a plurality of arbitrary data output terminals, and all the plurality of data output terminals output 0 during a period when the clock signal is in the first phase. Can be.

Further, as a specific configuration, in the data temporary storage device according to the third aspect of the present invention, each of the temporary data storage devices receives a clock signal and a data signal, and outputs data during a period when the clock signal is in the first phase. During the period when the clock signal is in the opposite phase to the first phase, two level latches for holding data, two data input terminals for inputting respective output signals of the two level latches and two Having an output terminal, inputting the clock signal and each output signal of the two level latches, and during the period in which the clock signal is in the first phase, the two output terminals each output 0; During a period in which the clock signal is out of phase with the first phase, one output terminal is connected to the second phase.
And a decode circuit for outputting the logical product of the input signals from the two level latches and outputting the logical sum of the input signals from the two level latches.

According to the data temporary storage device having the above configuration,
At the timing when the clock signal changes from the period of the first phase to the period of the opposite phase to the first phase, the values of the two data signals are written, and the period when the clock signal is in the opposite phase to the first phase is One output terminal of the two data output terminals outputs the logical product of the two written values and the other output terminal outputs the logical sum, and during the period in which the clock signal is in the first phase, two output terminals are output. Each of the data output terminals can output 0.

Further, in the data temporary storage device according to the present invention, each of them receives a clock signal and a data signal, writes data during a period in which the clock signal is in the first phase, and outputs the data signal in response to the clock signal. During a period opposite to one phase, two level latches for holding data, two data input terminals for inputting respective output signals of the two level latches, and an inverted signal of each output signal are input. It has two inverted signal input terminals and two output terminals, and inputs the clock signal, each of the output signals and each of the inverted signals, and the period in which the clock signal is in the first phase is the two phases. During a period in which the output terminals output 0 and the clock signal is in the opposite phase to the first phase, one output terminal outputs the logic of the input signal from the two level latches. Outputs the product, in which the other output terminal, characterized by comprising a decoding circuit for outputting an exclusive logical sum of the input signals from the two level latch.

According to the data temporary storage device having the above configuration,
At the timing when the clock signal changes from the period of the first phase to the period of the opposite phase to the first phase, the values of the two data signals are written, and the period when the clock signal is in the opposite phase to the first phase is One output terminal of the two data output terminals outputs the logical product of the two written values and the other output terminal outputs the exclusive OR, and during the period when the clock signal is in the first phase, Both of the two data output terminals can output 0.

[0033]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) FIG. 1 shows the configuration of a temporary data storage device according to Embodiment 1 of the present invention. In FIG. 1, reference numeral 101 denotes a tri-state inverter, which receives a clock signal CK as a control signal, outputs a high impedance state when CK = 1, and performs an inverter operation when CK = 0.

Reference numeral 103 denotes a tri-state inverter. CK is input as a control signal. When CK = 0, the output is in a high impedance state, and when CK = 1, the inverter operates. 102 is an inverter.

By connecting the tri-state inverter 101, the inverter 102 and the tri-state inverter 103 as shown in the figure, data is written when CK = 0, and the level latch 10 which holds data when CK = 1.
8. This level latch 108 corresponds to the level latch according to the first aspect.

Reference numeral 104 denotes a P-channel transistor (hereinafter, P-Tr) to which a clock signal CK is input. Reference numerals 105 and 106 denote N-channel transistors (hereinafter referred to as N-Tr). The gate of the N-Tr 105 receives the output of the level latch 108 and the N-Tr 10
The clock signal CK is input to each of the gates 6. 107 is an inverter, P-Tr 104, N
-Decoding circuit 1 together with -Tr105 and N-Tr106
09. This decoding circuit 109 corresponds to the decoding circuit described in claim 1.

The operation of the temporary data storage device according to the first embodiment will be described below. Level latch 108
During the period of CK = 0 (corresponding to the period of the first phase described in claim 1), the value of the input terminal DIN is
2, and during a period of CK = 1 (a period of a phase opposite to the first phase according to claim 1), a value immediately before the change from CK = 0 to CK = 1 is output from the inverter 102.

The decoder 109 sets P during the period of CK = 0.
-Tr 104 is turned on, the inverter 107 outputs 0, and during the period of CK = 1, the N-Tr 106 is turned on and the output of the inverter 102, that is, the level latch 108
Is 1, the N-Tr 105 is turned on,
The charge at the input gate of the inverter 107 is N-Tr10
5 and 106, the discharge is made 0, and the inverter 107 outputs 1 and the inverter 102 outputs
, The output of the level latch 108 is 0, the N-Tr 105 is turned off, and the charge at the input gate of the inverter 107 remains at 1 without being discharged, so the inverter 107 outputs 0.

That is, the operation of the data temporary storage device according to the first embodiment of the present invention is as follows. During the period of clock signal CK = 1, the value of DIN at the timing of the rising edge of clock signal CK is output from DOUT. During the period of CK = 0, 0 is output. FIG.
This is an operation timing chart.

In the data temporary storage device according to the first embodiment configured as described above, the level latch 108 having the above configuration and the decoder 109 having the above configuration are arranged and connected as shown in FIG. During the period of 1, the value of DIN at the timing of the rising edge of the clock signal CK is output from DOUT, and the clock signal CK is output.
In the period of = 0, 0 can be output.

The level latch and the decoder may have a configuration other than the above-described circuit configuration.

(Embodiment 2) FIG. 3 shows a circuit of a temporary data storage device according to Embodiment 2 of the present invention. In FIG. 3, reference numeral 301 denotes a tri-state inverter, which is used as a control signal as a control signal. The clock signal CK is input, the output is in a high impedance state when CK = 1, and the inverter operates when CK = 0. 3
Reference numeral 03 denotes a tristate inverter to which CK is input as a control signal. When CK = 0, the output is in a high impedance state, and when CK = 1, the inverter operates. 302 is an inverter.

By connecting the tri-state inverter 301, the inverter 302, and the tri-state inverter 303 as shown in the figure, data is written when CK = 0 and the level latch 31 which holds data when CK = 1.
7.

Reference numeral 305 denotes a tri-state inverter to which a clock signal CK is input as a control signal. When CK = 1, the output is in a high impedance state, and when CK = 0, the inverter operates. 307 is a tri-state inverter, and CK is used as a control signal.
Is input, the output becomes a high impedance state when CK = 0, and performs an inverter operation when CK = 1. 306 is an inverter.

By connecting the tri-state inverter 305, the inverter 306, and the tri-state inverter 307 as shown in the figure, data is written when CK = 0, and the level latch 31 which holds data when CK = 1.
8.

Level latch 317 and level latch 318
Corresponds to the two-level latch of the third aspect.

Reference numeral 309 denotes a P-channel transistor (hereinafter, P-Tr), to which a clock signal CK is input. Reference numerals 310, 311 and 312 denote N-channel transistors (hereinafter referred to as N-Trs).
The output of the level latch 317 is input to 0, the output of the level latch 318 is input to the N-Tr 311, and the clock signal CK is input to the gate of the N-Tr 312.

Reference numeral 313 denotes a P-Tr, and a clock signal CK is input to the gate. 314,315,31
Reference numeral 6 denotes an N-Tr. The output of the level latch 317 is output to the N-Tr 315, and the level latch 3 is output to the N-Tr 314.
The output of 18 and the clock signal CK are input to the gate of the N-Tr 316.

Reference numerals 304 and 308 denote inverters.
-Tr309, 313, N-Tr310,311,31
2, 314, 315, 316 and decode circuit 31
9. This decoding circuit 319
. Corresponds to the decoding circuit described in.

The operation of the temporary data storage device according to the second embodiment will be described below. Level latch 317
Outputs the value of the input terminal DIN1 from the inverter 302 during the period of CK = 0, that is, the period corresponding to the first phase described in claim 3, and outputs the value of CK = 1, that is, the period of CK = 1. During the period opposite to the first phase, the inverter 302 outputs the value immediately before CK = 0 to CK = 1.

The level latch 318 is connected to the level latch 31
7, the value of the input terminal DIN2 is output from the inverter 306 during the period of CK = 0, and the value of CIN is output during the period of CK = 1.
The value immediately before the change from K = 0 to CK = 1 is calculated by the inverter 3
Output from 06.

The decoder 319 outputs the signal P during the period of CK = 0.
-Tr 309 turns on, inverter 304 outputs 0, P-Tr 313 turns on, and inverter 308 turns 0
Is output.

During the period of CK = 1, N-Trs 312 and 31
6, the output of the inverter 302, that is, the output of the level latch 317 is 1, and if the output of the inverter 306, that is, the output of the level latch 318, is 1, the N-Tr 310 and Tr 311 are turned on, and the inverter 304 is turned on. Of the input gate of the N-Tr 310,
Since it is discharged to 0 by passing through 311 and 312, the inverter 304 outputs 1 and the inverter 30 outputs
4 or the output of the level latch 317 or
If the output of the inverter 306, that is, the output of the level latch 318 is 0, N-Tr 310 or N-Tr3
11 is turned off, and the charge at the input gate of the inverter 304 remains at 1 without being discharged, so that the inverter 304 outputs 0.

On the other hand, if the output of the inverter 302, ie, the output of the level latch 317, or the output of the inverter 306, ie, the output of the level latch 318, is 1,
N-Tr314 or N-Tr315 is turned on,
The charge of the input gate of the inverter 308 is N-Tr 314
Alternatively, the charge is discharged through the N-Tr 315 and the N-Tr 316 to become 0, so that the inverter 308
Output 1 and the output of the inverter 302, that is, the output of the level latch 317 is 0, and the output of the inverter 3
If the output of 06, that is, the output of the level latch 318 is 0, the N-Trs 314 and 315 are turned off, and the charge of the input gate of the inverter 308 remains 1 without being discharged, so the inverter 308 outputs 0. .

That is, the operation of the temporary data storage device according to the second embodiment of the present invention is as follows. In the period of clock signal CK = 1, the logical product signal of the value of DIN1 and the value of DIN2 at the timing of the rising edge of clock signal CK is used. GO
UT outputs a logical sum signal of the value of DIN1 and the value of DIN2 at the timing of the rising edge of the clock signal CK from POUT, and outputs 0 from GOUT and 0 from POUT during the period of clock signal CK = 0. It will be.

FIG. 4 is an operation timing chart of the temporary data storage device according to the second embodiment.

The temporary data storage device according to the second embodiment configured as described above has a structure in which the level latch 317, the level latch 318, and the decoder 319 are arranged and connected as shown in FIG. =
In the period of 1, the logical product of the values of DIN1 and DIN2 at the timing of the rising edge of the clock signal CK is GOUT.
, And the logical sum is output from POUT. During the period of the clock signal CK = 0, both GOUT and POUT can output 0.

The level latch 317, the level latch 318, and the decoder 319 may have a configuration other than the above-described circuit configuration. Further, in the second embodiment, the case where the number of level latches is two has been described as an example, but a case other than two may be used. Further, although the configuration in which the logical product signal and the logical sum signal of the input terminal are output during the period of CK = 1 has been described, a configuration in which a logical operation result other than this is output may be used.

(Embodiment 3) FIG. 5 shows a circuit of a data temporary storage device according to Embodiment 3 of the present invention. In FIG. 5, reference numeral 501 denotes a tri-state inverter to which a clock signal CK is input as a control signal. When CK = 1, the output is in a high impedance state, and when CK = 0, the inverter operates. 5
Reference numeral 03 denotes a tristate inverter to which CK is input as a control signal. When CK = 0, the output is in a high impedance state, and when CK = 1, the inverter operates. 502 is an inverter.

By connecting the tri-state inverter 501, the inverter 502 and the tri-state inverter 503 as shown in the figure, data is written when CK = 0, and the level latch 51 which holds data when CK = 1.
9.

Reference numeral 505 denotes a tri-state inverter to which a clock signal CK is input as a control signal. When CK = 1, the output is in a high impedance state, and when CK = 0, the inverter operates. 507 is a tri-state inverter, and CK is used as a control signal.
Is input, the output becomes a high impedance state when CK = 0, and performs an inverter operation when CK = 1. 506 is an inverter.

By connecting the tri-state inverter 505, the inverter 506, and the tri-state inverter 507 as shown in the figure, data is written when CK = 0, and the level latch 52 which holds data when CK = 1.
0.

Level latch 519 and level latch 520
Corresponds to the two-level latch according to claim 4.

Reference numeral 509 denotes a P-channel transistor (hereinafter, P-Tr), to which a clock signal CK is input. Reference numerals 510, 511, and 512 denote N-channel transistors (hereinafter referred to as N-Trs).
The output of the level latch 519 is input to 0, the output of the level latch 520 is input to the N-Tr 511, and the clock signal CK is input to the gate of the N-Tr 512, respectively.

Reference numeral 513 denotes a P-Tr, and a clock signal CK is input to a gate. 514,515,51
6, 517 and 518 are N-Tr and N-Tr51.
4, the output of the level latch 519, the output of the tri-state inverter 505, that is, an inverted signal of the output of the level latch 520, the N-Tr 516, the output of the level latch 520, and the N-Tr 517. The output of the state inverter 501, that is, the inverted signal of the output of the level latch 519, and the clock signal CK are input to the gate of the N-Tr 518, respectively.

Reference numerals 504 and 508 denote inverters.
-Tr509, 513, N-Tr510,511,51
Along with 2,514,515,516,517,518,
The decoding circuit 521 is included. This decoding circuit 521 corresponds to the decoding circuit described in claim 4.

The operation of the temporary data storage device according to the third embodiment will be described below. Level latch 519
Outputs the value of the input terminal DIN1 from the inverter 502 during the period of CK = 0, that is, the period corresponding to the first phase described in claim 4, and outputs the value of CK = 1, that is, the period of CK = 1. During the period opposite to the first phase, the inverter 502 outputs a value immediately before CK = 0 to CK = 1.

The level latch 520 is connected to the level latch 51.
9, the value of the input terminal DIN2 is output from the inverter 506 during the period of CK = 0, and the value of the input terminal DIN2 is output during the period of CK = 1.
The value immediately before the change from K = 0 to CK = 1 is calculated by the inverter 5
Output from 06.

The decoder 521 outputs P during CK = 0.
-Tr509 turns on, the inverter 504 outputs 0, P-Tr513 turns on, and the inverter 508 turns 0
Is output.

During the period of CK = 1, N-Trs 512 and 51
8 is turned on, the output of the inverter 502, that is, the output of the level latch 519 is 1, and the output of the inverter 506, that is, the output of the level latch 520 is 1, the N-Trs 510, 511 are turned on, and the inverter 504 is turned on. Of the input gate of the N-Tr 510, 51
The inverter 504 outputs 1 since it is discharged to 0 by passing through the inverters 1, 512.
, Ie, the output of the level latch 519 or the output of the inverter 506, ie, the output of the level latch 520, is 0, the N-Tr 510 or the N-Tr 51
Since 1 is turned off and the charge of the input gate of the inverter 504 remains 1 without being discharged, the inverter 504 outputs 0.

On the other hand, the output of inverter 502, that is, the output of level latch 519 is 1, and the output of tristate inverter 505, that is, level latch 5
20 or the output of the inverter 506, that is, the output of the level latch 520 is 1 and the tri-state inverter 501
, The inverted signal of the output of the level latch 520 is 1, the N-Tr 514, 515 or N-Tr
Trs 516 and 517 are turned on, and the electric charge at the input gate of the inverter 508 is discharged through the N-Trs 514, 515 and 518 or N-Trs 516, 517 and 518 and becomes 0, so that the inverter 508 outputs 1. When the output of the inverter 502, ie, the output of the level latch 519, is 0, or the output of the tristate inverter 505, ie, the inverted signal of the output of the level latch 520 is 0, and the output of the inverter 506, ie, the output of the level latch 520, is 0, Alternatively, when the output of the tri-state inverter 501, that is, the inverted signal of the output of the level latch 519 is 0, the path from the input gate of the inverter 508 to the ground is turned off, so that the charge at the input gate of the inverter 508 is discharged. It remains at 1 and therefore
Inverter 508 outputs 0.

That is, the operation of the data temporary storage device according to the third embodiment of the present invention is as follows. In the period of clock signal CK = 1, the logical product signal of the value of DIN1 and the value of DIN2 at the timing of the rising edge of clock signal CK is used. GO
UT, an exclusive OR signal of the value of DIN1 and the value of DIN2 at the timing of the rising edge of the clock signal CK is output from POUT, and the clock signal CK = 0
During this period, 0 is output from GOUT and 0 is output from POUT.

FIG. 6 shows an operation timing chart of the temporary data storage device according to the third embodiment.

In the temporary data storage device according to the third embodiment having the above-described structure, the clock signal CK is provided by arranging and connecting the level latch 519, the level latch 520, and the decoder 521 as shown in FIG. =
In the period of 1, the logical product of the values of DIN1 and DIN2 at the timing of the rising edge of the clock signal CK is GOUT.
And the exclusive OR is output from POUT. During the period of clock signal CK = 0, both GOUT and POUT are set to 0.
Can be output.

The level latch 519, the level latch 520, and the decoder 521 may have a configuration other than the above-described circuit configuration. Further, in the third embodiment, the case where the number of level latches is two has been described as an example, but a case other than two may be used. Further, the configuration in which the AND signal of the input terminal and the exclusive OR signal are output during the period of CK = 1 has been described. However, a configuration in which other logical operation results are output may be used.

In general, the number of data output terminals of the decoder need not be equal to the number of level latches. For example, a decoder which has two level latches and has three data output terminals as a decoding circuit, a circuit for extracting the logical product and the logical sum in FIG. 3 and a circuit for extracting the exclusive logical sum in FIG. Is also possible.

[0078]

As described above, the data temporary storage device of the present invention has the following features. (1) A clock signal and a data signal are input, data is written during a period when the clock signal is in the first phase, and A level latch that serves as data holding during a period when the signal is in phase opposite to the first phase;
The clock signal and the output signal of the level latch are input, and 0 is output while the clock signal is in the first phase, and the value of the input signal from the level latch is output while the clock signal is in the opposite phase to the first phase. And (2) inputting a clock signal and a data signal, and writing data during a period in which the clock signal is in the first phase, and inverting the clock signal from the first phase. During the phase period, a plurality of level latches for holding data, the same number of data input terminals as the number of level latches and an arbitrary plurality of output terminals are provided, and a clock signal and each output signal of the plurality of level latches are input. During the period when the clock signal is in the first phase, each output terminal outputs 0, and during the period when the clock signal is in the opposite phase to the first phase, each output terminal is plural. Composed of a decode circuit that outputs a different logical operation result of the value of each input signal from the level latch.

As a result, in the prior art, the clock signal is turned off during the period of 0, which is required in the domino logic circuit represented by the carry chain of the Manchester carry adder, and the precharge node is precharged. The N-Tr for preventing the state from being destroyed is eliminated, and the operation delay time of the domino logic circuit can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a temporary data storage device according to a first embodiment of the present invention.

FIG. 2 is an operation timing chart of the temporary data storage device according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram of a temporary data storage device according to a second embodiment of the present invention;

FIG. 4 is an operation timing chart of the temporary data storage device according to the second embodiment of the present invention;

FIG. 5 is a circuit diagram of a temporary data storage device according to a third embodiment of the present invention.

FIG. 6 is an operation timing chart of the temporary data storage device according to the third embodiment of the present invention.

FIG. 7 is a circuit diagram of an example of a carry chain of a Manchester carry adder, which is a kind of a conventional domino logic circuit;

FIG. 8 is a circuit diagram of a flip-flop which is an example of a conventional data temporary storage device.

FIG. 9 is an operation timing chart of a flip-flop which is an example of a conventional data temporary storage device.

FIG. 10 is a circuit diagram of an example of a conventional AND circuit;

FIG. 11 is a circuit diagram of an example of a conventional exclusive OR circuit;

[Explanation of symbols]

101, 103, 301, 303, 305, 307, 5
01, 503, 505, 507 Tri-state inverters 102, 107, 302, 304, 306, 308, 5
02, 504, 506, 508 Inverter 104, 309, 313, 509, 513 P-channel transistor 105, 106, 310, 311, 312, 314, 3
15,316,510,511,512,514,51
5,516,517,518 N-channel transistor 108,317,318,519,520 Level latch 109,319,521 Decoder

Claims (4)

[Claims] 1. A clock signal and a data signal are input, data is written during a period when the clock signal is in a first phase, and data is held during a period when the clock signal is in a phase opposite to the first phase. A level latch, the clock signal and the output signal of the level latch being input, and a period during which the clock signal is in the first phase is 0.
And a decoding circuit for outputting a value of an input signal from the level latch during a period when the clock signal is in an opposite phase to the first phase. 2. A clock signal and a data signal are respectively input, and data writing is performed during a period when the clock signal is in a first phase, and data is held during a period when the clock signal is in a phase opposite to the first phase. A plurality of level latches, and the same number of data input terminals and any number of output terminals as the number of the level latches, and inputting the clock signal and each output signal of the plurality of level latches, During a period when the signal is at the first phase, each of the output terminals outputs 0, and during a period when the clock signal is at an opposite phase to the first phase, each of the output terminals is at the plurality of levels. A decoding circuit for outputting different logical operation results of the values of the respective input signals from the latches. 3. A clock signal and a data signal are respectively input, and data writing is performed during a period when the clock signal is in a first phase, and data is held during a period when the clock signal is in an opposite phase to the first phase. And two data input terminals and two output terminals for inputting respective output signals of the two level latches, respectively, and receive the clock signal and the respective output signals of the two level latches. Then, during the period when the clock signal is the first phase, the two output terminals each output 0, and during the period when the clock signal is in the opposite phase to the first phase,
One output terminal outputs a logical product of the input signals from the two level latches, and the other output terminal includes a decoding circuit that outputs a logical sum of the input signals from the two level latches. Data temporary storage device. 4. A clock signal and a data signal are respectively input, data writing is performed during a period when the clock signal is in a first phase, and data is held during a period when the clock signal is in a phase opposite to the first phase. And two data input terminals for inputting respective output signals of the two level latches, two inverted signal input terminals for inputting inverted signals of the respective output signals, and two output terminals. The clock signal, each of the output signals, and each of the inverted signals are input, and during the period when the clock signal is in the first phase, the two output terminals each output 0, and the clock signal During a period in which the first phase is opposite to the first phase, one output terminal outputs the logical product of the input signals from the two level latches, and the other output terminal outputs the logical product of the two levels. Data temporary storage device characterized by comprising a decoding circuit for outputting an exclusive logical sum of the input signals from Ruratchi.