KR100464380B1 - Integrated circuits - Google Patents

Abstract

PURPOSE: A semiconductor device is provided, which comprises a bus driver circuit constituted to reduce internal delay of a bus and also to reduce driving power consumption. CONSTITUTION: According to the semiconductor device, a data/address buffer(500) buffers input data or addresses. A pulse generation part(510) is connected to the data/address buffer, and generates a pulse signal in response to an output signal of the data/address buffer. A pull-up/down driver(520) is connected to the pulse generation part and the data/address buffer, and is pulled up in response to the pulse signal from the pulse generation part, and is pulled down in response to a signal being output from the data/address buffer. A latch part(530) is connected to the pull-up/down driver, and reduces swing width of a signal being output from the pull-up/down driver and latches it. A bus line(540) transmits a signal being output from the latch part. And a receiver part(550) is connected to the bus line, and receives a signal transmitted through the bus line, and decodes an address signal transmitted through the bus line, and latches data being transmitted through the bus line. The receiver part does not include a level conversion part converting the swing width of the signal transmitted from the bus line.

Description

Semiconductor device {Integrated circuits}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a bus line driving circuit capable of reducing driving power consumption.

As the performance of semiconductor devices is improved, the size and operating frequency of chip circuits are increased and power dissipation of chip circuits is increased. Therefore, as the technology of the semiconductor device is developed and its integration is increased to the scale of the gigabit unit, research on the design of the semiconductor device that can reduce the driving power consumption has been a major issue.

Attempts to lower driving power consumption in semiconductor devices have been largely made in two aspects. The first is to reduce the operating voltage of the chip circuit to a very low value, for example 1.5V. The second is to devise a new circuit technology that can reduce the driving power consumption while keeping the operating supply voltage of the chip circuit at a moderately low value, such as 2.0V.

If the operating power supply voltage of the chip circuit is lowered to a very low value, for example, 1.5V, the operating speed of the chip circuit is rather adversely affected. In other words, in order to lower the driving power supply voltage, threshold voltages of devices constituting the semiconductor device should be lowered. The threshold voltage values of the devices have a physical minimum value determined according to the size of each device. Therefore, the reduction of the threshold voltage value actually causes the phenomenon that the driving power consumption increases due to the increase of the standby current.

As a circuit technology that can reduce driving power consumption while maintaining an operating power supply voltage of a chip circuit at a moderately low value, for example, 2.0V, research on a new technique of a bus driving circuit inside a chip circuit has been conducted. .

In general, power consumption by charging and discharging of the internal bus is a significant portion of the driving power consumption of the semiconductor device. Therefore, by reducing the swing of the bus signal transmitted through the bus line to a very low value, the power consumption by charging and discharging of the bus is reduced, thereby reducing the overall chip circuit. Driving power consumption can be reduced.

1 shows a block diagram of a bus drive circuit in a conventional semiconductor device using a novel circuit technique that can reduce drive power consumption.

Referring to FIG. 1, in a conventional semiconductor device using a novel circuit technique capable of reducing driving power consumption, a bus driving circuit includes a data / address buffer 100, a pull up / down driver 110, and a bus line. 120, and a receiver 130.

The data / address buffer 100 buffers and outputs data or addresses to be transmitted through the bus line 120.

The pull up / down driver 110 inputs and drives a data / address signal buffered and output from the data / address buffer 100. The pull up / down driver 110 is powered by the power terminals VINTL and VSS. The voltage of the power supply terminal VINTL is much lower than the voltage of the power supply terminal VINT that operates the chip circuit.

The bus line 120 is a transmission line that transmits a signal output from the pull up / down driver 110.

The receiver 130 inputs a signal transmitted from the bus line 120 to convert a signal having a swing width corresponding to the driving power voltage level of the elements constituting the chip circuit, and outputs the signal as a corresponding data / address. The receiver 130 is configured as a level shifter, an address predecoder, and a data receiver. The level converter inputs a signal transmitted from the bus line 120 and converts the signal into a signal having a swing width corresponding to the driving power supply voltage level of the elements constituting the chip circuit. When the signal transmitted from the bus line 120 is an address, the address predecoder inputs a signal output from the level converter, decodes the signal into a corresponding address signal, and outputs the decoded address. When the signal transmitted from the bus line 120 is data, the data receiver inputs a signal output from the level switch and latches the data as the corresponding data.

2A illustrates a timing diagram of signals input to the pull up / down driver 110 in FIG. 1, and FIG. 2B illustrates a timing diagram of signals output from the pull up / down driver 110 in FIG. 1. have.

2A and 2B, in FIG. 1, the signal 220 output from the pull up / down driver 110 has a smaller swing width than the signal 210 input to the pull up / down driver 110. For example, it has a value corresponding to VINTL-VSS. The driving power supply voltages VINTL and VSS are generated by an internal power generation circuit inside the chip circuit.

FIG. 3 shows a circuit diagram of the level switch constituting the receiver 130 in FIG.

Referring to FIG. 3, the level switch constituting the receiver 130 in FIG. 1 includes PMOS transistors P1, P2, and P3, and NMOS transistors N1, N2, and N3.

The PMOS transistor P1 receives a signal transmitted from the bus line 120 through the source terminal from the input terminal IN and is gated by the power supply terminal VSS.

The NMOS transistor N1 receives a signal transmitted from the bus line 120 through the drain terminal from the input terminal IN, and is gated by the power supply terminal VINTL.

The PMOS transistor P2 has a source terminal connected to the power supply terminal VINT, a drain terminal connected to the source terminal of the NMOS transistor N1, and a gate terminal connected to the output terminal OUT.

The PMOS transistor P3 has a source terminal connected to the power supply terminal VINT, a drain terminal connected to the output terminal OUT, and a gate terminal connected to the source terminal of the NMOS transistor N1. The PMOS transistor P3 is turned on when the voltage level of the signal input to the input terminal IN is at the power supply terminal VSS level, so that the signal having the value of the power supply terminal VINT level is output to the output terminal OUT. Output The power supply terminal VINT is an internal power supply for driving the elements constituting the chip circuit.

In the NMOS transistor N2, the drain terminal is connected to the drain terminal of the PMOS transistor P1, the source terminal is connected to the ground terminal GND, and the gate terminal is connected to the output terminal OUT.

The NMOS transistor N3 has a drain terminal connected to the output terminal OUT, a source terminal connected to the ground terminal GND, and a gate terminal connected to the drain terminal of the PMOS transistor P1. The NMOS transistor N3 is turned on when the voltage level of the signal input to the input terminal IN is at the power supply terminal VINTL level, so that the signal having the value of the level of the ground terminal GND is supplied to the output terminal OUT. Output

FIG. 4 shows a detailed circuit diagram of the address free decoder constituting the receiver 130 in FIG.

Referring to FIG. 4, the address free decoder constituting the receiver 130 in FIG. 1 includes NAND gates 302, 304, 306, and 308, and inverter arrays 312, 314, 316, and 318. Here, the address free decoder is for the case of the address signals Ai and Aj. The address signals Ai and Aj are transmitted from the bus line 120 and converted to a level having a swing width corresponding to the driving power supply voltage level of the elements constituting the chip circuit through the level switch of the receiver 130. admit.

The NAND gate 302 inputs the address signals Ai, Aj, and the data / address enable pulse signal PDAAB so that they are low ('L') levels only when they are all high ('H') levels. Output the signal.

The NAND gate 304 inputs the address signal Ai, the inverted address signal / Aj, and the data / address enable pulse signal PDAAB so that they are low only when they are all high ('H') levels. ') Outputs a signal at the level.

The NAND gate 306 inputs the inverted address signal / Ai, the address signal Aj, and the data / address enable pulse signal PDAAB so that only when they are all high ('H') levels (L) ') Outputs a signal at the level.

The NAND gate 308 inputs inverting address signals / Ai, / Aj, and the data / address enable pulse signal PDAAB so that they are low ('L') only when they are all high ('H') levels. Outputs the signal to be the level.

The inverter array 312 receives a signal output from the NAND gate 302, inverts it, drives a delay, and outputs the signal. That is, the inverter array 312 is high only when the address signals Ai and Aj and the data / address enable pulse signal PDAEB input to the NAND gate 302 are all high ('H') levels. H ') level is output.

The inverter array 314 inputs a signal output from the NAND gate 304, inverts and drives a delay, and outputs the signal. In other words, the inverter array 314 has the address signal Ai, the inverted address signal / Aj, and the data / address enable pulse signal PDAEB input to the NAND gate 304 all high ('H'). Only when the signal reaches the high level ('H') is output.

The inverter array 316 inputs a signal output from the NAND gate 306, inverts and drives a delay, and outputs the signal. In other words, the inverter array 316 has the inverted address signal / Ai, the address signal Aj, and the data / address enable pulse signal PDAEB input to the NAND gate 306 to be high ('H') level. Only when the signal reaches the high level ('H') is output.

The inverter array 318 inputs a signal output from the NAND gate 308, inverts it, drives a delay, and outputs the signal. In other words, the inverter array 318 is provided only when the inverted address signals / Ai and / Aj and the data / address enable pulse signal PDAEB input to the NAND gate 308 are all high ('H') levels. Outputs a signal that is at a high ('H') level.

1 and 4, in the conventional semiconductor device, the bus driving circuit further includes a pull up / down driver 110 and a receiver 130 to reduce driving power consumption. The swing width of the bus signal is reduced at 110 and then transmitted through the bus line 120, and the swing width of the bus signal is changed in accordance with the elements constituting the chip circuit at the receiver 130. However, since the configuration method of the circuit requires an additional circuit such as a level switcher in the receiver 130, the DC power consumption is increased and the production cost is increased. In addition, there is a problem that the operation speed of the chip circuit is reduced by the delay of the signal through the level switch of the receiver 130.

It is therefore an object of the present invention to provide a semiconductor device having a bus driving circuit configured to reduce not only driving power consumption but also internal delay of the bus in the semiconductor device.

In order to achieve the above object, a semiconductor device according to the present invention includes a data / address buffer; A pulse generator for inputting a signal output from the data / address buffer and generating a pulse signal having a predetermined pulse width accordingly; A pull up / down driver pulled up by a pulse signal output from the pulse generator and pulled down by a signal output from the data / address buffer; A latch unit for reducing and latching a swing width of a signal output from the pull up / down driver; A bus line transmitting a signal output from the latch unit; And a receiver configured to input a signal transmitted from the bus line and decode corresponding address signals and output the decoded address signal as an address signal or to latch and output a corresponding data signal.

The receiver does not include a level switch for switching the swing width of the signal transmitted from the bus line to match the level of the elements constituting the chip circuit.

Next, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5 is a block diagram of a bus driving circuit in the semiconductor device according to the embodiment of the present invention.

Referring to FIG. 5, in a semiconductor device according to an exemplary embodiment of the present invention, a bus driving circuit includes a data / address buffer 500, a pulse generator 510, a pull up / down driver 520, and a latch unit 530. , A bus line 540, and a receiver 550.

The data / address buffer 500 buffers and outputs data or addresses to be transmitted through the bus line 540.

The pulse generator 510 inputs a signal output from the data / address buffer 500 and accordingly generates a pulse signal SP having a predetermined pulse width.

The pull up / down driver 520 is pulled up by the pulse signal SP output from the pulse generator 510 and pulled down by the signal output from the data / address buffer 500. -Down).

The latch unit 530 reduces and latches a swing width of a signal output from the pull up / down driver 520.

The bus line 540 transmits a signal output from the latch unit 530.

The receiver 550 inputs signals transmitted from the bus line 540 and thus decodes corresponding address signals to output corresponding address signals or latches signals transmitted from the bus line 540 as corresponding data. The receiver 550 does not need a level shifter for switching the swing width of the signal transmitted from the bus line 540 to match the level of the elements constituting the chip circuit.

FIG. 6 is a circuit diagram of a circuit according to a specific embodiment of the pulse generator 510 in FIG. 5.

Referring to FIG. 6, a circuit according to a specific embodiment of the pulse generator 510 in FIG. 5 includes a latch means 512, an inversion delay unit 514, and a NAND gate 516.

The latch means 512 inputs and latches a signal IN0 output from the data / address buffer 500.

The inversion delay unit 514 inputs a signal latched to the latch unit 512, inverts the signal, and outputs the signal by delaying the predetermined period. The inversion delay unit 514 is configured as an array of inverters 517, 518 and 519.

The NAND gate 516 inputs a signal output from the data / address buffer 500 and a signal output from the inversion delay unit 514 so that only a low level ('L') is provided when they are both high ('H') levels. Outputs a signal.

FIG. 7 illustrates a circuit diagram of a circuit according to a specific embodiment of the pull up / down driver 520 and the latch unit 530 in FIG. 5.

Referring to FIG. 7, a circuit according to a specific embodiment of the pull up / down driver 520 in FIG. 5 includes a PMOS transistor 522 and an NMOS transistor 524.

The PMOS transistor 522 has a source terminal connected to the power supply terminal VINT, and is gated by the signal SP output from the pulse generator 510.

The NMOS transistor 524 is connected between the drain terminal of the PMOS transistor 522 and the ground terminal GND and is gated by a signal IN0 output from the data / address buffer 500.

The pull up / down driver 520 is pulled up by the PMOS transistor 522 gated by the signal SP output from the pulse generator 510, and the data / address buffer 500 It is pulled down by the NMOS transistor 524 gated by the signal IN0 outputted from the output signal, and an output terminal is connected to the drain terminal of the PMOS transistor 522 to output the signal IN1. .

Referring to FIG. 7, the latch unit 530 is driven by a power supply terminal VINTL voltage having a lower value than the power supply terminal VINT voltage. Accordingly, the signal OUT0 output from the latch unit 530 has a swing width of the difference between the power terminal VINT voltage and the power terminal VINTL voltage, or the power terminal VINTL voltage and the ground terminal GND. Has the swing width of the value of the difference in voltage.

FIG. 8A illustrates a timing diagram of the signal IN0 output from the data / address buffer 500 and input to the pulse generator 510 in FIG. 5, and FIG. 8B illustrates the timing diagram of the latch unit 530 in FIG. 5. The timing chart of the output signal OUT0 is shown. Here, the timing diagram of the signal 220 shown in FIG. 2B is simultaneously shown in comparison with the conventional case.

8A and 8B, the pull up / down driver 520 of the bus driving circuit in the semiconductor device according to the embodiment of the present invention is driven by the power supply terminal VINT, compared with the conventional case. It has a faster rising time. In addition, since the voltage of the power supply terminal (VINT) is greater than that of the power supply terminal (VINTL), it has a faster pull-up time.

9 is a block diagram of a circuit according to a specific embodiment of the receiver 550 in FIG. 5.

Referring to FIG. 9, a circuit according to a specific embodiment of the receiver 550 in FIG. 5 includes an address free decoder 560 and a data latch unit 570.

The address predecoder 560 inputs address signals Ai and Aj transmitted from the bus line 540, decodes them, and outputs them as corresponding address signals PDA0 to PDAn.

The data latch unit 570 receives a data signal Di transmitted from the bus line 540 and latches the data signal Di as a corresponding data signal PDi and stores the data signal Di.

FIG. 10 shows a circuit diagram of a circuit according to a specific embodiment of the address free decoder 560 in FIG. 9.

Referring to FIG. 10, a circuit according to a specific embodiment of the address free decoder 560 in FIG. 9 includes an address decoding unit 580 and an address signal driver 590.

The address decoding unit 580 receives a signal transmitted from the bus line 540, decodes the signal, and outputs the decoded signal as the corresponding address signals DA0 to DA3. The address decoding means 580 comprises pull up means 581,582,583,584, decoding means 585,586,587,588, and pull down means 589,590,591,592.

The pull-up means 581, 582, 583, and 584 are PMOS transistors connected between a power supply terminal VINT and a corresponding output terminal among the output terminals 593, 594, 595, and 596 and gated by a timing control signal PDAP, respectively.

Decoding means 585,586,587,588 are respectively connected in series to the corresponding output terminal of the output terminals 593,594,595,596 and input corresponding address signals, for example signals Ai, Aj, transmitted from bus line 540. Decode them and output them.

The decoding means 585 is connected between the source terminal of the NMOS transistor NQ1 and the NMOS transistor NQ1 and the pull-down means 589 having a drain terminal connected to the output terminal 593 and gated by the signal Ai. It is comprised by the NMOS transistor NQ2 connected and gated by the signal Aj.

The decoding means 586 is connected between the source terminal of the NMOS transistor NQ3 and the NMOS transistor NQ3 and the pull-down means 590 having a drain terminal connected to the output terminal 594 and gated by the signal Ai. It consists of the PMOS transistor PQ1 connected and gated by the signal Aj.

The decoding means 587 is connected between the drain terminal of the PMOS transistor PQ2 and the PMOS transistor PQ2 and the pull-down means 591 which have a source terminal connected to the output terminal 595 and gated by the signal Ai. It is comprised by the NMOS transistor NQ4 connected and gated by the signal Aj.

The decoding means 588 has a source terminal connected to the output terminal 596 and is connected between the drain terminal of the PMOS transistor PQ3 and the pull-down means 592 which are gated by the signal Ai. It consists of the PMOS transistor PQ4 connected and gated by the signal Aj.

The pull down means 589, 590, 591, 592 are NMOS transistors connected between the corresponding decoding means and the ground terminal GND among the decoding means 585, 586, 587, and 588, respectively, and are gated by the timing control signal PDAE.

Although the address decoding means 580 inputs and decodes signals Ai and Aj having a low swing width through the decoding means 585,586, 587 and 588, pull-up means controlled by the timing control signal PDAP. The signals DA0 to DA3 having a swing width of a level pulled up by (581,582,583,584) to drive the elements constituting the chip circuit are output to the output terminals 593,594,595,596. Here, the timing control signal PDAP is a low ('L') level pulse signal and the timing control signal PDAA is a high ('H') level pulse signal. The timing control signal PDAP is activated before the timing control signal PDAE.

The address driver 600 latches and drives the address signals DA0 to DA3 that are decoded and output by the address decoding unit 580. The address driver 600 includes address signal latches and drivers 610, 620, 630, and 640.

The address signal latch and driver 610 is constituted by an address signal latch means 612, a precharge means 614, and an address signal driver 616.

The address signal latching means 612 receives a corresponding address signal DA0 among the address signals DA0, DA1, DA2, and DA4 output from the address decoding means 580, and latches the corresponding address signal DA0 to output the latched address.

The precharge means 614 is connected between the power supply terminal VINT and the address signal latch means 612, and is controlled by the timing control signal PDAE to precharge the address signal latch means 612. .

The address signal driver 616 drives the signal latched by the address signal latching means 612 and outputs it as an address signal PDA0.

Since the address signal latches and drivers 620, 630 and 640 have the same structure as the address signal latches and drivers 610, detailed descriptions thereof will be omitted.

As such, the pull-up means 581, 582, 583, 584, the pull-down means 589, 590, 591, 592, and the address signal latching means 612 are gated by the timing control signals PDAE and PDAP in the form of pulses. Signals having a swing width of a voltage level for driving the elements constituting the chip circuit are output as corresponding address signals without changing the levels of the signals Ai and Aj transmitted from the circuits.

FIG. 11 is a circuit diagram of a circuit according to a specific embodiment of the data latch unit 570 in FIG. 9.

Referring to FIG. 11, a circuit according to a specific embodiment of the data latch unit 570 in FIG. 9 includes a pull-up transistor 572, a data driving unit 574, a pull-down transistor 576, and a data latch unit. It consists of 578.

The pull-up transistor 572 is a PMOS transistor having a source terminal connected to the power supply terminal VINT and gated by the timing control signal PDAP.

The data driving means 574 is connected between the drain terminal of the pull-up transistor 572 and the pull-down transistor 576, and is an NMOS transistor gated by the data signal Di transmitted from the bus line 540. to be.

The pull-down transistor 576 is an NMOS transistor connected between the data driving means 574 and the ground terminal GND and gated by the timing control signal PDAE.

The data latching means 578 inputs and latches a data signal output from the drain terminal of the pull-down transistor 572.

Since the pull-up transistor 572 and the pull-down transistor 576 constituting the data latch unit 570 are gated by the timing control signals PDAP and PDA in the form of pulses, they are transmitted from the bus line 540. The signal having the swing width of the voltage level for driving the elements constituting the chip circuit is output as a corresponding data signal without changing the level of the data signal Di.

FIG. 12 shows the operation simulation result of the address free decoder shown in FIG. 10 with the operation simulation result of the conventional address free decoder shown in FIG. 4 in the semiconductor device according to the embodiment of the present invention. In this simulation, the power terminal VINTL voltage value is set to have 1/2 of the power terminal VINT voltage value, and the reference art represents the results of the present invention, and the reference art is a conventional art. The results are shown.

Referring to FIG. 12, the semiconductor device according to the embodiment of the present invention shows that the delay time and the driving power consumption of the signal transmission are much lower than those of the conventional case.

As described above, in the semiconductor device according to the embodiment of the present invention, the bus driving circuit includes the pulse generator 510, the pull up / down driver 520, the latch unit 530, the bus line 540, and the receiver 550. It is provided. Since the pull up / down driver 520 is driven by the power supply terminal VINT, the pull up / down driver 520 has a faster rising time and a pull-up time as compared with the conventional case. In addition, the receiver 550 may include the pull-up means 581, 582, 583, 584, the pull-down means 589, 590, 591, 592, and the address signal latch means 612 of the address predecoder 560 constituting the receiver 550. Since the gate is gated by the timing control signals PDAE and PDAP, the swing of the voltage level driving the elements constituting the chip circuit without changing the level of the signals Ai and Aj transmitted from the bus line 540. Signals having a width are output as corresponding address signals PDA0 to PDA3. In addition, the reception unit 550 is configured to gate the pull-up transistor 572 and the pull-down transistor 576 of the data latch unit 570 constituting the reception unit 550 by pulsed timing control signals PDAP and PDAE. Therefore, even if the level of the data signal Di transmitted from the bus line 540 is not switched, a signal having a swing width of a voltage level for driving the elements constituting the chip circuit is output as a corresponding data signal.

Therefore, since a level changer for switching the level of the signal transmitted from the bus line 540 is not necessary, the swing of the signal transmitted through the bus line 540 without reducing the operation speed of the chip circuit or increasing the production cost. The width can be reduced. Therefore, the driving power consumption can be significantly reduced.

13 is a block diagram of a bus driving circuit in a semiconductor device according to another embodiment of the present invention.

Referring to FIG. 13, in a semiconductor device according to another exemplary embodiment of the present invention, a bus driving circuit includes a data / address buffer 700, a pulse generator 710, a pull up / down driver 720, and a latch unit 730. ), A bus line 740, and a receiver 750.

The data / address buffer 700 buffers and outputs data or addresses to be transmitted through the bus line 740.

The pulse generator 710 inputs a signal output from the data / address buffer 700 and accordingly generates a pulse signal SP having a predetermined pulse width.

The pull up / down driver 720 is pulled up by the pulse signal SP output from the pulse generator 710 and pulled down by the signal output from the data / address buffer 700. -Down).

The latch unit 730 reduces and latches a swing width of a signal output from the pull up / down driver 720.

The bus line 740 transmits a signal output from the latch unit 730.

The pulse generator 710, the pull up / down driver 720, and the latch unit 730 include the pulse generator 510, the pull up / down driver 520, and the latch unit illustrated in FIGS. 6 to 7. Since it has the same structure as 530, detailed description thereof will be omitted.

The receiver 750 inputs signals transmitted from the bus line 740, and level-changes them to have a swing width of a signal for driving elements constituting the chip circuit, thereby decoding corresponding ones and outputting corresponding address signals. Or print the corresponding data.

The receiving unit 750 is configured as a level shifter, an address predecoder, and a data latching unit. The level converter inputs a signal transmitted from the bus line 740 and converts the signal into a signal having a swing width corresponding to the driving power supply voltage level of the elements constituting the chip circuit. When the signal transmitted from the bus line 740 is an address, the address predecoder inputs a signal output from the level converter and decodes the signal into a corresponding address signal. When the signal transmitted from the bus line 740 is data, the data latch unit inputs a signal output from the level switch and latches it as the corresponding data.

The level shifter, the address predecoder, and the data latch unit constituting the receiving unit 750 can be configured to have the same structure as the conventional circuits shown in FIGS. I will omit them.

As described above, in the semiconductor device according to the embodiment of the present invention, the bus driving circuit includes a pulse generator 710, a pull up / down driver 720, a latch unit 730, a bus line 740, and a receiver. 750. Since the pull up / down driver 720 is driven by the power supply terminal VINT, the pull up / down driver 720 has a faster rising time and a pull-up time as compared with the conventional case.

Therefore, the swing width of the signal transmitted through the bus line 740 can be reduced without reducing the operation speed of the chip circuit. Therefore, the driving power consumption can be significantly reduced.

14 is a block diagram of a bus driving circuit in a semiconductor device according to still another embodiment of the present invention.

Referring to FIG. 14, in a semiconductor device according to another exemplary embodiment, a bus driving circuit may include a data / address buffer 800, a pull up / down driver 810, a bus line 820, and a receiver 830. ).

The data / address buffer 800 buffers and outputs data or addresses to be transmitted through the bus line 820.

The pull up / down driver 810 receives a signal output from the data / address buffer 800 and is pulled up and pulled down accordingly, and is driven by the power supply terminal VINTL.

The bus line 820 transmits a signal output from the pull up / down driver 810.

The receiver 830 inputs a signal transmitted from the bus line 820, and accordingly decodes the corresponding address or latches the corresponding data as output.

The receiver 830 does not include a level switch for switching the swing width of the signal transmitted from the bus line 820 to match the level of the elements constituting the chip circuit. The receiver 830 inputs a signal transmitted from the bus line 820 and inputs an address pre-decoder to decode a corresponding address and a signal transmitted from the bus line 820 to latch and store corresponding data. It is comprised as a latch part.

Since the pull up / down driver 810 may be configured to have the same structure as the pull up / down driver 110 shown in FIG. 1, a detailed description thereof will be omitted. In addition, since the address predecoder and the data latch unit constituting the receiving unit 830 may be configured in the same way as the structures of the address signal predecoder 560 and the data latch unit 570 shown in FIGS. 9 to 11. Will be omitted.

As described above, in the semiconductor device according to the exemplary embodiment of the present invention, the bus driving circuit includes a pull up / down driver 810, a bus line 820, and a receiver 830. The receiver 830 is configured to gate pull-up means, pull-down means, and address signal latch means of the address signal predecoder constituting the receiver 830 by gate timing control signals PDAA and PDAP. Therefore, signals having a swing width of a voltage level for driving the elements constituting the chip circuit are output as corresponding address signals without changing the levels of the signals Ai and Aj transmitted from the bus line 820. In addition, since the pull-up transistor and the pull-down transistor of the data latch unit constituting the receiver 830 are gated by the timing control signals PDAP and PDA in the form of the receiver 830, the receiver 830 transmits from the bus line 820. A signal having a swing width of a voltage level for driving the elements constituting the chip circuit is output as a corresponding data signal without changing the level of the data signal Di to be used.

Therefore, since a level changer for switching the level of the signal transmitted from the bus line 820 is not necessary, the swing of the signal transmitted through the bus line 820 without reducing the operation speed of the chip circuit or increasing the production cost. The width can be reduced. Therefore, the driving power consumption can be significantly reduced.

According to the present invention, the bus driving circuit has a high rising time and pull-up time of a bus signal having a low swing width, and also uses a pulse type timing control signals to configure the bus. A signal having a swing width of a voltage level for driving the elements constituting the chip circuit is output as a corresponding data / address signal without switching the level of the signal. Thus, the swing width of the signal transmitted through the bus line can be reduced without reducing the operation speed of the chip circuit or increasing the production cost. Therefore, the driving power consumption can be significantly reduced.

1 is a block diagram of a bus driving circuit in a conventional semiconductor device.

FIG. 2A is a timing diagram of signals input to the pull up / down driver in FIG. 1.

FIG. 2B is a timing diagram of signals output from the pull up / down driver in FIG. 1.

FIG. 3 is a circuit diagram of the level changer constituting the receiver in FIG. 1.

4 is a circuit diagram of an address free decoder constituting a receiver in FIG.

5 is a block diagram of a bus driving circuit in the semiconductor device according to the embodiment of the present invention.

FIG. 6 is a circuit diagram of a circuit according to a specific embodiment of the pulse generator in FIG. 5.

FIG. 7 is a circuit diagram of a circuit according to a specific embodiment of the pull up / down driver and the latch unit in FIG. 5.

8A is a timing diagram of a signal input to a pulse generator in FIG. 5.

FIG. 8B is a timing diagram of signals output from the pulse generator and the latch unit in FIG. 5.

9 is a block diagram of a circuit according to a specific embodiment of the receiver of FIG. 5.

FIG. 10 is a circuit diagram of a circuit according to a specific embodiment of the address free decoder in FIG. 9.

FIG. 11 is a circuit diagram of a circuit according to a specific embodiment of the data latch unit in FIG. 9.

12 is a simulation result of the operation of the address free decoder in FIG. 9.

13 is a block diagram of a bus driving circuit in a semiconductor device according to another embodiment of the present invention.

14 is a block diagram of a bus driving circuit in a semiconductor device according to still another embodiment of the present invention.

<Detailed Description of Symbols in Drawings>

VINT, VINTL, VSS, GND: power terminals, t1, t2: time

PDAP, PDAE: timing control signals, Ai, Aj: address signals,

PDA0 to PDAn: pre-address signals,

N1 to N3, NQ1 to NQ4: NMOS transistors,

P1 to P3, PQ1 to PQ4: PMOS transistors.

Claims (34)

In a semiconductor device, A data / address buffer for buffering and outputting input data or addresses; A pulse generator connected to the data / address buffer and generating a pulse signal having a predetermined pulse width in response to an output signal of the data / address buffer; A pull up / down driver connected to the pulse generator and a data / address buffer, pulled up in response to a pulse signal output from the pulse generator, and pulled down in response to a signal output from the data / address buffer; A latch unit connected to the pull up / down driver and configured to reduce and latch a swing width of a signal output from the pull up / down driver; A bus line transmitting a signal output from the latch unit; And It is connected to the bus line, inputs a signal transmitted through the bus line, and if the signal transmitted through the bus line is an address signal, decodes it and outputs it, and latches it if the signal transmitted through the bus line is data. And a receiving unit for outputting And the receiving unit does not include a level switching unit for switching the swing width of the signal transmitted from the bus line to match the level of the elements constituting the chip circuit. The method of claim 1, wherein the pulse generator 510 is Latch means (512) for inputting and latching a signal output from the data / address buffer; An inversion delay unit 514 for inputting a signal latched to the latch means 512, inverting the signal, and outputting the signal by delaying a predetermined period of time; And And a NAND gate 516 for inputting a signal output from the data / address buffer 500 and a signal output from the inversion delay unit 514 and outputting a signal that becomes a low level only when both of them are at a high level. A semiconductor device, characterized in that. The method of claim 1, wherein the pull up / down driver 520 is A PMOS transistor 520 having a source terminal connected to a first power supply terminal VINT and gated by a signal output from the pulse generator 510; And An NMOS transistor 524 connected between the drain terminal of the PMOS transistor 520 and a ground terminal GND and gated by a signal output from the data / address buffer 500, An output terminal (OUT0) is connected to the drain terminal of the PMOS transistor (522). 4. The semiconductor device of claim 3, wherein the latch unit is driven by a second power supply terminal voltage. The semiconductor device according to claim 4, wherein the second power supply terminal voltage has a value smaller than the first power supply terminal voltage. 6. The semiconductor device according to claim 5, wherein the latch section outputs a signal having a swing width of a value of a difference between the first power supply terminal voltage and the second power supply terminal voltage. 6. The semiconductor device according to claim 5, wherein the latch section outputs a signal having a swing width of a value of a difference between the second power supply terminal voltage and the ground terminal voltage. The method of claim 1, wherein the receiver 550 is An address predecoder 560 which receives signals transmitted from the bus line 540, decodes them, and outputs them as corresponding address signals; And And a data latch unit (570) for inputting a signal transmitted from the bus line (540), latching it as corresponding data, and storing the same. The method of claim 8, wherein the address predecoder 560 is Address decoding means (580) for inputting signals transmitted from the bus line (540), decoding them and outputting them as corresponding address signals; And And an address driver (590) for latching and driving address signals decoded by the address decoding means (580). 10. The apparatus of claim 9, wherein the address decoding means 580 A plurality of pull-up means 581 to 584 respectively connected between the first power supply terminal VINT and the corresponding output terminal and controlled by a first timing control signal; A plurality of decoding means 585 to 588, each connected in series to the corresponding output terminal, for inputting the corresponding signals transmitted from the bus line 540 and decoding them; And Each of the plurality of decoding means 585 to 588 includes a plurality of pull down means 589 to 592 connected between a corresponding decoding means and a ground terminal and controlled by a second timing control signal. A semiconductor device, characterized in that. The semiconductor device according to claim 10, wherein said plurality of pull-up means (581 to 584) are PMOS transistors. 11. A semiconductor device according to claim 10, wherein the plurality of pull down means (589-592) are NMOS transistors. 12. The plurality of NMOS transistors of claim 10, wherein the plurality of decoding means 585 to 588 are gated by a corresponding signal among the signals transmitted from the bus line 540 and connected to each other in series. And a decoding means (585) constituted by (NQ1, NQ2). 12. The plurality of PMOS transistors of claim 10, wherein the plurality of decoding means 585 to 588 are respectively gated by a corresponding signal among the signals transmitted from the bus line 540 and connected in series with each other. And a decoding means (588) constituted by (PQ3, PQ4). The at least one PMOS transistor of claim 10, wherein the plurality of decoding means 585 to 588 are respectively gated by a corresponding signal among the signals transmitted from the bus line 540 and connected in series with each other. (PQ1, PQ2) and decoding means (586 or 587) composed of at least one NMOS transistor (NQ3, NQ4). The method of claim 9, wherein the address driver 600, respectively, Address signal latching means (612) for inputting and latching a corresponding address signal among the address signals outputted from the address decoding means (580); A precharge means 614 connected between the first power supply terminal VINT and the address signal latching means 612 and controlled by the first timing control signal to precharge the address signal latching means 612. ); And And a plurality of address signal latches and drivers (610, 620, 630, 640) having an address signal driver (616) for driving and outputting a signal latched by said address signal latching means (612). In a semiconductor device, A data / address buffer for buffering and outputting input data or addresses; A pulse generator connected to the data / address buffer and generating a pulse signal having a predetermined pulse width in response to an output signal of the data / address buffer; A pull up / down driver connected to the pulse generator and a data / address buffer, pulled up in response to a pulse signal output from the pulse generator, and pulled down in response to a signal output from the data / address buffer; A latch unit connected to the pull up / down driver and configured to reduce and latch a swing width of a signal output from the pull up / down driver; A bus line transmitting a signal output from the latch unit; And A signal connected to the bus line and inputted through the bus line, and converted to a level suitable for driving a chip circuit connected to the semiconductor device, and if the level converted signal is an address signal, it is decoded and outputted And a receiver configured to latch and output the level-converted signal when the data is data. 18. The method of claim 17, wherein the pulse generator 710 is Latch means (512) for inputting and latching a signal output from the data / address buffer 700; An inversion delay unit 514 for inputting a signal latched to the latch means 512, inverting the signal, and outputting the signal by delaying a predetermined period of time; And And a NAND gate 516 for inputting a signal output from the data / address buffer 700 and a signal output from the inversion delay unit 514 to output a signal that becomes a low level only when both of them are at a high level. A semiconductor device, characterized in that. 18. The method of claim 17, wherein the pull up / down driver 720 A PMOS transistor 522 connected to a first power supply terminal VINT, the source terminal being gated by a signal output from the pulse generator 710; And An NMOS transistor 524 connected between the drain terminal of the PMOS transistor 522 and a ground terminal GND and gated by a signal output from the data / address buffer 700, An output terminal (OUT0) is connected to the drain terminal of the PMOS transistor (522). 20. The semiconductor device according to claim 19, wherein said latch portion is driven by a second power supply terminal voltage. 21. The semiconductor device according to claim 20, wherein the second power supply terminal voltage has a value smaller than the first power supply terminal voltage. The semiconductor device according to claim 21, wherein the latch unit outputs a signal having a swing width of a value of a difference between the first power terminal voltage and the second power terminal voltage. 23. The semiconductor device according to claim 22, wherein the latch section outputs a signal having a swing width of a difference between the second power supply terminal voltage and the ground terminal voltage. The method of claim 17, wherein the receiver 750 is A level switch 753 which inputs a signal transmitted from the bus line 740 and level-changes the signal to have a swing width of a level for driving elements constituting the chip circuit; An address predecoder 755 which receives the outputs from the level switch 753 and decodes them accordingly and outputs them as corresponding address signals; And And a data latch unit (757) for inputting the output from the level shifter (753) and latching and storing the output as the corresponding data accordingly. In a semiconductor device, First and second power supply terminals; A data / address buffer for buffering and outputting input data or addresses; A pull up / down driver connected to the second power supply terminal and a data / address buffer and pulled up in response to a pulse signal output from the pulse generator, and pulled down in response to a signal output from the data / address buffer; A pull-up / down driver coupled to the second power terminal and a data / address buffer and pulled up and pulled down in response to a signal output from the data / address buffer and driven by the second power terminal; A bus line transmitting a signal output from the pull up / down driver; And It is connected to the bus line and inputs signals transmitted through the bus line, and if the signal transmitted through the bus line is an address signal, it is decoded and outputted. If the signal transmitted through the bus line is data, it is latched. And a receiving unit for outputting And the receiving unit does not include a level switching unit for switching the swing width of the signal transmitted through the bus line to match the level of the elements constituting the chip circuit. The method of claim 25, wherein the receiving unit 830 An address pre-decoder 835 for inputting signals transmitted from the bus line 820, decoding them, and outputting them as corresponding address signals; And And a data latch unit (837) for inputting a signal transmitted from the bus line (820), latching it as the corresponding data, and storing the same. 27. The method of claim 26 wherein the address predecoder 835 is Address decoding means (580) for inputting a signal transmitted from the bus line (820), decoding it, and outputting it as corresponding address signals; And And an address driver (600) for latching and driving the address signal decoded by the address decoding means (580). 28. The apparatus of claim 27, wherein the address decoding means 580 A plurality of pull-up means 581 to 584 respectively connected between the first power supply terminal VINT and the corresponding output terminal and controlled by a first timing control signal; A plurality of decoding means 585 to 588, each connected in series to the corresponding output terminal, for inputting the corresponding signals transmitted from the bus line 820 and decoding them; And Each of the plurality of decoding means 585 to 588 includes a plurality of pull down means 589 to 592 connected between a corresponding decoding means and a ground terminal and controlled by a second timing control signal. A semiconductor device, characterized in that. The semiconductor device according to claim 28, wherein said plurality of pull-up means are PMOS transistors. 29. The semiconductor device of claim 28, wherein the plurality of pull down means are NMOS transistors. 29. The plurality of NMOS transistors of claim 28, wherein the plurality of decoding means 585 to 588 are each gated by a corresponding signal among the signals transmitted from the bus line 820 and connected in series with each other. And a decoding means (585) constituted by (NQ1, NQ2). 29. The plurality of PMOS transistors of claim 28, wherein the plurality of decoding means 585 to 588 are respectively gated by a corresponding signal among the signals transmitted from the bus line 820 and connected in series with each other. And a decoding means (588) constituted by (PQ3, PQ4). 29. The at least one PMOS transistor of claim 28, wherein the plurality of decoding means 585 to 588 are respectively gated by a corresponding signal among the signals transmitted from the bus line 820 and connected in series with each other. And a decoding means (585 or 587) composed of (PQ1, PQ2) and at least one NMOS transistor (NQ3, NQ4). The method of claim 27, wherein the address driver 600, respectively, Address signal latching means (612) for inputting and latching a corresponding address signal among the address signals output from the address decoding means (580); Precharge means (614) connected between said first power supply terminal (VINT) and said address signal latch means (612) and controlled by said first timing control signal to precharge said address signal latch means; And And a plurality of address signal latches and drivers (610, 620, 630, 640) having an address signal driver (616) for driving and outputting a signal latched by said address signal latching means (612).

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