CN104461620B - A kind of SoPC chips Autonomous Reconfiguration soft configuration method - Google Patents

Abstract

A SoPC chip self-reconfiguration soft configuration method, the SoPC chip self-reconfiguration soft configuration circuit technology is studied, and a SoPC chip self-reconfiguration soft configuration method is proposed, and the method of the present invention fully utilizes the characteristics of the controllability of the configuration interface , connect the GPIO interface of the processor with the configuration interface of the FPGA chip, construct the physical data path and configuration link, realize the configuration sequence and configuration data by controlling the signal output and collection of the GPIO interface, and change the interface level, and complete the self-reconfiguration operate. Compared with the traditional reconfiguration configuration method, the method of the present invention can realize the autonomous reconfiguration operation of the system without adding an FPGA-specific configuration chip to the SoPC chip, effectively reducing the volume of the SoPC chip, and at the same time, the interior of the SoPC chip is used for control and realization. There are fewer signals for autonomous reconfiguration operations, which reduces design complexity.

Description

A SoPC chip autonomous reconfiguration soft configuration method

technical field

The present invention relates to a chip autonomous reconfiguration soft configuration method, in particular to a SoPC chip autonomous reconfiguration soft configuration method, enabling the chip to have intelligent autonomous reconfiguration and on-orbit upgrade capabilities of hardware tasks in an outer space environment .

Background technique

Traditional on-board electronic systems include a large number of discrete devices and small-scale integrated circuits. More printed boards and stand-alone machines increase the volume and power consumption of the whole machine, and the complex interconnection structure reduces system reliability. , obviously, the traditional electronic system will be difficult to meet the development needs of future spaceborne computer miniaturization.

The domestic SoPC chip BM3109 is more in line with the needs of the development of electronic systems. In the spatial dimension, data calculation and processing are realized by constructing hardware logic circuits, thus making full use of the advantages of high-efficiency and concurrent execution of hardware circuits. The variability in the time dimension enables an FPGA to perform different functions at different times, increasing the System flexibility and functional density.

The traditional FPGA configuration method needs to be realized by using a dedicated configuration chip and corresponding circuits. When designing a SoPC chip, if this part of the circuit is integrated into the chip through SIP technology, the chip area will increase and the density of the internal processing circuit will be reduced. If the configuration circuit is placed outside the chip, the entire configuration process will be exposed, which is not conducive to the security and confidentiality of the chip.

Contents of the invention

The technical problem solved by the invention is: to overcome the deficiencies of the prior art and provide a method for realizing the self-reconfiguration soft configuration circuit of the SoPC chip under the premise of reducing the area of the chip configuration part.

The technical solution of the present invention is: a kind of SoPC chip self-reconfiguration soft configuration method, comprises the following steps:

(1) Connect the address line A _i of the SPARC V8 processor to the address line PA _{i-1 of the FLASH, i=1, 2, 3,..., 22} , and the data line D _j is connected to the data line DQ _{g of the FLASH, j=16,17,18,...,31, g=0,1,2,...,15} , the write control signal terminal is connected to the WE terminal of FLASH, the reset control signal terminal is connected to the PRESET terminal of FLASH, The chip selection control signal terminal is connected to the CE terminal of FLASH, and the read control signal terminal is connected to the OE terminal of FLASH;

(2) Connect the GPIO-PIO48 pin of the SPARC V8 processor to the IO_D7 pin of the FPGA, connect the GPIO-PIO49 pin to the IO_D6 pin of the FPGA, connect the GPIO-PIO50 pin to the IO_D5 pin of the FPGA, and connect the GPIO-PIO49 pin to the IO_D5 pin of the FPGA. The PIO51 pin is connected to the IO_D4 pin of the FPGA, the GPIO-PIO52 pin is connected to the IO_D3 pin of the FPGA, the GPIO-PIO53 pin is connected to the IO_D2 pin of the FPGA, and the GPIO-PIO54 pin is connected to the IO_D1 pin of the FPGA. The GPIO-PIO55 pin is connected to the IO_D0 pin of the FPGA, the GPIO-PIO56 pin is connected to the INIT pin of the FPGA, the GPIO-PIO58 pin is connected to the DONE pin of the FPGA, and the GPIO-PIO60 pin is connected to the IO_DOUT_BUSY pin of the FPGA. GPIO-PIO62 is connected to the IO_WRITE pin of the FPGA, GPIO-PIO63 is connected to the IO_CS pin of the FPGA, GPIO-PIO57 is connected to the PROGRAM pin of the FPGA, and GPIO-PIO61 is connected to the GCLK pin of the FPGA foot;

(3) Generate a .bit file arbitrarily in the ISE10.1 development environment and send it to the FLASH, power on the SPARCV8 processor, FLASH, and FPGA, and the SPARC V8 processor reads the .bit file from the FLASH, according to the .bit file format and the configuration format of the Virtex chip to generate an array of configuration information;

(4) Set the GPIO-PIO57 pin of the SPARC V8 processor as an output, write "1" to the data register of the GPIO-PIO57 pin, and then write to the data register of the GPIO-PIO57 pin of the SPARC V8 processor Enter "0", set the GPIO-PIO56 pin of the SPARC V8 processor as an input, and monitor the voltage change of the INIT pin of the FPGA;

(5) If the INIT pin changes from low level to high level, then go to step (6); if the INIT pin of FPGA is high level, then repeat step (3)-step (4) until FPGA Turn to step (6) after the INIT pin transitions from low level to high level;

(6) Set the SPARC V8 processor GPIO-PIO63 pin as an output, then write "0" to the data register of the SPARC V8 processor GPIO-PIO63, set the SPARC V8 processor GPIO-PIO62 pin as an output after one clock cycle, And write "0" to the data register of SPARC V8 processor GPIO-PIO62;

(7) Set the GPIO-PIO61 pin of the SPARC V8 processor as an output, write "1" to the data register of the GPIO-PIO61 of the SPARC V8 processor, and send the data of the GPIO-PIO61 of the SPARC V8 processor in the next clock cycle Write "0" to the register, write "1" and "0" to the data register of the GPIO-PIO61 of the SPARC V8 processor alternately, and perform steps (8)-step (9) at the same time;

(8) Set the GPIO-PIO63 pin of the SPARC V8 processor as an output, write "0" to the data register of the SPARC V8 processor GPIO-PIO63, set the GPIO-PIO62 pin of the SPARC V8 processor as an output, and send to the SPARC Write "0" into the data register of GPIO-PIO62 of the V8 processor, set the GPIO-PIO57 pin of the SPARC V8 processor as an output, and write "1" into the data register of the GPIO-PIO57 of the SPARC V8 processor;

(9) Take out the data sequentially from the configuration information array, and when the GCLK signal of the FPGA is at a high level, write it into the GPIO-PIO48, GPIO-PIO49, and GPIO-PIO50 of the SPARC V8 processor from high to low in binary format , GPIO-PIO51, GPIO-PIO52, GPIO-PIO53, GPIO-PIO54, GPIO-PIO55, and continuously monitor the IO_DOUT_BUSY pin of the FPGA. Write the current configuration data into the data registers of GPIO-PIO50, GPIO-PIO51, GPIO-PIO52, GPIO-PIO53, GPIO-PIO54, and GPIO-PIO55 until the IO_DOUT_BUSY signal output is low. If IO_DOUT_BUSY is low, then Go to step (10);

(10) Set the SPARC V8 processor GPIO-PIO62 pin as an output, write "1" to the data register of the SPARC V8 processor GPIO-PIO62, then set the SPARC V8 processor GPIO-PIO63 pin as an output, and write "1" to the SPARC V8 processor GPIO-PIO63 pin as an output The data register of the processor GPIO-PIO63 is written to "1";

(11) Configure the GPIO-PIO58 pin of the SPARC V8 processor as an input, and continuously detect the output of the DONE control signal of the FPGA. If the DONE control signal level is high, the soft configuration circuit is completed. If the DONE control signal level is not high , then continue to wait until the DONE signal is high, and when the waiting time exceeds the set threshold, then repeat steps (1) to (10) until the DONE signal is high.

The advantage of the present invention compared with prior art is:

(1) The inventive method makes the SoPC chip volume smaller, and compared with the traditional reconfiguration configuration method, the autonomous reconfiguration operation of the system can be realized without adding an FPGA-specific configuration chip to the SoPC chip, effectively reducing the SoPC chip. At the same time, there are fewer signals inside the SoPC chip to control and realize the autonomous reconfiguration operation, which reduces the design complexity, simplifies the layout and wiring, and reduces the size of the SoPC chip;

(2) the inventive method reconfiguration configuration power consumption is low, compares with traditional reconfiguration configuration method, the inventive method needn't add FPGA special-purpose configuration chip to realize independent reconfiguration operation, has reduced SoPC chip supporting circuit quantity and scale, Reduced power consumption of the system;

(3) the inventive method reconstruction configuration speed is fast, compares with traditional reconstruction configuration method, the present invention has realized the autonomous reconstruction operation of 8bit parallel mode inside SoPC chip, and speed is faster;

(4) The method of the present invention has high security. Compared with the traditional reconfiguration configuration method, the present invention realizes the autonomous reconfiguration operation inside the SoPC chip without external interface. During the system configuration process, other external devices cannot perform configuration information Interception and analysis ensure the security of configuration data;

(5) The method of the present invention has high reliability. Compared with the traditional reconfiguration configuration method, the present invention realizes the autonomous reconfiguration operation inside the SoPC chip, reduces the impact of the external environment on the exposed configuration chip, and prevents the configuration chip from Solder joints fall off due to vibration during flight.

Description of drawings

Fig. 1 is a schematic diagram of the self-reconfiguration operation of the method of the present invention;

Fig. 2 is a schematic diagram of the self-reconfiguration operation of the SoPC chip in the method of the present invention.

detailed description

The invention realizes the independent reconfiguration of the SoPC chip by constructing a configuration data link inside the SoPC chip BM3109. The SoPC chip BM3109 reads the configuration file of the FPGA from the storage space inside the chip according to the changes of the external environment and the requirements of the task, and loads the configuration data into the FPGA through the soft configuration interface. The self-reconfiguration operation is shown in Figure 1. SoPC The self-reconfiguration operation of the chip is shown in Figure 2. Among them, BM3109 includes external memory FLASH, SPARC V8 processor and FPGA.

Aiming at this special application background, the present invention conducts research on the realization scheme of SoPC chip BM3109 self-reconfiguration. A SoPC chip autonomous reconfiguration soft configuration method is proposed. Make full use of the controllability of the configuration interface, connect the GPIO interface of the processor with the configuration interface of the FPGA, and construct the physical data path and configuration link. The self-reconfiguration operation is completed by controlling the signal output and acquisition of the GPIO interface and realizing the configuration timing and configuration data through the interface level change.

1. To realize the configuration operation of the soft configuration circuit, it is necessary to realize the pin connection involving the SPARC V8 processor and the external memory FLASH.

The address line A1 of the SPARC V8 processor is connected to the address line PA0 of the external memory FLASH, the address line A2 is connected to the address line PA1 of the FLASH, the address line A3 is connected to the address line PA2 of the FLASH, and the address line A4 is connected to the address line PA3 of the FLASH. Address line A5 is connected to address line PA4 of FLASH; address line A6 is connected to address line PA5 of FLASH, address line A7 is connected to address line PA6 of FLASH, address line A8 is connected to address line PA7 of FLASH, and address line A9 is connected to FLASH The address line PA8, the address line A10 is connected to the address line PA9 of FLASH, the address line A11 is connected to the address line PA10 of FLASH, the address line A12 is connected to the address line PA11 of FLASH, the address line A13 is connected to the address line PA12 of FLASH, the address line A14 is connected to address line PA13 of FLASH, address line A15 is connected to address line PA14 of FLASH, address line A16 is connected to address line PA15 of FLASH, address line A17 is connected to address line PA16 of FLASH, and address line A18 is connected to address of FLASH Line PA17, address line A19 is connected to address line PA18 of FLASH, address line A20 is connected to address line PA19 of FLASH, address line A21 is connected to address line PA20 of FLASH, address line A22 is connected to address line PA21 of FLASH, and data line D16 is connected to FLASH data line DQ0, data line D17 is connected to FLASH data line DQ1, data line D18 is connected to FLASH data line DQ2, data line D19 is connected to FLASH data line DQ3, data line D20 is connected to FLASH data line DQ4, Data line D21 is connected to FLASH data line DQ5, data line D22 is connected to FLASH data line DQ6, data line D23 is connected to FLASH data line DQ7, data line D24 is connected to FLASH data line DQ8, and data line D25 is connected to FLASH Data line DQ9, data line D26 is connected to FLASH data line DQ10, data line D27 is connected to FLASH data line DQ11, data line D28 is connected to FLASH data line DQ12, data line D29 is connected to FLASH data line DQ13, data The line D30 is connected to the data line DQ14 of the FLASH, the data line D31 is connected to the data line DQ15 of the FLASH, the writing control signal terminal is connected to the WE terminal of the FLASH, the reset control signal terminal is connected to the PRESET terminal of the FLASH, and the chip selection control signal terminal is connected to the The CE end of FLASH and the read control signal end are connected to the OE end of FLASH.

2. To realize the configuration operation of the soft configuration circuit, it needs to involve the pin connection of the SPARC V8 processor and the FPGA chip BQV300.

The GPIO-PIO48 pin of the SPARC V8 processor is connected to the IO_D7 pin of the FPGA, the GPIO-PIO49 pin is connected to the IO_D6 pin of the FPGA, the GPIO-PIO50 pin is connected to the IO_D5 pin of the FPGA, and the GPIO-PIO51 pin is connected to Connect to the IO_D4 pin of the FPGA, connect the GPIO-PIO52 pin to the IO_D3 pin of the FPGA, connect the GPIO-PIO53 pin to the IO_D2 pin of the FPGA, connect the GPIO-PIO54 pin to the IO_D1 pin of the FPGA, and connect the GPIO-PIO55 pin The pin is connected to the IO_D0 pin of the FPGA, the GPIO-PIO56 pin is connected to the INIT pin of the FPGA, the GPIO-PIO58 pin is connected to the DONE pin of the FPGA, the GPIO-PIO60 pin is connected to the IO_DOUT_BUSY pin of the FPGA, and the GPIO- PIO62 is connected to the IO_WRITE pin of the FPGA, the GPIO-PIO63 pin is connected to the IO_CS pin of the FPGA, the GPIO-PIO57 pin is connected to the PROGRAM pin of the FPGA, and the GPIO-PIO61 pin is connected to the GCLK pin of the FPGA.

3. Soft configuration process

(1) Arbitrarily generate .bit files in the ISE10.1 environment and store them in the external memory FLASH. Power on the SPARC V8 processor, FLASH, and FPGA chip. After power-on, the SPARC V8 processor reads the .bit file from the FLASH. Refer to the Xilinx company.bit file format, remove the invalid information in the header of the file, and extract Valid data information, and generate a configuration array according to the configuration format of the XilinxVirtex chip.

(2) Configure the GPIO-PIO57 pin of the SPARC V8 processor as an output, first write "1" into the data register of the GPIO-PIO57 pin, so that the PROGRAM pin input of the FPGA chip is at a high level. After one clock cycle, write "0" into the data register of the GPIO-PIO57 pin of the SPARC V8 processor, so that the PROGRAM pin input of the FPGA is low level to start the reset configuration logic.

(3) After 2us, configure the GPIO-PIO56 of the SPARC V8 processor as the input to continuously monitor the voltage change of the INIT pin of the FPGA. When the INIT pin changes from low level to high level, GPIO-PIO56 When the input of the input changes from "0" to "1", it means that the operation of clearing the internal registers of the FPGA is completed; if the INIT pin of the FPGA is at a high level, repeat steps (1)-step (2) until the INIT pin of the FPGA There is a transition from low level to high level;

(4) Configure the GPIO-PIO63 pin of the SPARC V8 processor as an output, and write "0" to the data register of the SPARC V8 processor GPIO-PIO63, so that the IO_CS input of the FPGA is low;

(5) After one clock cycle, configure the GPIO-PIO62 pin of the SPARC V8 processor as an output, and write "0" to the data register of the SPARCV8 processor GPIO-PIO62, so that the IO_WRITE pin of the FPGA is low;

(6) Traversing the configuration information array and according to the configuration information array, continuously configure the GPIO registers in the SPARC V8 processor to make the 15 pins in the GPIO group generate clock signals, read and write control signals, chip selection control signals, and configuration enable signals , Eight data signals are sent to FPGA.

a. By periodically configuring the GPIO-PIO61 pin register of the SPARC V8 processor, the clock signal GCLK of the FPGA is provided by changing the control register and the data register. Every interval of 1 clock cycle, alternately make the GPIO-PIO61 pin of the SPARCV8 processor output "1" and "0". Each alternate cycle consists of three operations: configure the GPIO-PIO61 pin of the SPARC V8 processor as an output; write "1" to the data register of the GPIO-PIO61 of the SPARC V8 processor, so that the GCLK input of the FPGA is High level; the next clock cycle writes "0" to the data register of the GPIO-PIO61 of the SPARC V8 processor, so that the GCLK input of the FPGA is low level.

b. Configure the GPIO-PIO63 pin of the SPARC V8 processor as an output, write "0" to the data register of the GPIO-PIO63 of the SPARC V8 processor, and make the IO_CS input of the FPGA low; configure the GPIO of the SPARC V8 processor -PIO62 pin is output, and write "0" to the data register of SPARC V8 processor GPIO-PIO62, so that FPGA's IO_WRITE pin is low level; configure the GPIO-PIO57 pin of SPARC V8 processor as output, and Write "1" to the data register of the GPIO-PIO57 of the SPARC V8 processor to make the PROGRAM pin of the FPGA a high level.

c. Take out the data in turn from the configuration information array, and when the GCLK signal is high, write it into GPIO-PIO48, GPIO-PIO49, GPIO-PIO50, and GPIO of the SPARC V8 processor from high to low in binary format -PIO51, GPIO-PIO52, GPIO-PIO53, GPIO-PIO54, GPIO-PIO55 enable the 8-way IO_D7, IO_D6, IO_D5, IO_D4, IO_D3, IO_D2, IO_D1, IO_D0 signals of the FPGA to receive configuration data. Repeat this process until all configuration information arrays are traversed.

d. During the execution of (c), continuously monitor the IO_DOUT_BUSY pin of the FPGA. If the IO_DOUT_BUSY is at a high level, the configuration data at this time will not be recognized by the FPGA. , GPIO-PIO51, GPIO-PIO52, GPIO-PIO53, GPIO-PIO54, GPIO-PIO55 data registers write the current configuration data until the IO_DOUT_BUSY signal output is low level.

(7) Configure the GPIO-PIO62 pin of the SPARC V8 processor as an output, write "1" to the data register of the GPIO-PIO62 of the SPARC V8 processor, and make the IO_WRITE pin input of the FPGA a high level; configure the SPARC V8 processor The GPIO-PIO63 pin is an output, write "1" to the data register of the SPARC V8 processor GPIO-PIO63, so that the FPGA IO_CS pin input is high;

(8) Configure the GPIO-PIO58 pin of the SPARC V8 processor as an input, and continuously detect the output of the DONE control signal of the FPGA. If the level is high, the configuration is completed, otherwise continue to wait until the DONE signal is high. If the waiting time exceeds the threshold of 1s, repeat steps (1) to (7).

The content that is not described in detail in the description of the present invention belongs to the well-known technology of those skilled in the art.

Claims (1)

1. a kind of SoPC chips Autonomous Reconfiguration soft configuration method, it is characterised in that comprise the following steps：

(1) SPARC V8 processor address lines Ai is connected to FLASH address wire PAi-1, i=1,2,3 ..., 22, data wire Dj is connected to FLASH data wire DQg, j=16,17, and 18 ..., 31, g=0,1,2 ..., 15, the connection of write control signal end To FLASH WE ends, reseting controling signal end is connected to FLASH PRESET ends, and piece selects control signal end to be connected to FLASH's CE ends, read control signal end are connected to FLASH OE ends；

(2) the GPIO-PIO48 pins of SPARC V8 processors are connected to FPGA IO_D7 pins, GPIO-PIO49 pins connect FPGA IO_D6 pins are connected to, GPIO-PIO50 pins are connected to FPGA IO_D5 pins, and GPIO-PIO51 pins are connected to FPGA IO_D4 pins, GPIO-PIO52 pins are connected to FPGA IO_D3 pins, and GPIO-PIO53 pins are connected to FPGA IO_D2 pins, GPIO-PIO54 pins are connected to FPGA IO_D1 pins, and GPIO-PIO55 pins are connected to FPGA IO_ D0 pins, GPIO-PIO56 pins are connected to FPGA INIT pins, and GPIO-PIO58 pins are connected to FPGA DONE pins, GPIO-PIO60 pins are connected to FPGA IO_DOUT_BUSY pins, and the IO_WRITE that GPIO-PIO62 is connected to FPGA draws Pin, GPIO-PIO63 pins are connected to FPGA IO_CS pins, and GPIO-PIO57 pins are connected to FPGA PROGRAM pins, GPIO-PIO61 pins are connected to FPGA GCLK pins；

(3) .bit files are arbitrarily generated in ISE10.1 development environments and delivered in FLASH, to SPARCV8 processors, FLASH, FPGA carries out electricity, and SPARC V8 processors read .bit files from FLASH, according to .bit file formats and Virtex chips Configuration format generation configuration information array；

(4) the GPIO-PIO57 pins for setting SPARC V8 processors are output, to the data register of GPIO-PIO57 pins Middle write-in " 1 ", then writes " 0 " into the data register of the GPIO-PIO57 pins of SPARC V8 processors, sets SPARC The GPIO-PIO56 pins of V8 processors are input, monitor the voltage change of FPGA INIT pins；

(5) if INIT pins are changed into high level from low level, it is transferred to step (6)；If FPGA INIT pins are high electricity Flat, then repeat step (3)-step (4), goes to step after FPGA INIT pins occur from low level to the saltus step of high level (6)；

(6) SPARC V8 processor GPIO-PIO63 pins are set for output, then to SPARC V8 processors GPIO-PIO63 Data register write-in " 0 ", SPARC V8 processor GPIO-PIO62 pin are set after a clock cycle for output, and to SPARC V8 processors GPIO-PIO62 data register write-in " 0 "；

(7) the GPIO-PIO61 pins for setting SPARC V8 processors are output, to the GPIO-PIO61 of SPARC V8 processors Data register write-in " 1 ", next clock cycle writes to the GPIO-PIO61 of SPARC V8 processors data register Enter " 0 ", write " 1 " and " 0 " alternately to the GPIO-PIO61 of SPARC V8 processors data register, and perform simultaneously Step (8)-step (9)；

(8) the GPIO-PIO63 pins for setting SPARC V8 processors are output, to SPARC V8 processors GPIO-PIO63's Data register writes " 0 ", and the GPIO-PIO62 pin for setting SPARC V8 processors are output, and to SPARC V8 processors GPIO-PIO62 data register write-in " 0 ", the GPIO-PIO57 pins for setting SPARC V8 processors are output, and to The GPIO-PIO57 of SPARC V8 processors data register write-in " 1 "；

(9) data are taken out successively from configuration information array, when FPGA GCLK signals are high level, with the form of 2 systems GPIO-PIO48, GPIO-PIO49, GPIO-PIO50, GPIO-PIO51, GPIO- of SPARC V8 processors are write from high to low PIO52, GPIO-PIO53, GPIO-PIO54, GPIO-PIO55, while FPGA IO_DOUT_BUSY pins are persistently monitored, such as Fruit IO_DOUT_BUSY pins are high level, then continue to GPIO-PIO48, GPIO-PIO49, GPIO-PIO50, GPIO- Write-in is currently configured number in PIO51, GPIO-PIO52, GPIO-PIO53, GPIO-PIO54, GPIO-PIO55 data register According to until IO_DOUT_BUSY signal outputs are low level, if IO_DOUT_BUSY is low level, being transferred to step (10)；

(10) SPARC V8 processor GPIO-PIO62 pins are set for output, to SPARC V8 processors GPIO-PIO62 number " 1 " is write according to register, then SPARC V8 processor GPIO-PIO63 pins are set for output, to SPARC V8 processors GPIO-PIO63 data register write-in " 1 "；

(11) SPARC V8 processor GPIO-PIO58 pins are configured as input, persistently detection FPGA DONE control signals is defeated Go out, if DONE control signals level is height, soft configuration circuit is completed, if DONE control signals level is not height, after It is continuous to wait, until DONE signals are height, when threshold value of the stand-by period beyond setting, then repeat (1) to (10) until DONE signals are height.