CN201876872U - Large-volume data acquisition device - Google Patents
Large-volume data acquisition device Download PDFInfo
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- CN201876872U CN201876872U CN 201020653087 CN201020653087U CN201876872U CN 201876872 U CN201876872 U CN 201876872U CN 201020653087 CN201020653087 CN 201020653087 CN 201020653087 U CN201020653087 U CN 201020653087U CN 201876872 U CN201876872 U CN 201876872U
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Abstract
The utility model relates to a large-volume data acquisition device, belonging to the technical field of data transmission among boards, aiming at achieving the technical goals of simplifying the electromagnetic compatible design and improving the data real-time performance. The device comprises a data acquisition main board and a plurality of expansion daughter boards. A central processing unit (CPU) and a field programmable gate array (FPGA) are arranged on the data acquisition main board. Each expansion daughter board is provided with a three-wire serial communication interface. The FPGA is provided with a plurality of serial-to-parallel conversion modules and a plurality of memory modules corresponding to the expansion daughter boards. The FPGA regularly transmits enabling signals and clock signals to the three-wire serial communication interface of each expansion daughter board. Each expansion daughter board transmits data to the corresponding serial-to-parallel conversion module according to the time sequences of the clock signals. The data is converted into parallel data by the serial-to-parallel conversion module and then the parallel data is stored in the corresponding memory module. The CPU reads the data of each expansion daughter board by accessing to each memory module. The device and a method provided by the utility model have the advantages that the electromagnetic compatible design can be simplified and the data real-time performance is high.
Description
Technical field
The utility model relates to data transmission technology between plate, particularly relates to a kind of technology of large capacity data acquisition device.
Background technology
A lot of automation equipments in the electric system all are provided with data collector, and the data acquisition amount of most equipment is all bigger.
The data collector of existing automation equipment all is made up of blocks of data collection mainboard and polylith expansion daughter board in the electric system, on the data acquisition mainboard, be provided with CPU, because the bus cycles of CPU can not extend arbitrarily, general minimum tens megahertzes of also wanting of bus speed, therefore along with the increase of expansion board number of packages amount, signal transmission path also can increase thereupon, make and adopt traditional cpu data bus to carry out mode meeting interconnected between plate owing to the frequency of transmission signals higher (being generally tens) makes transmission signals be faced with the problem of electromagnetic compatibility, if adopt traditional serial communication mode between plate then can expand daughter board and all need to increase CPU and support and can significantly increase hardware cost owing to each, and along with the increase of expanding daughter board quantity, CPU with serial communication mode in regular turn one by one visit respectively to expand the daughter board required time also longer, can have influence on the real-time of data.
The utility model content
At the defective that exists in the above-mentioned prior art, technical problem to be solved in the utility model provides a kind ofly can simplify EMC Design, and simple in structure, with low cost, large capacity data acquisition device and data transmission method thereof that real-time property is high.
In order to solve the problems of the technologies described above, a kind of large capacity data acquisition device provided by the utility model, comprise that a blocks of data is gathered mainboard and polylith is expanded daughter board, described data acquisition mainboard is provided with CPU, described CPU is provided with data-interface, every expansion daughter board is equipped with a three-way serial communication interface, the every three-way serial communication interface of expanding on the daughter board all has three terminals, be respectively the enable signal input end, clock signal input terminal, the serial data output terminal is characterized in that: also be provided with one on the described data acquisition mainboard and be used to manage the FPGA that respectively expands daughter board;
Described FPGA is provided with an enable signal output terminal, a clock signal output part, and is provided with and each the expansion a plurality of one to one strings of daughter board and modular converter, and goes here and there and a plurality of one to one memory modules of modular converter with each;
Each string and modular converter are equipped with serial datum input end, a parallel data interface;
Each memory module is equipped with a data input port, a data output, and the data output of each memory module is connected to the data-interface of CPU, and the data input port of each memory module is connected to the parallel data grabbing card of its corresponding string and modular converter;
The every serial data output terminal of expanding the three-way serial communication interface on the daughter board is connected to the also serial data input end of modular converter of its corresponding string, each enable signal input end of expanding the three-way serial communication interface on the daughter board is connected to the enable signal output terminal of FPGA, and each clock signal input terminal of expanding the three-way serial communication interface on the daughter board is connected to the clock signal input terminal of FPGA.
Large capacity data acquisition device and data transmission method thereof that the utility model provides, utilize FPGA regularly to send enable signal and clock signal to each expansion daughter board, each expands the signal that daughter board sends according to FPGA, with serial communication mode data in real time is transferred in each memory module among the FPGA and to store, CPU obtains the data of respectively expanding daughter board by visiting each memory module, owing to only installed a slice FPGA additional, each is expanded and need not to install additional CPU on the daughter board, it is relatively simple for structure, realize that cost is also lower, and owing to data between plate are transmitted with serial communication mode, therefore EMC Design is also fairly simple, and CPU is the data of visiting each daughter board by data bus, so real-time property is also higher.
Description of drawings
Fig. 1 is the structured flowchart of the large capacity data acquisition device of the utility model embodiment.
Embodiment
Below in conjunction with description of drawings embodiment of the present utility model is described in further detail, but present embodiment is not limited to the utility model, every employing analog structure of the present utility model and similar variation thereof all should be listed protection domain of the present utility model in.
As shown in Figure 1, a kind of large capacity data acquisition device that the utility model embodiment is provided, comprise that a blocks of data is gathered mainboard and polylith is expanded daughter board, described data acquisition mainboard is provided with the CPU(central processing unit), described CPU is provided with data-interface, every expansion daughter board is equipped with a three-way serial communication interface, the every three-way serial communication interface of expanding on the daughter board all has three terminals, be respectively the enable signal input end, clock signal input terminal, the serial data output terminal is characterized in that: also be provided with one on the described data acquisition mainboard and be used to manage the FPGA(programmable gate array of respectively expanding daughter board);
Described FPGA is provided with an enable signal output terminal, a clock signal output part, and is provided with and each the expansion a plurality of one to one strings of daughter board and modular converter, and goes here and there and a plurality of one to one memory modules of modular converter with each;
Each string and modular converter are equipped with serial datum input end, a parallel data interface;
Each memory module is equipped with a data input port, a data output, and the data output of each memory module is connected to the data-interface of CPU, and the data input port of each memory module is connected to the parallel data grabbing card of its corresponding string and modular converter;
The every serial data output terminal of expanding the three-way serial communication interface on the daughter board is connected to the also serial data input end of modular converter of its corresponding string, each enable signal input end of expanding the three-way serial communication interface on the daughter board is connected to the enable signal output terminal of FPGA, and each clock signal input terminal of expanding the three-way serial communication interface on the daughter board is connected to the clock signal input terminal of FPGA.
The data transmission method of the large capacity data acquisition device that the utility model embodiment is provided is characterized in that: FPGA regularly sends enable signal and clock signal to each expansion daughter board by its enable signal output terminal and clock signal output terminal;
After each is expanded the enable signal input end of the three-way serial communication interface on the daughter board and clock signal input terminal and receives the enable signal and clock signal that FPGA sends, promptly send data to corresponding string and modular converter with serial communication mode according to the sequential of the clock signal serial data output terminal by its three-way serial communication interface;
Each string and modular converter are converted to parallel data with the serial data of receiving earlier after receiving the serial data that corresponding expansion daughter board sends here, and the parallel data after will change again is sent in the memory module of correspondence and stores;
When CPU need read wherein the data of an expansion daughter board, promptly by its data-interface read with the corresponding memory module of this expansion daughter board in data.
Claims (1)
1. large capacity data acquisition device, comprise that a blocks of data is gathered mainboard and polylith is expanded daughter board, described data acquisition mainboard is provided with CPU, described CPU is provided with data-interface, every expansion daughter board is equipped with a three-way serial communication interface, the every three-way serial communication interface of expanding on the daughter board all has three terminals, be respectively enable signal input end, clock signal input terminal, serial data output terminal, it is characterized in that: also be provided with one on the described data acquisition mainboard and be used to manage the FPGA that respectively expands daughter board;
Described FPGA is provided with an enable signal output terminal, a clock signal output part, and is provided with and each the expansion a plurality of one to one strings of daughter board and modular converter, and goes here and there and a plurality of one to one memory modules of modular converter with each;
Each string and modular converter are equipped with serial datum input end, a parallel data interface;
Each memory module is equipped with a data input port, a data output, and the data output of each memory module is connected to the data-interface of CPU, and the data input port of each memory module is connected to the parallel data grabbing card of its corresponding string and modular converter;
The every serial data output terminal of expanding the three-way serial communication interface on the daughter board is connected to the also serial data input end of modular converter of its corresponding string, each enable signal input end of expanding the three-way serial communication interface on the daughter board is connected to the enable signal output terminal of FPGA, and each clock signal input terminal of expanding the three-way serial communication interface on the daughter board is connected to the clock signal input terminal of FPGA.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201020653087 CN201876872U (en) | 2010-12-10 | 2010-12-10 | Large-volume data acquisition device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201020653087 CN201876872U (en) | 2010-12-10 | 2010-12-10 | Large-volume data acquisition device |
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| CN201876872U true CN201876872U (en) | 2011-06-22 |
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| CN 201020653087 Expired - Fee Related CN201876872U (en) | 2010-12-10 | 2010-12-10 | Large-volume data acquisition device |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102012879A (en) * | 2010-12-10 | 2011-04-13 | 上海申瑞电力科技股份有限公司 | High-capacity data acquisition device and data transmission method thereof |
| CN103353725A (en) * | 2013-03-19 | 2013-10-16 | 中国科学院声学研究所 | PCI interface protocol based array expandable data collection system realized by adopting FPGA (field programmable gate array) |
| CN104484301A (en) * | 2014-12-25 | 2015-04-01 | 南京因泰莱电器股份有限公司 | FPGA-based (Field Programmable Gate Array-based) IO (Input/Output) bus device with automatic recognition function |
| CN106371530A (en) * | 2016-09-07 | 2017-02-01 | 英业达科技有限公司 | Server |
| CN111258941A (en) * | 2018-12-03 | 2020-06-09 | 中国电信股份有限公司 | System for outputting digital signal and method for outputting digital signal |
-
2010
- 2010-12-10 CN CN 201020653087 patent/CN201876872U/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102012879A (en) * | 2010-12-10 | 2011-04-13 | 上海申瑞电力科技股份有限公司 | High-capacity data acquisition device and data transmission method thereof |
| CN103353725A (en) * | 2013-03-19 | 2013-10-16 | 中国科学院声学研究所 | PCI interface protocol based array expandable data collection system realized by adopting FPGA (field programmable gate array) |
| CN104484301A (en) * | 2014-12-25 | 2015-04-01 | 南京因泰莱电器股份有限公司 | FPGA-based (Field Programmable Gate Array-based) IO (Input/Output) bus device with automatic recognition function |
| CN104484301B (en) * | 2014-12-25 | 2017-08-11 | 南京因泰莱电器股份有限公司 | A kind of IO bus units based on FPGA with self-recognition function |
| CN106371530A (en) * | 2016-09-07 | 2017-02-01 | 英业达科技有限公司 | Server |
| CN111258941A (en) * | 2018-12-03 | 2020-06-09 | 中国电信股份有限公司 | System for outputting digital signal and method for outputting digital signal |
| CN111258941B (en) * | 2018-12-03 | 2021-11-26 | 中国电信股份有限公司 | System for outputting digital signal and method for outputting digital signal |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI SUNRISE PROTECTIVE RELAY ELECTRIC CO.,LTD Free format text: FORMER OWNER: SHANGHAI SUNRISE POWER AUTOMATION CO., LTD. Effective date: 20130220 |
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| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20130220 Address after: 200233, building 5, building 470, No. 12, Guiping Road, Shanghai, Xuhui District 200233 Patentee after: Shanghai Sunrise Power Technology Co., Ltd. Address before: 200233 Shanghai City, Xuhui District Road No. 159 15 Tianzhou room unit 1301 Patentee before: Shanghai Sunrise Power Automation Co., Ltd. |
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| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20170109 Address after: 200233 Shanghai city Xuhui District caodong East No. 81 room 206 Patentee after: Cloud power Polytron Technologies Inc Address before: 200233 Guiping Road, Xuhui District, No. 470, building 12, building 5, building Patentee before: Shanghai Sunrise Power Technology Co., Ltd. |
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| TR01 | Transfer of patent right |
Effective date of registration: 20170606 Address after: 200000 No. 179 Shipyard Road, Shanghai Patentee after: Shanghai Qiaersi electric (Group) Co. Ltd. Address before: 200233 Shanghai city Xuhui District caodong East No. 81 room 206 Patentee before: Cloud power Polytron Technologies Inc |
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| TR01 | Transfer of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110622 Termination date: 20171210 |
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| CF01 | Termination of patent right due to non-payment of annual fee |