CN113433858A - Automatic monitoring system for satellite-borne FPGA chip - Google Patents
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Abstract
The invention discloses an automatic monitoring system of a satellite-borne FPGA chip, which comprises: the superior system is used for sending monitoring instructions and comprehensively receiving monitoring information; the monitoring FPGA is used for receiving the configuration file information sent by the upper-level system command and configuration file recombination sending module to monitor the FPGA to be tested and feeding back the monitoring information to the upper-level system; the configuration file recombination and sending module is used for recombining the configuration file of the monitoring FPGA and sending the recombined configuration file to the monitoring FPGA from the RS422 data link; the Flash memory chip is used for storing the configuration information written into the monitoring FPGA; and the power supply system is used for providing required electric energy for the FPGA to be detected, the Flash storage chip and the monitoring FPGA. The invention can dynamically monitor the satellite high-speed data processing chip in real time and has the advantages of high transmission rate, accurate data acquisition and high measurement precision.
Description
Technical Field
The invention relates to the technical field of FPGA chips, in particular to an automatic monitoring system of a satellite-borne FPGA chip.
Background
The requirements on functions such as data processing rate, transmission mode, task requirements and the like of satellite data transmission products are continuously improved, and the logic resource consumption, the operation speed and the power consumption of FPGA chips of core function devices of the products are increased along with the requirements. The vacuum environment is unfavorable for heat dissipation, and excessive heat accumulation easily causes thermal breakdown or electric breakdown, causes the chip to lose efficacy. Meanwhile, the FPGA with high speed and resource requirement takes an SRAM type as the best, the logic setting information of the FPGA based on the technology cannot be stored after the FPGA is powered off, and the FPGA can operate after the configuration information is written from the outside when the FPGA is powered on every time.
Disclosure of Invention
The invention provides an automatic monitoring system of a satellite-borne FPGA chip, aiming at continuously improving the processing data rate, the transmission mode and the task requirement of a satellite data transmission product.
In order to solve the technical problems, the technical scheme of the invention is as follows:
an automatic monitoring system of a satellite-borne FPGA chip comprises:
the superior system is used for sending monitoring instructions and receiving monitoring information in a comprehensive mode;
the monitoring FPGA is used for receiving the command of the superior system and the configuration file information sent by the configuration file recombination sending module to monitor the FPGA to be detected and feed back the monitoring information to the superior system;
the configuration file reorganization and sending module is used for reorganizing the configuration files of the monitoring FPGA and sending the configuration files to the monitoring FPGA from the RS422 data link;
the Flash memory chip is used for storing the configuration information written into the monitoring FPGA;
and the power supply system is used for supplying required electric energy to the FPGA to be detected, the Flash storage chip and the monitoring FPGA.
Preferably, the monitoring FPGA includes:
the remote control and remote measurement processing module is used for receiving a superior system command to monitor the FPGA to be measured and feeding back monitoring information;
the temperature acquisition module is used for acquiring the core temperature of the chip when the FPGA to be detected runs and feeding back temperature information to the remote control and remote measurement processing module;
the file uploading module is used for receiving the configuration file information sent by the configuration file reorganization sending module and storing the configuration file information in the Flash storage chip;
the configuration information writing module is used for reading configuration file information from the Flash memory chip and programming the FPGA to be tested on line;
and the system initialization module is used for initializing the system, starting the FPGA to be tested within a reasonable judgment time and judging a command to restart all functions of the product.
Preferably, the telemetry processing module includes:
the remote measurement acquisition unit is in butt joint with the FPGA to be measured, inquires the working state in real time, is in butt joint with the temperature acquisition module, and finally summarizes and calculates all remote measurement data to form a data frame with a check sum;
the protocol processing unit concretizes the communication convention and schedules duplex data;
the remote control analysis unit is used for judging the correctness of the received data verification and verifying whether the instruction content is in the instruction set appointed by the communication, the inspected instruction is sent to the instruction forwarding unit for further processing and distribution, and unqualified instruction data are directly discarded;
the first serial-parallel conversion unit is used for performing serial-parallel conversion on the received data and sending the data to the remote control analysis unit or the superior system;
and the instruction forwarding unit is connected with the FPGA to be tested with high reliability and is used for performing triple modular redundancy backup at the same time.
Preferably, the file annotation module includes:
the second serial-parallel conversion unit is used for performing serial-parallel conversion on the configuration file information sent by the configuration file recombination sending module;
the data analysis unit is used for receiving the parallel data output by the second serial-parallel conversion unit, caching and inquiring a file header, checking whether the data stream is data or a command, extracting effective data from the rear wing data stream, generating an effective gating signal according to a preset time axis, and providing the data to the data storage unit;
and the data storage unit starts the storage array according to the instruction of the Flash storage chip and writes the data provided by the data analysis unit according to bytes.
Preferably, the monitoring system comprises a voltage acquisition module; the voltage acquisition module directly acquires the power supply voltage information of the core of the chip when the FPGA to be tested operates, and feeds back the voltage information to the remote control and remote measurement processing module.
Preferably, the monitoring FPGA is an antifuse type FPGA or a Flash type FPGA.
Preferably, the monitoring FPGA has a specification of 50 ten thousand doors or a specification of 100 ten thousand doors.
Compared with the prior art, the invention has the beneficial effects that:
the invention dynamically monitors the running state, temperature information, channel number and the like of the satellite high-speed data processing chip in real time, provides a working mode and command processing and sending for the chip, provides running file storage and automatic programming after starting up, has the capabilities of analyzing commands and executing feedback communication with high reliability, automatically measures the internal temperature of the FPGA in real time under the condition of not needing an external analog-to-digital conversion chip, and plays an active role in monitoring the working condition of aerospace products;
the design system of the invention shares part of the logic resource requirements, so that the monitoring FPGA which bears the main function can be concentrated on high-speed data processing;
the invention also solves the problem of writing in the configuration information of the SRAM type FPGA when the SRAM type FPGA is started.
Drawings
FIG. 1 is a schematic block diagram of an automatic monitoring system of a satellite-borne FPGA chip according to the present invention;
FIG. 2 is a functional block diagram of a telemetry processing module in accordance with an embodiment of the present invention;
fig. 3 is a schematic block diagram of a temperature acquisition module according to an embodiment of the present invention.
Detailed Description
The following further describes embodiments of the present invention with reference to the drawings. It should be noted that the description of the embodiments is provided to help understanding of the present invention, but the present invention is not limited thereto. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, an automatic monitoring system for a satellite-borne FPGA chip includes:
the superior system is used for sending monitoring instructions and receiving monitoring information in a comprehensive mode;
the monitoring FPGA is used for receiving the configuration file information sent by the upper-level system command and configuration file recombination sending module to monitor the FPGA to be detected and feeding back the monitoring information to the upper-level system;
the configuration file reorganization sending module is used for reorganizing and sending the configuration file of the FPGA, extracting each 4096 Byte data to form a data frame, adding a file header, a frame header and a tail remainder for completion, forming a code stream with a certain baud rate and sending the code stream to the RS422 data link;
the Flash memory chip is used for storing the configuration information written into the monitoring FPGA; the chip specification can be selected and matched according to the size of the file, the file can be repeatedly erased and written, and the normal work of the tested chip is not influenced when the file is changed;
and the power supply system is used for supplying required electric energy to the FPGA to be detected, the Flash storage chip and the monitoring FPGA.
In the embodiment, the system does not need to adopt an external analog-to-digital converter ADC or a temperature sensor to measure the temperature; the chip type selection on the hardware has multiple specification compatibility; the system has the functions of automatically programming, storing and updating the configuration file after the FPGA is powered on, and can reset or suspend all functions of the product at any time when the temperature is too high or the superior equipment sends out a requirement according to a judgment result, so that the system stability reaches the highest.
With continued reference to fig. 1, monitoring the FPGA includes:
the remote control and remote measurement processing module is used for receiving a superior system command to monitor the FPGA to be measured and feeding back monitoring information;
the temperature acquisition module is used for acquiring the core temperature of the chip when the FPGA to be measured operates, feeding back 12bit digital quantity temperature information to the remote control and remote measurement processing module, and converting an actual temperature value through a formula on the ground;
the file uploading module is used for receiving the configuration file information sent by the configuration file reorganization sending module and storing the configuration file information in the Flash storage chip;
the configuration information writing module is used for reading configuration file information from the Flash memory chip and programming the FPGA to be tested on line;
and the system initialization module is used for initializing the system, starting the FPGA to be tested within a reasonable judgment time and judging a command to restart all functions of the product.
The working process is as follows:
step 2, timing for 0.5 second to complete, wherein the time aims to avoid the micro voltage fluctuation of a power chip caused by the simultaneous starting of a plurality of supplied electric equipment, so that the low possible time sequence error phenomenon is caused; the system starts to read out the content of the configuration file from the lookup table one by one address in the Flash memory chip or when a bad block is encountered, and sends a clock, data and control signals to a SelectMap bus connected with the SRAM FPGA according to a specified time sequence; in the period, all operations of the file uploading module are forbidden; after all the chips are finished, the tested chip starts to operate;
step 3, the system monitors that the FPGA to be measured works normally and then the kernel temperature measuring module is started;
step 4, the system processes the annotation request of the configuration file at the moment; after receiving a re-injection command of a superior system, the system firstly erases an original file stored in a Flash memory chip, then carries out self-check on the memory chip and returns a self-check result and a bad block table to superior communication equipment; at the moment, the configuration file code stream is sent from the ground test equipment, the system receives, analyzes and verifies the configuration file code stream, and the data meeting the requirements are written into the Flash memory chip.
And at any time after the system operates, the telemetering remote control processing module responds to the communication request of the superior system in a response mode. At any time after the system runs, the system initialization module responds to the restart command of the upper level, namely returning to the step 1.
Referring to fig. 2, the communication rate of the remote telemetry processing module can be selected and easily adjusted according to actual conditions; the data protocol is agreed by both parties, the receiver checks the byte and the full data frame after receiving the command or the sender receives the feedback, and returns the check result, and judges whether to start the retransmission mechanism according to the check result; the data was checked a total of 3 times to ensure error free. The method specifically comprises the following steps:
the remote measurement acquisition unit is in butt joint with the FPGA to be measured, inquires the working state in real time, is in butt joint with the temperature acquisition module, and finally gathers and calculates all remote measurement data to form a data frame with a check sum;
the protocol processing unit concretizes the communication convention, schedules duplex data and plays a role in commanding the whole communication process; preferably, according to the level required by the specific communication protocol, the protocol processing unit can be changed according to the requirements of both parties, and part of handshake protocol content is gated or ignored according to the requirements; the essential contents of the instruction and the remote measurement can be customized and are not limited by the communication time length and the length of the data frame;
the remote control analysis unit is used for judging the correctness of the received data verification and verifying whether the instruction content is in the instruction set appointed by the communication, the inspected instruction is sent to the instruction forwarding unit for further processing and distribution, and unqualified instruction data are directly discarded;
the first serial-parallel conversion unit is used for performing serial-parallel conversion on the received data and sending the data to the remote control analysis unit or the superior system, and the transmission rate of the data can be adjusted without any influence on a high-level communication protocol;
and the instruction forwarding unit is connected with the FPGA to be tested with high reliability and performs triple modular redundancy backup at the same time, so that the correctness of an instruction transmission link on the satellite-ground link is ensured.
In this embodiment, the valid information sent by the superior device to the system is divided into two types: one is a command, which is setting information for a product operation mode, a data rate, an output power, and the like; the other type is a state query request, and the system is required to reply the condition information of the current working mode, the data rate, the output power, the core temperature and the like of the product.
The communication process of the remote control and telemetry processing module is as follows:
step 2, looking up the instruction table, and regarding the following conditions as legal contents in the register CMD: 1) the format requirements of switching commands such as the working mode or the speed of a product are met, and the values are all in an executable range, and the communication superior device is judged to send a command; 2) if the content of the state query request is completely consistent with that of the state query request, the communication superior device is judged to send the state query request;
and 3, performing overall check on the whole communication sequence according to the protocol no matter whether the command or the acquisition request is received, wherein if the check sum does not accord with the transmission, the error occurs in the transmission. The system needs to avoid the possibility of operation errors and prompts the superior equipment to retransmit;
step 4, if the command sequence is completely legal and correct, executing the command, and sending back information of 'command check is correct and executed' to the superior equipment; if the command sequence is illegal or incorrect, sending 'command verification is incorrect and execution refusing' information to the upper-level equipment;
step 5, if the state query request is judged, the system queries the working state of the product, packs the product and sends back the telemetering information of the superior equipment;
step 6, within 200 milliseconds of sending the telemetering information, the superior device should return feedback to the state inquiry request, and the feedback is divided into two types of 'telemetering information check is correct' or 'telemetering information check is wrong'; and if the check error information is received or no response is given after 200 milliseconds timeout, the system retransmits the working state information.
The information of the current working state command of the cache product is stored in 3 registers currant _ 1-currant 3, namely triple modular redundancy backup, which is very difficult to make mistakes aiming at the conditions of single particles, radiation damage and the like of the space environment. The output of the control command is decoded according to the values of currant _1 to currant 3. The output of control command and feedback of working state are passed through 12 mutually independent signal lines, and as an improvement, it can use single-level control, or grouping of several levels, and combination of several high-low level coding modes to code effective information of working mode, speed and power, etc.
In one embodiment, the file annotation module comprises:
the second serial-parallel conversion unit is used for performing serial-parallel conversion on the configuration file information sent by the configuration file recombination sending module;
the data analysis unit is used for receiving the parallel data output by the second serial-parallel conversion unit, caching and inquiring the file header, checking whether the data stream is data or a command, extracting effective data from the rear wing data stream, generating an effective gating signal according to a preset time axis, and providing the data to the data storage unit;
and the data storage unit starts the storage array according to the instruction of the Flash storage chip and writes the data provided by the data analysis unit according to bytes.
In one embodiment, the automatic monitoring system of the satellite-borne FPGA chip comprises a voltage acquisition module; the voltage acquisition module directly acquires the power supply voltage information of the core of the chip when the FPGA to be tested operates, and feeds back the voltage information to the remote control and remote measurement processing module.
In this embodiment, the voltage acquisition module may be configured to acquire the core power supply voltage information of the chip by the same method as that applied by the temperature acquisition module, and provide more operation health information of the chip.
In one embodiment, the monitoring FPGA is an antifuse-type FPGA or a Flash-type FPGA having a specification of 50 ten thousand gates or 100 ten thousand gates.
In this embodiment, the monitoring FPGA may be an antifuse-type FPGA with a specific specification of AX500-1PQ208I, or a Flash-type FPGA, such as an A3PE3000 series.
Referring to fig. 3, the system is directly connected to the JTAG interface of the tested FPGA, and the signals are: clock TCK, control TMS, data TDI, and TDO. The JTAG interface and the XADC register of the FPGA are operated according to the design of a chip manufacturer, and various kernel control registers of the FPGA are addressed and read-write operated through different arrangement combinations of high-low overturn of a TMS signal line. The specific working process of the temperature acquisition module is as follows:
and 2, periodically reading the value of the state register of the XADC, wherein the corresponding address of the kernel temperature is 00 h. The original data is a 12-bit serial signal, and the system converts the original data into parallel data and feeds the parallel data back to a data frame of product state information.
The design of the monitoring system comprises a product working mode, a data rate, a chip core temperature, output power and the like, and reflects the data as telemetering quantity to form a data frame for downloading; the design subsystem of the monitoring system shares part of the logic resource requirements, so that the monitoring FPGA bearing the main function can be concentrated on high-speed data processing; the monitoring system simultaneously solves the problem of writing in configuration information of the SRAM type FPGA when the SRAM type FPGA is started.
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the described embodiments. It will be apparent to those skilled in the art that various changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, and the scope of protection is still within the scope of the invention.
Claims (7)
1. The utility model provides a satellite-borne FPGA chip automatic monitoring system which characterized in that includes:
the superior system is used for sending monitoring instructions and receiving monitoring information in a comprehensive mode;
the monitoring FPGA is used for receiving the command of the superior system and the configuration file information sent by the configuration file recombination sending module to monitor the FPGA to be detected and feed back the monitoring information to the superior system;
the configuration file reorganization and sending module is used for reorganizing the configuration files of the monitoring FPGA and sending the configuration files to the monitoring FPGA from the RS422 data link;
the Flash memory chip is used for storing the configuration information written into the monitoring FPGA;
and the power supply system is used for supplying required electric energy to the FPGA to be detected, the Flash storage chip and the monitoring FPGA.
2. The automatic monitoring system of the FPGA chip on-board of claim I, wherein the FPGA monitoring system comprises:
the remote control and remote measurement processing module is used for receiving a superior system command to monitor the FPGA to be measured and feeding back monitoring information;
the temperature acquisition module is used for acquiring the core temperature of the chip when the FPGA to be detected runs and feeding back temperature information to the remote control and remote measurement processing module;
the file uploading module is used for receiving the configuration file information sent by the configuration file reorganization sending module and storing the configuration file information in the Flash storage chip;
the configuration information writing module is used for reading configuration file information from the Flash memory chip and programming the FPGA to be tested on line;
and the system initialization module is used for initializing the system, starting the FPGA to be tested within a reasonable judgment time and judging a command to restart all functions of the product.
3. The automatic monitoring system of the FPGA chip on board of claim 2, wherein the remote telemetry processing module comprises:
the remote measurement acquisition unit is in butt joint with the FPGA to be measured, inquires the working state in real time, is in butt joint with the temperature acquisition module, and finally summarizes and calculates all remote measurement data to form a data frame with a check sum;
the protocol processing unit concretizes the communication convention and schedules duplex data;
the remote control analysis unit is used for judging the correctness of the received data verification and verifying whether the instruction content is in the instruction set appointed by the communication, the inspected instruction is sent to the instruction forwarding unit for further processing and distribution, and unqualified instruction data are directly discarded;
the first serial-parallel conversion unit is used for performing serial-parallel conversion on the received data and sending the data to the remote control analysis unit or the superior system;
and the instruction forwarding unit is connected with the FPGA to be tested with high reliability and is used for performing triple modular redundancy backup at the same time.
4. The automatic monitoring system of the on-board FPGA chip of claim 3, wherein the file annotation module comprises:
the second serial-parallel conversion unit is used for performing serial-parallel conversion on the configuration file information sent by the configuration file recombination sending module;
the data analysis unit is used for receiving the parallel data output by the second serial-parallel conversion unit, caching and inquiring a file header, checking whether the data stream is data or a command, extracting effective data from the rear wing data stream, generating an effective gating signal according to a preset time axis, and providing the data to the data storage unit;
and the data storage unit starts the storage array according to the instruction of the Flash storage chip and writes the data provided by the data analysis unit according to bytes.
5. The automatic monitoring system of the satellite-borne FPGA chip according to claim 1, characterized by comprising a voltage acquisition module; the voltage acquisition module directly acquires the power supply voltage information of the core of the chip when the FPGA to be tested operates, and feeds back the voltage information to the remote control and remote measurement processing module.
6. The automatic monitoring system of the on-board FPGA chip of claim 1, wherein the monitoring FPGA is an antifuse-type FPGA or a Flash-type FPGA.
7. The automatic monitoring system of the on-board FPGA chip as recited in claim 1, wherein the monitoring FPGA is in a specification of 50 ten thousand doors or in a specification of 100 ten thousand doors.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117539826A (en) * | 2023-11-10 | 2024-02-09 | 中国科学院国家空间科学中心 | JTAG-based satellite-borne SRAM type FPGA loading configuration system |
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Application publication date: 20210924 |