CN102135927A - Method and device for system booting based on NAND FLASH - Google Patents
Method and device for system booting based on NAND FLASH Download PDFInfo
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- CN102135927A CN102135927A CN2011101117517A CN201110111751A CN102135927A CN 102135927 A CN102135927 A CN 102135927A CN 2011101117517 A CN2011101117517 A CN 2011101117517A CN 201110111751 A CN201110111751 A CN 201110111751A CN 102135927 A CN102135927 A CN 102135927A
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Abstract
The invention provides a method and a device for system booting based on NAND FLASH. The method comprises the steps of: storing a plurality of boost programs in NAND FLASH in advance, carrying out offset operation on an original address sent to the NAND FLASH by a CPU (Central Processing Unit) by using a logic chip in the process of system booting in order to obtain an unread boot program address; and reading and executing the unread boot program in the NAND FLASH by the CPU, judging that the system booting is successful if the execution is successful, otherwise, restarting the CPU for trying the system booting again until the system booting is successful, or judging that the system booting fails in the event that all the boot programs are failed to execute. According to the invention, backup starting of the boot programs can be realized by replacing the read boot program address.
Description
Technical field
The present invention relates to the bootstrap technique of computer system, particularly a kind of based on the bootstrap technique and the device of non-flash memory (NANDFLASH).
Background technology
At the beginning of system start-up, the internal memory of system is not directly read-write, does not have the kernel code that can carry out in the internal memory yet, and this just need carry out system bootstrap.System bootstrap is meant the boot of operation before operating system nucleus operation, by boot, initiating hardware equipment, sets up the mapping graph of memory headroom, for final call operation system kernel is ready to correct environment.Boot leaves on the non-volatile memory apparatus usually.
Present non-volatile memory apparatus mainly comprises or non-flash memory (NOR FLASH) and with two kinds of non-flash memories (NAND FLASH).The interface of NOR FLASH is by address bus, control signal wires such as data bus and reading and writing, sheet choosing are formed, interface read-write control timing is also identical with the RAM chip, can carry out (XIP) operation in the chip of code, therefore becomes main flow system bootstrap storage chip.The interface of NANDFLASH does not have the differentiation of address bus and data bus as shown in Figure 1, to the read-write operation of data all by the serial operation of I/O bus.Read the data of NAND FLASH, need to send the read operation order earlier and pass through the address that reading of data is wanted in the input of I/O bus, again by I/O bus sense data, read-write operation is different with the read-write operation of RAM chip, can't realize the XIP operation.
Compare with NOR FLASH, NAND FLASH has higher storage density and than the advantage of long life, therefore, also has increasing CPU to support NAND FLASH as the system bootstrap storage chip.But there is following problem in NAND FLASH as the system bootstrap storage chip in start-up course:
(1) bad piece problem: because the process characteristic of NAND FLASH, bad piece problem is inevitable.Erase operation to NAND FLASH is that the storage unit full recovery is become the logical one level, and when the page or leaf that can not be resumed was arranged in the data block of NAND FLASH, this piece was exactly a bad piece.Bad piece can not be used again, identifies by self oob (out of band) zone.
(2) bit flipping: data owing to the charge storing unit dispose procedure, the problem of bit flipping can occur when keeping and reading, cause the unusual of data.The method that solves the bit flipping problem is the ECC at this page data of the oob of each page regional record, the correction action when being used to read, the reliability of assurance data.
(3) backup that can't realize guidance code is carried out: NAND FLASH does not support the random access of data, can't reach as the connected mode of NOR FLASH by the modified address bus to change the start-up code position, backs up the purpose of startup.
Because the existence of above several problems, there is bigger risk in the application of NAND FLASH aspect system bootstrap, bit flipping and bad piece problem may cause the mistake of run time version, can not support linear access at random as NOR FLASH, also the just directly backup of code section startup.
In the prior art, can realize by connected mode as shown in Figure 2 starting, also can realize by connected mode as shown in Figure 3 starting from NAND FLASH from NAND FLASH.
In connected mode shown in Figure 2, each pin of CPU and NAND FLASH directly links to each other, CPU is directly started by NAND FLASH, because the restriction of NAND FLASH interface, can't directly read the data of particular address, can't realize the backup of code is started by changing the start-up code position by address wire; This connected mode obviously also can't solve the bit flipping problem of NAND FLASH, can't guarantee the reliability of start-up code, can't guarantee the reliability of system start-up, and therefore, this connected mode is also inapplicable in the system that produces in enormous quantities.
In connected mode shown in Figure 3, use a slice low capacity NOR FLASH to deposit the initial start code, finish the initialization of CPU NAND FLASH controller and read bigger section start-up code among the NAND FLASH, the code that reads NAND FLASH among the NOR FLASH need have bad piece and detect and the ECC algorithmic code.Yet this implementation need be used NOR FLASH chip, and realizes that bad piece detects and the ECC function, therefore, and the system design more complicated.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of system bootstrap device based on NAND FLASH, this device can realize that the backup of boot starts, and system design is simple.
In order to achieve the above object, the invention provides a kind of system bootstrap device based on NAND FLASH, this device comprises CPU, NAND FLASH and logic chip; Wherein, input and output (I/O) bus between logic chip switching CPU and NAND FLASH; The control pin of CPU directly links to each other with the control pin of NANDFLASH, is linked into logic chip simultaneously;
Described NAND FLASH, be used for storing in advance main bootstrap program and a or many parts be equipped with boot;
Described CPU is used for when needs carry out system bootstrap, sends to NAND FLASH and reads control command and original address; Described original address is an address in NAND FLASH address space range; After control command and original address are read in transmission, from NAND FLASH, read boot and execution, if run succeeded, then send timing signal, otherwise do not send timing signal to logic chip;
Described logic chip is used for storing in advance respectively and is equipped with the side-play amount of bootstrap address with respect to original address; Be used to wait for and receive the timing signal that CPU sends, and judge whether the timing signal of receiving that in Preset Time CPU sends, if do not receive, if there is the boot that was not read, then send reset signal to CPU, restart CPU and attempt carrying out system bootstrap once more, and when CPU reads boot again, be equipped with the side-play amount of boot according to storage in advance with respect to original address, the original address that CPU is sent to NAND FLASH be offset computing obtain one be not read be equipped with bootstrap address, and bootstrap address sends to NAND FLASH so that CPU reads the boot fully that this was not read being equipped with of will describedly not being read; If there is not the boot that was not read, then this system bootstrap failure.
The present invention also provides the system boot method based on NAND FLASH, is applied to this method of said apparatus and comprises:
A, in advance in NAND FLASH the storage main bootstrap program and a or many parts be equipped with boot, storage respectively is equipped with the side-play amount of bootstrap address with respect to original address in logic chip in advance;
B, in the time of need carrying out system bootstrap, CPU sends to NAND FLASH and reads control command and original address; And after control command and original address are read in transmission, from NAND FLASH, read boot and execution, if run succeeded, then send timing signal, otherwise do not send timing signal to logic chip;
C, logic chip is waited for and is received the timing signal that CPU sends, and judge whether the timing signal of receiving that in Preset Time CPU sends, if do not receive, if there is the boot that was not read, then send reset signal to CPU, restart CPU and attempt carrying out system bootstrap once more, and when CPU reads boot again, be equipped with the side-play amount of boot according to storage in advance with respect to original address, the original address that CPU is sent to NAND FLASH be offset computing obtain one be not read be equipped with bootstrap address, and the described bootstrap address that is equipped with that was not read sent to NANDFLASH, so that CPU reads the boot that is equipped with that this was not read; If there is not the boot that was not read, then this system bootstrap failure.
By top technical scheme as can be known, the present invention is by utilizing logic chip, in the process of carrying out system bootstrap, the original address that CPU is sent to NAND FLASH is offset computing, obtain offset address, CPU reads and carries out the boot that begins from this offset address among the NAND FLASH, carries out system bootstrap.The present invention changes boot by the address of changing boot, can realize that the backup of boot starts, and simplify system design.
Description of drawings
Fig. 1 is the interface synoptic diagram of NAND FLASH;
Fig. 2 is a kind of structural representation of realizing starting from NAND FLASH the device that carries out system bootstrap of prior art;
Fig. 3 is the another kind of structural representation of realizing starting from NAND FLASH the device that carries out system bootstrap of prior art;
Fig. 4 is the structural representation of the embodiment of the invention based on the system bootstrap device of NAND FLASH;
Fig. 5 is a kind of inner structure synoptic diagram of CPLD in the device shown in Figure 4;
Fig. 6 is a kind of boot location mode synoptic diagram among the NAND FLASH in the device shown in Figure 4;
Fig. 7 is the system boot method process flow diagram of the embodiment of the invention based on NAND FLASH.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer, below in conjunction with the accompanying drawing embodiment that develops simultaneously, the present invention is described in detail.
The present invention provides the more characteristic of high power capacity by utilizing the high storage density of NAND FLASH in given die size, deposit many parts and be equipped with boot in NAND FLASH, and write down each and be equipped with the side-play amount of boot with respect to original address; When system bootstrap needs, by logic chip the original address that CPU sends to NAND FLASH is offset computing, and then changes the bootstrap address that will read, read the purpose of boot startup fully thereby reach.
The boot fully here also is the backup boot of main bootstrap program, below is referred to as boot fully.
The present invention is described in detail as example to use CPLD (CPLD) below, and those skilled in the art can understand that the logic chip here is not limited to CPLD, can also be other logic chip, for example FPGA.
Referring to Fig. 4, Fig. 4 is the system bootstrap structure drawing of device of the embodiment of the invention based on NAND FLASH; Wherein, CPLD links to each other with the I/O pin of CPU NAND FLASH controller and the I/O pin of NANDFLASH respectively, and I/O bus between CPU and the NAND FLASH is used to transfer; The control pin of CPU directly links to each other with the control pin of NAND FLASH, is linked into CPLD simultaneously.
In the device shown in Figure 4, NAND FLASH, be used for storing in advance main bootstrap program and a or many parts be equipped with boot;
CPU is used for when needs carry out system bootstrap, sends to NAND FLASH and reads control command and original address; After sending read control signal and original address, from NAND FLASH, read boot and execution, if run succeeded, then send timing signal, otherwise do not send timing signal to CPLD; Described original address is an address in NAND FLASH address space range;
CPLD is used for storing in advance respectively and is equipped with the side-play amount of bootstrap address with respect to original address; Be used to wait for and receive the timing signal that CPU sends, and judge whether the timing signal of receiving that in Preset Time CPU sends, if do not receive, if there is the boot that was not read, then send reset signal to CPU, restart CPU and attempt carrying out system bootstrap once more, when CPU reads boot again, be equipped with the side-play amount of boot according to storage in advance with respect to original address, the original address that CPU is sent to NANDFLASH be offset computing obtain one be not read be equipped with bootstrap address, and bootstrap address sends to NAND FLASH so that CPU reads the boot fully that this was not read being equipped with of will describedly not being read; If there is not the boot that was not read, then this system bootstrap failure.
Referring to Fig. 5, Fig. 5 is a kind of inner structure synoptic diagram of CPLD in the device shown in Figure 4, and this CPLD comprises: adder unit, address offset unit, timing unit, reset unit; Wherein,
Adder unit is used for storing in advance respectively and is equipped with the side-play amount of bootstrap address with respect to original address;
The address offset unit, be used for when CPU reads boot again, be equipped with the side-play amount of boot according to what store in the adder unit with respect to original address, the original address that CPU is sent to NAND FLASH be offset computing obtain one be not read be equipped with bootstrap address, and bootstrap address sends to NAND FLASH so that CPU reads the boot fully that this was not read being equipped with of will describedly not being read;
Timing unit is used to wait for receive the timing signal that CPU sends, and judges whether to receive the timing signal that CPU sends in Preset Time, if, then this system bootstrap success, otherwise, timeout signal sent to reset unit;
Reset unit, be used to receive the timeout signal that timing unit sends after, judge whether the boot that was not read in addition, if, then send reset signal to CPU, restart CPU and attempt carrying out system bootstrap once more, otherwise, this system bootstrap failure.
In addition, this CPLD also comprises command resolution unit, be used to detect the state that CPU is linked into the control pin of CPLD, and judge to the control command of reading that NAND FLASH sends whether current be address cycle according to the state of described control pin and CPU, if then send the address cycle indication to the address offset unit;
Described address offset unit, to CPU before the original address that NAND FLASH sends carries out the address offset computing, be further used for: the address cycle indication that the command resolution unit that judges whether to receive is sent, if, then CPU is carried out the address offset computing to the original address that NAND FLASH sends, otherwise the CPU of switching and the I/O bus between NAND FLASH are set to direct mode operation; The state of described direct mode operation for the data transmission between CPU and NAND FLASH not being intervened;
The I/O bus of described CPU between CPU and NAND FLASH reads boot code when being direct mode operation from NAND FLASH.
Here, because NAND FLASH has only the I/O bus, when needs read data among the NAND FLASH, need to send earlier and read control command and read the address, read the described data that read the address from NAND FLASH then, wherein to NAND FLASH, transmission is read the address and is sent to NAND FLASH at address cycle, reading of data then is to carry out at cycle data from NAND FLASH, and this belongs to prior art, repeats no more.
Among the present invention, CPU also need read boot according to said process, therefore, command resolution unit need judge to the control command of reading that NAND FLASH sends whether current be address cycle according to the state and the CPU of control pin, here, judge that whether current be that the method for address cycle is same as the prior art.If current is address cycle, then send the address cycle indication to the address offset unit, the address offset unit need be indicated according to the address cycle that command resolution unit is sent, do the address offset computing at address cycle and original address need be carried out the address offset computing time, at non-address cycle, CPLD does not need transmission data between CPU and the NAND FLASH or order are made any modification, and therefore the CPU of its switching and the I/O bus between the NAND FLASH are set to direct mode operation.Direct mode operation is meant that CPLD does not do any change to the data of transmitting on the CPU of its switching and the I/O bus between NAND FLASH or the state of this I/O bus when disturbing.
Here, because before CPU reads boot from NAND FLASH, whether carry out system bootstrap first by the CPLD basis, CPU has been carried out respective handling to the original address that NAND FLASH sends, and obtain bootstrap address after will handling and send to NAND FLASH, therefore CPU can directly read the boot at this bootstrap address place among the NAND FLASH after the I/O bus of CPLD switching is set to direct mode operation.
In addition, timing unit also has clocking capability, and when carrying out system bootstrap, CPLD needed to start clocking capability before waiting for the timing signal that reception CPU sends at every turn; After receiving the timing signal that CPU sends, determine this system bootstrap success, close clocking capability.Can any moment in the system bootstrap process play the unlatching clocking capability, as long as described Preset Time is finished the needed time greater than begin to carry out boot to CPU from timer time.For example, can after receiving the main bootstrap program address that CPU sends, pick up counting, also can when CPU begins to read and carry out boot, pick up counting.
Referring to Fig. 6, Fig. 6 is a kind of boot location mode synoptic diagram among the NAND FLASH in the device shown in Figure 4.The many parts of boot of storing in NAND FLASH are deposited in the following manner: in advance according to the data block size of NAND FLASH, calculate the data block number that every part of boot takies, the reference position of the data block of the integral multiple position of the NAND FLASH data block number that every part of boot is taken from boot respectively begins to deposit.For example, the data block size of supposing NAND FLASH is 128kbytes, the boot size is 550kbytes, need take 5 data blocks of NAND FLASH altogether, if boot 1 is deposited from the starting position of the 1st data block of NAND FLASH as main bootstrap program, and take the 0th to 4 totally 5 data blocks of NAND FLASH; Boot 2 is equipped with boot as first to be deposited from the starting position of the 5th data block, and takies the from the 5th to 95 pieces of totally 5 data block BOB(beginning of block)s; Boot 3 is equipped with boot as second to be deposited from the starting position of the 10th data block, and takies the from the 10th to 14 totally 5 data blocks; And the like.In actual applications, also can and be equipped with boot with described main bootstrap program and leave in successively among the NAND FLASH, for example, boot 2 begins to deposit from the ending of boot 1, and boot 3 begins to deposit from the ending of boot 2, and the like.Also described main bootstrap program can be deposited with boot is out of order fully.
Among the present invention, because CPU carries out system bootstrap after restarting resetting, the address that each retry sends when carrying out system bootstrap is original address.In order to realize starting from being equipped with boot, adder unit needs register system directed retry number of times, so that when this boot that reads is carried out failure, obtains the next bootstrap address that was not read.
For this reason, adder unit be further used for setting in advance and initialization system directed retry number of times be 0; Be further used for: after receiving the timing signal that CPU sends, the zero clearing of system bootstrap number of retries; Be used to wait for receive the retry notice that reset unit is sent, and after receiving the retry notice that reset unit sends, the system bootstrap number of retries added 1;
Reset unit is further used for: storage in advance is equipped with the boot umber; After receiving the timeout signal that timing unit sends, whether judge current system bootstrap number of retries less than the boot umber of storing in advance fully, if then determine the boot fully that existence was not read, otherwise, do not have the boot that is equipped with that was not read; When CPU sends reset signal, be further used for: send the retry notice to adder unit;
The original address that the address offset unit mails to NAND FLASH to CPU be offset computing obtain one be not read be equipped with bootstrap address the time, be specially:, then be equipped with value that bootstrap address obtains with respect to side-play amount and the original address addition of original address as a bootstrap address fully that was not read the n that writes down in the adder unit if current system bootstrap number of retries is n.Here n is the natural number greater than 0.
In addition, carry out system bootstrap in order to prevent unconfined retry, described reset unit is further used for: storage in advance is equipped with the boot umber; After receiving the timeout signal that timing unit sends, the system bootstrap number of retries was added before 1, be further used for: judge that whether current system bootstrap number of retries is less than the boot umber of storing in advance fully, if, then determine the boot fully that existence was not read, otherwise, do not have the boot that is equipped with that was not read.
The boot umber that is equipped with here is the actual umber of storing among the NAND FLASH of boot fully.
Here, CPLD can determine that CPU reads boot first or reads boot again according to described system bootstrap number of retries, if the system bootstrap number of retries is 0, determine that then CPU reads boot first, if the system bootstrap number of retries is not 0, determine that then CPU reads the guiding number of times again, if read boot again, the address offset computing is carried out in the address that then needs CPU to be mail to NAND FLASH, and this introduced in front in detail.
In addition, in order further to verify the correctness of boot, deposit the CRC record of this section boot in the fixed position of boot;
CPU reads and carries out boot among the NAND FLASH finish after, before timing unit sends timing signal, be further used for: the boot that reads is carried out the CRC computing, and the record of the CRC in operation result and the boot compared, if it is identical, then send timing signal to timing unit, otherwise, timing signal do not sent.
In the embodiment of the invention shown in Figure 4, described original address can be the main bootstrap program address, also can be non-bootstrap address; If the main bootstrap program address then when carrying out system bootstrap first, does not need CPLD that this original address is carried out the address offset computing; If above-mentioned original address is not the main bootstrap program address, then when carrying out system bootstrap first, CPLD also needs further this original address to be carried out the address offset computing and obtains the main bootstrap program address.
Therefore, when described original address was non-bootstrap address, described adder unit was further used for: store the side-play amount of main bootstrap program address with respect to original address in advance; Described address offset unit is further used for: when carrying out system bootstrap first, with in the adder unit in advance the main bootstrap program address of storage obtain with respect to the side-play amount of original address and described original address addition and as the main bootstrap program address, and described main bootstrap program address sent to NAND FLASH.
More than the system bootstrap device that the present invention is based on NAND FLASH is had been described in detail, the present invention also provides a kind of system boot method based on NAND FLASH.
Referring to Fig. 7, Fig. 7 is the system boot method process flow diagram based on NANDFLASH that the embodiment of the invention realizes on the described device of Fig. 4, and this method may further comprise the steps:
The original address here is an address in NAND FLASH address space range.
In embodiment illustrated in fig. 7, described CPLD also continues the state that monitoring CPU is linked into the control pin of this CPLD;
Described CPLD to CPU before the original address that NAND FLASH sends carries out the address offset computing, further comprise: state and CPU according to the control pin that monitors judge to the control command of reading that NAND FLASH sends whether current be address cycle, if, then CPU is carried out the address offset computing to the original address that NANDFLASH sends, otherwise the CPU of CPLD switching and the I/O bus between NAND FLASH are set to direct mode operation; The state of described direct mode operation this I/O bus when to be CPLD to the CPU of its switching and the I/O bus data information transmitted between NAND FLASH do not intervene;
CPU and NAND FLASH between the I/O bus from NAND FLASH, read boot code when being direct mode operation.
In addition, CPLD has clocking capability, and when carrying out system bootstrap, CPLD needed to start clocking capability before waiting for the timing signal that reception CPU sends at every turn; After receiving the timing signal that CPU sends, determine this system bootstrap success, close clocking capability.Can any moment in the system bootstrap process play the unlatching clocking capability, as long as described Preset Time is finished the needed time greater than begin to carry out boot to CPU from timer time.For example, can after receiving the main bootstrap program address that CPU sends, pick up counting, also can when CPU begins to read and carry out boot, pick up counting.
In the embodiment of the invention shown in Figure 7, being provided with also in advance in CPLD, initialization system directed retry number of times is 0; Storage is equipped with the boot umber in CPLD in advance;
The described CPLD of step 703 further comprises: with the zero clearing of system bootstrap number of retries judgement determines to receive the timing signal that CPU sends in Preset Time after; After judge determining in Preset Time, not receive the timing signal that CPU sends, further comprise: the system bootstrap number of retries is added 1, and the system bootstrap number of retries was being added before 1, judge that whether current system bootstrap number of retries is less than being equipped with the boot umber, if, then there is the boot that is equipped with that was not read, otherwise, do not have the boot that is equipped with that was not read;
The described CPLD of step 703 is equipped with bootstrap address with respect to the side-play amount between original address according to storage in advance, the original address that CPU is sent to NAND FLASH is offset computing and obtains a method that is equipped with bootstrap address that was not read and be: if the system bootstrap number of retries is n, then with original address and n offset addition that is equipped with bootstrap address with respect to original address, addition is obtained and as one be not read be equipped with bootstrap address.
Here, CPLD is equipped with bootstrap address with respect to the side-play amount between original address according to storage in advance, to CPU before the original address that NAND FLASH sends is offset computing, can draw retry according to current system leads number of times and determines that CPU reads boot first or reads boot again, if current system bootstrap number of retries is 0, can determine that then CPU reads boot first, if current system bootstrap number of retries is not 0, can determine that CPU reads boot again.Therefore, according to the system bootstrap number of retries, just can determine whether and to do the address offset computing to original address.
In addition, in order further to verify the boot that reads, the CRC record of this section boot has been deposited at the place, fixed position of the boot of storing among the NAND FLASH; After the described CPU execution of step 702 boot is finished, before CPLD sends timing signal, further comprise: the boot that receives is carried out the CRC computing, and the CRC record that fixed position in operation result and the boot is located to deposit compares, if it is identical, then send timing signal to sending CPLD, otherwise, timing signal do not sent.
In the embodiment of the invention shown in Figure 7, described original address can be the main bootstrap program address, also can be non-bootstrap address; If the main bootstrap program address then when reading boot first, does not need CPLD that this original address is carried out the address offset computing; If not the main bootstrap program address, then when reading boot first, also need this original address is carried out the address offset computing.
Therefore, when described original address was non-bootstrap address, described CPLD also stored the side-play amount of main bootstrap program address with respect to original address in advance; When CPU reads boot first, the main bootstrap program address is obtained with respect to the side-play amount of original address and described original address addition and as the main bootstrap program address, and described main bootstrap program address sent to NAND FLASH.
By the technical scheme of the invention described above as can be known, the present invention is directed to the unreliable and impracticable problem that when NAND FLASH carries out system bootstrap, exists at present, propose a kind of system boot method and device based on NAND FLASH.Utilize logic chip system bootstrap to be monitored and changed the bootstrap address operation, and it is transparent to CPU and NAND FLASH to change the initial process of boot, therefore, is applicable to the system that all use NAND FLASH; Utilize NAND FLASH storage density height, characteristics that memory capacity is big to carry out many backup start-up operations, under the reliable prerequisite that starts of assurance system, omitted the logic realization of detection of bad piece and ECC verification, the inherent shortcoming of having evaded NAND FLASH chip has improved the reliability of NAND FLASH guidance system; The present invention has also simplified the realization of interface logic in addition, has improved realizability.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being made, is equal to replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (15)
- One kind based on the system bootstrap device of non-flash memory NAND FLASH, comprise CPU and NANDFLASH, it is characterized in that this device also comprises: logic chip; Wherein, input and output (I/O) bus between logic chip switching CPU and NAND FLASH; The control pin of CPU directly links to each other with the control pin of NAND FLASH, is linked into logic chip simultaneously;Described NAND FLASH, be used for storing in advance main bootstrap program and a or many parts be equipped with boot;Described CPU is used for when needs carry out system bootstrap, sends to NAND FLASH and reads control command and original address; Described original address is an address in NAND FLASH address space range; After control command and original address are read in transmission, from NAND FLASH, read boot and execution, if run succeeded, then send timing signal, otherwise do not send timing signal to logic chip;Described logic chip is used for storing in advance respectively and is equipped with the side-play amount of bootstrap address with respect to original address; Be used to wait for and receive the timing signal that CPU sends, and judge whether the timing signal of receiving that in Preset Time CPU sends, if do not receive, if there is the boot that was not read, then send reset signal to CPU, restart CPU and attempt carrying out system bootstrap once more, and when CPU reads boot again, be equipped with the side-play amount of boot according to storage in advance with respect to original address, the original address that CPU is sent to NAND FLASH be offset computing obtain one be not read be equipped with bootstrap address, and bootstrap address sends to NAND FLASH so that CPU reads the boot fully that this was not read being equipped with of will describedly not being read; If there is not the boot that was not read, then this system bootstrap failure.
- 2. device as claimed in claim 1 is characterized in that, described logic chip comprises: adder unit, address offset unit, timing unit, reset unit;Described adder unit is used for storing in advance respectively and is equipped with the side-play amount of bootstrap address with respect to original address;Described address offset unit, be used for when CPU reads boot again, be equipped with the side-play amount of boot according to what store in the adder unit with respect to original address, the original address that CPU is sent to NAND FLASH be offset computing obtain one be not read be equipped with bootstrap address, and bootstrap address sends to NAND FLASH so that CPU reads the boot fully that this was not read being equipped with of will describedly not being read;Described timing unit is used to wait for receive the timing signal that CPU sends, and judges whether to receive the timing signal that CPU sends in Preset Time, if do not receive, sends timeout signal to reset unit;Described reset unit, be used to receive the timeout signal that timing unit sends after, judge whether the boot that was not read in addition, if, then send reset signal to CPU, restart CPU and attempt carrying out system bootstrap once more, otherwise, this system bootstrap failure.
- 3. device as claimed in claim 2 is characterized in that described logic chip also comprises command resolution unit;Described command resolution unit, be used for the state that monitoring CPU is linked into the control pin of described logic chip, and judge to the control command of reading that NAND FLASH sends whether current be address cycle according to the state of the control pin that monitors and CPU, if then send the address cycle indication to the address offset unit;Described address offset unit, to CPU before the original address that NAND FLASH sends carries out the address offset computing, be further used for: judge whether to receive the address cycle indication that command resolution unit is sent, if, then CPU is carried out the address offset computing to the original address that NAND FLASH sends, otherwise the CPU of switching and the I/O bus between NAND FLASH are set to direct mode operation; The state of described direct mode operation this I/O bus when to be logic chip to the CPU of its switching and the I/O bus data information transmitted between NAND FLASH do not intervene;The I/O bus of described CPU between itself and NAND FLASH reads boot code from NANDFLASH when being direct mode operation.
- 4. device as claimed in claim 3 is characterized in that, described timing unit before waiting for the timing signal that reception CPU sends, is further used for: start clocking capability; After receiving the timing signal that CPU sends, be further used for, close clocking capability.
- 5. device as claimed in claim 4 is characterized in that, described adder unit is further used for setting in advance and initialization system directed retry number of times is 0; Be used to wait for receive the timing signal that CPU sends, and after receiving the timing signal that CPU sends, with the zero clearing of system bootstrap number of retries; Be used to wait for receive the retry notice that reset unit is sent, and after receiving the retry notice that reset unit sends, the system bootstrap number of retries added 1;Described reset unit is further used for: storage in advance is equipped with the boot umber, and the described boot umber that is equipped with is the actual umber of storing among the NAND FLASH of boot fully; After receiving the timeout signal that timing unit sends, whether judge current system bootstrap number of retries less than the boot umber of storing in advance fully, if then determine the boot fully that existence was not read, otherwise, do not have the boot that is equipped with that was not read; When CPU sends reset signal, be further used for: send the retry notice to adder unit;The bootstrap address fully that described address offset unit is stored in according to adder unit is with respect to the side-play amount of original address, the original address that CPU is sent to NAND FLASH be offset computing obtain one be not read be equipped with bootstrap address the time, be specially: if the system bootstrap number of retries is n, then with original address and n offset addition that is equipped with bootstrap address with respect to original address, and addition is obtained and as one be not read be equipped with bootstrap address.
- 6. device as claimed in claim 5 is characterized in that, the system bootstrap number of retries of described address offset unit in adder unit is not 0 o'clock, determines that CPU reads boot again.
- 7. device as claimed in claim 6 is characterized in that, deposits the CRC record of this section boot in advance in the fixed position of boot;CPU reads and carries out boot among the NAND FLASH finish after, before timing unit sends timing signal, be further used for: the boot that reads is carried out the CRC computing, and the record of the CRC in operation result and the boot compared, if it is identical, then send timing signal to timing unit, otherwise, timing signal do not sent.
- 8. as the described device of the arbitrary claim of claim 1 to 7, it is characterized in that,Described original address is the main bootstrap program address that is stored among the NAND FLASH;Perhaps,Described original address is an arbitrary address in NAND FLASH address space range;Described adder unit is further used for: store the side-play amount of main bootstrap program address with respect to original address in advance;Described address offset unit is further used for: when CPU reads boot first, that the main bootstrap program address is obtained with respect to the side-play amount of original address and original address addition and as the main bootstrap program address, and described main bootstrap program address sent to NAND FLASH.
- 9. the system boot method based on NAND FLASH is characterized in that, among the logic chip switching CPU and the I/O bus between NAND FLASH; The control pin of CPU directly links to each other with the control pin of NAND FLASH, is linked into logic chip simultaneously; This method comprises:A, in advance in NAND FLASH the storage main bootstrap program and a or many parts be equipped with boot, storage respectively is equipped with the side-play amount of bootstrap address with respect to original address in logic chip in advance;B, in the time of need carrying out system bootstrap, CPU sends to NAND FLASH and reads control command and original address; And after control command and original address are read in transmission, from NAND FLASH, read boot and execution, if run succeeded, then send timing signal, otherwise do not send timing signal to logic chip;C, logic chip is waited for and is received the timing signal that CPU sends, and judge whether the timing signal of receiving that in Preset Time CPU sends, if do not receive, if there is the boot that was not read, then send reset signal to CPU, restart CPU and attempt carrying out system bootstrap once more, and when CPU reads boot again, be equipped with the side-play amount of boot according to storage in advance with respect to original address, the original address that CPU is sent to NAND FLASH be offset computing obtain one be not read be equipped with bootstrap address, and the described bootstrap address that is equipped with that was not read sent to NANDFLASH, so that CPU reads the boot that is equipped with that this was not read; If there is not the boot that was not read, then this system bootstrap failure.
- 10. method as claimed in claim 9 is characterized in that, logic chip continues the state that monitoring CPU is linked into the control pin of described logic chip;Step C described to CPU before the original address that NAND FLASH sends carries out the address offset computing, further comprise: state and CPU according to the control pin that monitors judge to the control command of reading that NAND FLASH sends whether current be address cycle, if, then CPU is carried out the address offset computing to the original address that NANDFLASH sends, otherwise the CPU of switching and the I/O bus between NANDFLASH are set to direct mode operation; The state of described direct mode operation this I/O bus when to be logic chip to the CPU of its switching and the I/O bus data information transmitted between NAND FLASH do not intervene;The described CPU of step B reads boot code when the I/O bus between itself and NAND FLASH is direct mode operation from NAND FLASH.
- 11. method as claimed in claim 10 is characterized in that, the described logic chip of step C further comprised before waiting for the timing signal that reception CPU sends: start clocking capability; After receiving the timing signal that CPU sends, further comprise: close clocking capability.
- 12. method as claimed in claim 11 is characterized in that, setting in advance also, initialization system directed retry number of times is 0; Storage in advance is equipped with the boot umber, and the described boot umber that is equipped with is the actual umber of storing among the NAND FLASH of boot fully;The described logic chip of step C further comprises: with the zero clearing of system bootstrap number of retries judgement determines to receive the timing signal that CPU sends in Preset Time after; After judge determining in Preset Time, not receive the timing signal that CPU sends, further comprise: the system bootstrap number of retries is added 1, and the system bootstrap number of retries was being added before 1, judge that whether current system bootstrap number of retries is less than being equipped with the boot umber, if, then there is the boot that is equipped with that was not read, otherwise, do not have the boot that is equipped with that was not read;What the described basis of step C was stored in advance is equipped with bootstrap address with respect to the side-play amount between original address, the original address that CPU is sent to NAND FLASH is offset computing and obtains a method that is equipped with bootstrap address that was not read and be: if the system bootstrap number of retries is n, then with original address and n offset addition that is equipped with bootstrap address with respect to original address, addition is obtained and as one be not read be equipped with bootstrap address.
- 13. method as claimed in claim 12 is characterized in that, described logic chip is not 0 o'clock in current system bootstrap number of retries, determines that CPU reads boot again.
- 14. method as claimed in claim 13 is characterized in that, deposits the CRC record of this section boot in advance in the fixed position of boot;After the described CPU execution of step B boot is finished, before logic chip sends timing signal, further comprise: this section boot is carried out the CRC computing, and the record of the CRC in operation result and this section boot compared, if it is identical, then send timing signal to logic chip, otherwise, timing signal do not sent.
- 15., it is characterized in that described original address is the main bootstrap program address that is stored among the NAND FLASH as the described method of the arbitrary claim of claim 9 to 13;Perhaps,Described original address is an arbitrary address in NAND FLASH address space range;Described CPLD also stores the side-play amount of main bootstrap program address with respect to original address in advance; When CPU reads boot first, further the main bootstrap program address is obtained with respect to the side-play amount of original address and original address addition and as the main bootstrap program address, and described main bootstrap program address sent to NAND FLASH.
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