CN111338702B

CN111338702B - SOC system booting method based on off-chip nor-flash

Info

Publication number: CN111338702B
Application number: CN202010124190.3A
Authority: CN
Inventors: 不公告发明人
Original assignee: Zhuhai Eeasy Electronic Tech Co ltd
Current assignee: Zhuhai Eeasy Electronic Tech Co ltd
Priority date: 2020-02-27
Filing date: 2020-02-27
Publication date: 2022-04-26
Anticipated expiration: 2040-02-27
Also published as: CN111338702A

Abstract

The invention discloses an SOC system booting method based on off-chip nor-flash, which comprises the following steps: the spi controller selects a 1-line reading mode, a hardware system reset circuit is added to a strap design, when a reset _ n signal is released, a hardware system grabs the level state of a p _ xip pin, when the p _ xip pin is detected to be high level, an xip _ en enabling signal is invalid, and when the p _ xip pin is detected to be low level, the xip _ en enabling signal is valid; in the hardware system address decoder, both nor-xip and boot-rom are corresponding to 0 address: when the xip _ en enabling signal is invalid, the hardware system decodes the 0 address to the boot-rom, the boot-rom guides the software system after the system is powered on, when the xip _ en enabling signal is valid, the 0 address is decoded to the nor-flash space, and the software system is guided from the nor after the hardware system is powered on. The invention has the beneficial effects that: all the nors can be compatible through the SOC system booting method, and the development time of the SOC system is saved.

Description

SOC system booting method based on off-chip nor-flash

Technical Field

The invention relates to the field of SOC chips, in particular to an SOC system booting method based on off-chip nor-flash.

Background

The SoC is called a system-on-chip, and also called a system-on-chip, meaning that it is a product, an integrated circuit with a dedicated target, which contains the complete system and has the entire contents of embedded software. Meanwhile, the method is a technology for realizing the whole process from the determination of system functions to the software/hardware division and completing the design.

In the prior art, one of a spi-nor-flash and an spi-nand-flash is generally used for starting an SOC chip as an off-chip memory for storing a boot program, and the boot program is read into a RAM by a corresponding driver to start the chip. At present, spi-nor-flash of a plurality of manufacturers has an xip function, for example, n25q series of magnesium light defines a special xip mode thereof, the content of nor is read in the special xip mode without sending a nor command, only an address needs to be sent, so that the transmission speed can be increased, and in addition, a multi-line xip reading mode such as 2-line and 4-line is defined according to the requirement. However, these vendor-specific nor xip modes are not compatible with each other, and the enabling modes of the xip modes may be different, and the supported line widths may also be different, so that it is difficult to apply the mode to the SOC system.

Disclosure of Invention

Aiming at the problems, the invention provides an SOC system guiding method based on off-chip nor-flash, which mainly solves the problem that the existing SOC system guiding method is poor in nor compatibility.

In order to solve the technical problems, the technical scheme of the invention is as follows:

an SOC system booting method based on off-chip nor-flash comprises the following steps:

s100: the method comprises the steps that 1 line reading mode is selected by an spi controller, and the spi controller sends a complete command + address to an spi-nor-flash to read required data;

adding a strap design into a hardware system reset circuit, grabbing the level state of a p _ xip pin by the hardware system when a reset _ n signal is released, invalidating an xip _ en enabling signal when the p _ xip pin is detected to be a high level, and validating the xip _ en enabling signal when the p _ xip pin is detected to be a low level;

s200: in the hardware system address decoder, both nor-xip and boot-rom are corresponding to 0 address: when the xip _ en enabling signal is invalid, the hardware system decodes the 0 address to the boot-rom, the boot-rom guides the software system after the system is powered on, when the xip _ en enabling signal is valid, the 0 address is decoded to the nor-flash space, and the software system is guided from the nor after the hardware system is powered on;

s300: when the xip _ en enabling signal is effective, the system starts a clock of the spi controller, releases a reset signal of the spi controller, enables the spi controller and enables the spi controller to start to work after the reset is finished;

s400: after the cpu sends a read instruction, if an xip _ en enable signal is valid, the bus decoder decodes the instruction to the spi controller through the bus;

s500: after receiving the reading instruction sent by the bus, the spi controller translates the reading instruction of the bus into a reading command and a reading address of the spi-nor-flash, and waits for data to be read back from the spi-nor-flash; when the data is not returned from the nor-flash, the spi controller pulls a ready/busy signal of the bus, and the bus is in a waiting state;

s600: the bus returns data to the CPU, which executes the data.

In some embodiments, in the process of executing S300, when xip _ en enable signal is active, the hardware system allocates a pin of the spi controller in addition to automatically starting a clock of the spi controller, enabling the spi controller.

In some embodiments, prior to performing S400: and assigning PC as an initial value of 0.

In some embodiments, S600 is followed by S700: and judging whether the PC jumps to the sram/dram, if so, pointing the sram/dram by the PC, ending the leading of the spi _ nor _ boot, starting the next stage, and if not, continuously executing the rest codes of the spi _ nor _ boot.

The invention has the beneficial effects that:

1. all the nor can be compatible through the SOC system booting method;

2. the method has the advantages of quickly developing the SOC guidance system;

3. when the SOC needs to be updated, the boot-rom is not manufactured again (the tape needs to be reflowed), and the boot-rom is directly upgraded on the nor, so that the method is convenient and fast.

Drawings

FIG. 1 is a flowchart of an off-chip nor-flash based SOC system boot method of the present invention;

FIG. 2 is a flow chart of the behavior of the spi _ nor _ boot bus of the present invention;

FIG. 3 is a software flow diagram of the spi _ nor _ boot of the present invention;

FIG. 4 is a timing diagram of the AHB bus decode spi controller of the present invention;

FIG. 5 is a schematic diagram of the xip enable pin on the pcb of the present invention;

FIG. 6 is a schematic representation of a spi-nor-boot of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer and clearer, the following detailed description of the present invention is provided with reference to the accompanying drawings and detailed description. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some but not all of the relevant aspects of the present invention are shown in the drawings.

Example one

As shown in fig. 1, the present embodiment provides an off-chip nor-flash-based SOC system booting method, including the following steps:

s100: the spi controller selects a 1-line reading mode, sends a complete command + address to the spi-nor-flash and reads required data; the spi controller selects the 1-line read mode which is supported by all the nors to be used, and actively sends a read command without setting the nor-flash to a special xip mode. One read action, the controller sends the complete command + address and then reads the required data back. While the xip generally does not send commands and only sends addresses, so that multi-line reading is realized, but the nor-flash is required to enter an xip mode to cooperate with reading and writing of the spi controller. Therefore, the invention improves the compatibility by sacrificing part of the speed.

A hardware system reset circuit is added into a strap design, when a reset _ n signal is released, a hardware system grabs the level state of a p _ xip pin, when the p _ xip pin is detected to be in a high level, an xip _ en enabling signal is invalid, and when the p _ xip pin is detected to be in a low level, the xip _ en enabling signal is valid; and when the key is reset, the fixed pin is selected to be switched to nor guide, so that boot-rom guide is compatible.

S200: in the hardware system address decoder, both nor-xip and boot-rom are corresponding to 0 address: when the xip _ en enabling signal is invalid, the hardware system decodes the 0 address to the boot-rom, and after the system is powered on, the boot-rom guides the software system; when the xip _ en enabling signal is effective, decoding the 0 address into a nor-flash space, and after a hardware system is powered on, guiding a software system from the nor; realizing the address mapping switching of nor-flash and boot-rom through an xip _ en signal;

s400: after the cpu sends a read instruction (for example, an AHB BUS read instruction, which reads a 0 to 8M code space and can define the size according to the requirement), if the xip _ en enable signal is valid, the BUS (AHB) decoder decodes the instruction to the spi controller through the BUS;

s500: after receiving a reading instruction sent by the bus, the spi controller translates the reading instruction of the bus into a reading command (spi-read-cmd-0x03) and a reading address (spi-nor-address) of the spi-nor-flash and waits for data to be read back from the spi-nor-flash; when the data is not returned from the nor-flash, the spi controller pulls a ready/busy signal of the bus, and the bus is in a waiting state;

s600: the bus returns data (instructions) to the CPU, which executes the data (instructions).

The SOC system booting method can be compatible with all the nors and has the advantage of quickly developing the SOC booting system. When the SOC needs to be updated, the boot-rom is not required to be manufactured again, the chip is re-streamed and then is directly upgraded on the nor, and the upgrading on the nor is convenient and fast. The principle of saving the development time of the SOC system is that in the development stage, the system can be guided and the application function can be developed on the spi-nor-flash, simultaneously boot-rom is developed in parallel, and finally integration is carried out; the robustness of the system is enhanced, and a standby path can be provided even if the boot-rom design fails; the method for upgrading/adding new functions of the existing SOC product is provided, some functions and applications which can be added only by upgrading the boot-rom can be realized by rewriting nor, and the time and cost for remanufacturing the stream chip of the boot-rom are saved.

Example two

As shown in fig. 2, the flow of steps S300 to S600 in the first embodiment is described in more detail with reference to the spi _ nor _ boot bus behavior flow chart, as follows:

in the process of executing S300, when the xip _ en enabling signal is valid, the hardware system automatically starts a clock of the spi controller, enables the spi controller, and also allocates a GPIO (general purpose input/output) pin of the spi controller;

before performing S400: assigning PC as 0;

s700 is also included after S600: and judging whether the PC jumps to the sram/dram, if so, pointing the sram/dram by the PC, ending the leading of the spi _ nor _ boot, starting the next stage, and if not, continuously executing the rest codes of the spi _ nor _ boot. The assignment of the PC is illustrated in fig. 2, where PC +4 is only one of the most common cases to continue execution, not all. It is also possible that pc equals another value, but as long as pc is in the range of 0,8M, execution of the code in nor continues.

EXAMPLE III

On the basis of the first embodiment or the second embodiment, a software flow of spi _ nor _ boot is further provided, as shown in fig. 3, the steps are as follows:

the method comprises the following steps: powering on a hardware system, judging whether an xip _ en enabling signal is effective, if so, executing a spi _ nor boot flow, otherwise, performing ROM boot, and entering an OS;

step two: assigning the value to be an initial value of 0, and starting execution by the CPU;

step three: the cpu reads data from nor, writes to sram: the nor address is 1M, the address of sram is the starting address, the data length is determined after compiling by a compiler (including sdram initialization code and data segment);

step four: PC is 0xx xxx, and the CPU jumps to the starting position of sram to start execution;

step five: carrying out sdram initialization;

step six: the cpu reads data from nor, writes to SDRAM: the nor address is the start of the 2M location (for example), and the sram address is the start address; the data length is determined after compiling by a compiler (the data contains the rest of the system boot code, and the operating system code);

step seven: : PC xx;

step eight: the CPU jumps to the sdam to start executing;

step nine: the system boot of the next stage is performed and the OS is entered.

The codes of the second step and the third step are executed in nor, the codes of the fourth step and the sixth step are executed in sram, and the codes of the seventh step and the ninth step are executed in sdram.

Example four

On the basis of the first to third embodiments, a timing chart of the AHB bus decoding spi controller is also provided, and as shown in fig. 4, the bus behavior is more intuitively explained.

EXAMPLE five

On the basis of the first to fourth embodiments, a schematic diagram of the xip enable pin on the pcb is also provided, and as shown in fig. 5, the hardware principle of the xip enable pin is further explained.

EXAMPLE six

On the basis of the first to the fifth embodiments, a schematic view of the spi-nor-boot is also provided, and as shown in fig. 6, a guidance flow of the spi-nor is more intuitively explained.

The above embodiments are only for illustrating the technical concept and features of the present invention, and the purpose thereof is to enable those skilled in the art to understand the contents of the present invention and implement the present invention accordingly, and not to limit the protection scope of the present invention accordingly. All equivalent changes or modifications made in accordance with the spirit of the present disclosure are intended to be covered by the scope of the present disclosure.

Claims

1. An SOC system booting method based on off-chip nor-flash is characterized by comprising the following steps:

s600: the bus returns data to the CPU, which executes the data.

2. The off-chip nor-flash based SOC system boot method of claim 1, wherein: in the process of executing S300, when the xip _ en enable signal is valid, the hardware system allocates a GPIO pin of the spi controller in addition to automatically starting the clock of the spi controller and enabling the spi controller.

3. The off-chip nor-flash based SOC system boot method of claim 1 or 2, wherein: s700 is also included after S600: and judging whether the PC jumps to the sram/dram, if so, pointing the sram/dram by the PC, ending the leading of the spi _ nor _ boot, starting the next stage, and if not, continuously executing the rest codes of the spi _ nor _ boot.