CN101599024A - A kind of device of switching and booting codes in double memory area, system and method - Google Patents
A kind of device of switching and booting codes in double memory area, system and method Download PDFInfo
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- CN101599024A CN101599024A CNA2009103049362A CN200910304936A CN101599024A CN 101599024 A CN101599024 A CN 101599024A CN A2009103049362 A CNA2009103049362 A CN A2009103049362A CN 200910304936 A CN200910304936 A CN 200910304936A CN 101599024 A CN101599024 A CN 101599024A
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Abstract
The invention discloses a kind of device, system and method for switching and booting codes in double memory area, relate to the computer starting technical field, purpose is the problem that complex structure, the cost of solution prior art existence is higher, be prone to the guiding failure, device comprises timer circuit, the output mapping control signal is cleared when receiving reset signal; The timer clear circuit receives the zero clearing control signal that comes from the external world, exports above-mentioned reset signal; Switch executive circuit, receive the address input signal that comes from the external world, under the control of above-mentioned mapping control signal, OPADD output signal, wherein the RC delay circuit of timer circuit for constituting by resistance and electric capacity; Method comprises the status signal of central processing unit check map addresses and commutation circuit, judgement is normal condition or malfunction, shines upon master boot sector or the backup boot section of the enabling address signal of central processing unit to bootstrap memory respectively by map addresses and commutation circuit then.
Description
Technical field
The present invention relates to the computer starting technical field, particularly store two parts of mutually redundant guidance codes and start device, the system and method that automatically switches to the backup guidance code under the situation of failing at its main guidance code with bootstrap memory.
Background technology
A part of code of at first carrying out after the computer system electrification reset is called as boot, and the boot function is: (1) operating system software and other application software graftabls, and jump to the inlet of operating system or application software; (2) on-the-spot operating system and the application software upgraded.
Boot leaves in the erasable nonvolatile memory chip, for example EPROM, EEPROM, flash etc.CPU if therefore there are not other additional map addresses devices, can only have a boot in the computer system from the fixing physical address boot of packing into.In case this boot is destroyed, computer system can't start, and this fault can not solve with the method that guidance code is upgraded at the scene.
By an additional map addresses and switching device shifter, the physical address map of a guidance code that can send CPU is on two zoness of different of nonvolatile memory, and one of them is a master boot sector, another one backup boot section.When the situation that starts failure with the guidance code of master boot sector, map addresses and switching device shifter can automatically switch to the backup boot section guidance code of packing into.This method can significantly improve the reliability of bootup process, reduces because the anti-revisionist rate of the equipment that has the CPU mini system that the guidance code fault causes.
Is publication number that US2004/0250058 A1, application number are that a kind of usefulness has been described in U.S.'s application for a patent for invention of 10/861,737? map addresses and changing method that DLC (digital logic circuit) such as door, counter, selector switch realize, this invention mainly has the following disadvantages:
1, adopt counter to come timing to realize delay function, circuit structure is more complicated relatively, and cost is higher;
2, the zero clearing of counter realizes by the high level signal that its clear pin reception comes from CPU, when the program of CPU operation breaks down, if the clear pin of CPU is in high level state, counter is zero always in the then above-mentioned U.S. Patent application, upset never, CPU can not reset yet, and can't reload guidance code from backup area, does not reach the effect of backup;
3, the inner watchdog function of realizing of this invention does not have the supply voltage monitoring function, so system also need dispose special voltage monitoring chip, has improved application cost.
Summary of the invention
The objective of the invention is to solve the problem that complex structure, cost that prior art exists are higher, be prone to the guiding failure, provide that a kind of cost is lower, structure is simpler, the device of two parts of guidance codes on the bootstrap memory that can automatically switch, improve the success ratio that cpu system starts in the product, and then improve reliability of products.
Another object of the present invention provides a kind of system that is applied to above-mentioned switching and booting codes in double memory area, can adopt the lower scheme of cost to improve the product reliability of applying.
A further object of the invention provides a kind of method of switching and booting codes in double memory area, can adopt the lower scheme of cost to improve the product reliability of applying.
Purpose of the present invention realizes by following technical proposals respectively:
A kind of device of switching and booting codes in double memory area comprises
Timer circuit, the output mapping control signal is cleared when receiving reset signal;
The timer clear circuit receives the zero clearing control signal that comes from the external world, exports above-mentioned reset signal;
Switch executive circuit, receive the address input signal that comes from the external world, under the control of above-mentioned mapping control signal, the OPADD output signal.
As an embodiment of the invention, described timer circuit inputs to the switching executive circuit with reset signal as mapping control signal when being cleared.
As an embodiment of the invention, described timer circuit is made of second resistance, second electric capacity of series connection, and both links are connected with the timer clear circuit.
As an embodiment of the invention, described timer clear circuit comprises first resistance and first electric capacity that the series connection back is connected with ground, and wherein the other end of first electric capacity receives and comes from extraneous zero clearing control signal; First resistance is connected the control end of first triple gate with the link of first electric capacity, the input end of first triple gate is by the 4th resistance eutral grounding, and the output terminal of first triple gate is connected with timer.
As an embodiment of the invention, described switching executive circuit comprises second triple gate and the 3rd resistance that is connected with its output terminal, the input end of second triple gate receives and comes from extraneous address input signal, and its control end connects timer circuit, its output terminal OPADD output signal.
As an embodiment of the invention, described switching executive circuit comprises NOR gate circuit and the 3rd resistance that is connected with its output terminal, an input end of this NOR gate circuit receives and comes from extraneous address input signal, another input end connects timer circuit, its output terminal OPADD output signal.
A kind of system of switching and booting codes in double memory area comprises
Central processing unit, output zero clearing control signal and address input signal receive the timer status signal;
Bootstrap memory respectively stores a mutually the same guidance code, the receiver address output signal in two zone;
Map addresses and commutation circuit receive zero clearing control signal and address input signal, output timer status signal and address output signal;
Watchdog circuit, when guidance code is directed failing in one of them zone on bootstrap memory, this watchdog circuit central processing unit that resets, the guidance code of packing in another zone then.
Described map addresses and commutation circuit comprise timer circuit, timer clear circuit, switch executive circuit;
Described timer circuit is made of second resistance, second electric capacity of series connection, and both links are connected with timer clear circuit, switching executive circuit;
Described timer clear circuit comprises first resistance and first electric capacity that the series connection back is connected with ground, and wherein the other end of first electric capacity receives and comes from extraneous zero clearing control signal; First resistance is connected the control end of first triple gate with the link of first electric capacity, the input end of first triple gate is by the 4th resistance eutral grounding, and the output terminal of first triple gate is connected with timer;
Described switching executive circuit comprises second triple gate and the 3rd resistance that is connected with its output terminal, and the input end of second triple gate receives and comes from extraneous address input signal, and its control end connects timer circuit, its output terminal OPADD output signal.
A kind of method of switching and booting codes in double memory area comprises
Guide the memory block high-order address signal by map addresses and commutation circuit mapping between central processing unit and the bootstrap memory;
The normal periodically high level pulse of the expression mapping whether map addresses and commutation circuit basis receive central processing unit output guides the memory block high-order address signal;
If normal condition, then the enabling address signal of central processing unit is mapped to the master boot sector of bootstrap memory by map addresses and commutation circuit, and the code in the master boot sector is read in guiding, and central processing unit starts successfully that the back continues to export the periodicity high level pulse;
If malfunction, then the enabling address signal of central processing unit is mapped to the backup boot section of bootstrap memory by map addresses and commutation circuit, the code in the backup boot section is read in guiding, does not export periodically high level pulse after central processing unit starts successfully.
In the said method, described central processing unit starts from master boot sector, the status signal of map addresses and commutation circuit output expression normal condition; Central processing unit starts from the backup boot section, the status signal of map addresses and commutation circuit output expression malfunction, and the status signal of central processing unit check map addresses and commutation circuit, judgement is normal starting state or fault initiating state.
The present invention adopts said structure and/or method, and the RC delay timer that utilizes resistance, electric capacity to constitute has advantage simple in structure, that cost is lower; And when the program of central processing unit operation broke down, timer of the present invention was understood overtime overflowing, and sent the signal of fault initiating.Other beneficial effect that the present invention has will further specify in embodiment.
Description of drawings
The present invention will illustrate by example and with reference to the mode of accompanying drawing, wherein:
Fig. 1 is a system architecture synoptic diagram of the present invention;
Fig. 2 is an apparatus structure synoptic diagram of the present invention;
Fig. 3 is a bootstrap memory synoptic diagram of the present invention;
Fig. 4 is another example structure synoptic diagram of device of the present invention;
Fig. 5 is a method synoptic diagram of the present invention.
Embodiment
A kind of device that is applied between CPU and the bootstrap memory, the master boot sector that leading address or the enabling address of CPU can be mapped to bootstrap memory, or when master boot sector breaks down, guide to the backup boot section.Among the typical embodiment, bootstrap memory is erasable nonvolatile memory, wherein stores a mutually the same guidance code respectively in two storage areas, and these two storage areas can be active and standby each other, be that one of them is a master boot sector, another then is the backup boot section
Generally speaking, after the cpu chip electrification reset, can be from pack into article one instruction of one of bootstrap memory fixing physical address, and this instruction that brings into operation, this address is called the enabling address.The address of follow-up load is decided by programmed logic.The cpu chip enabling address is made of three parts: a high position, interposition, low level.The interposition of the enabling address of most CPU is 0 entirely, and for example: Freescale PowerPC chip enable address is 0xfff00100 (perhaps 0x00000100).
Embodiment 1:
As shown in Figure 2, the above-mentioned booting codes in double memory area device that can automatically switch is map addresses and commutation circuit 100, comprises
Timer clear circuit 101 receives the zero clearing control signal that comes from the external world, exports above-mentioned reset signal, and described zero clearing control signal is the high level pulse signal;
Switch executive circuit 102, receive the address input signal that comes from the external world, under the control of above-mentioned mapping control signal, the OPADD output signal.
Map addresses and commutation circuit 100 can be a kind of module, chip or integrated circuit of encapsulation, have four external pins, are respectively:
The status pin, be status pin, this is an output pin, and it links to each other with the GPIO pin that is configured to import of CPU, it is to be in " normal condition ", still " malfunction " that map addresses and this pin of commutation circuit 100 usefulness are exported current start-up course.In the time of the status output low level, represent current being in " normal condition ", guidance code is packed into from the master boot sector of bootstrap memory;
The clear pin, i.e. zero clearing pin, this is an input pin, and it links to each other with the GPIO pin that is configured to export of CPU, and when on this pin regularly output high level pulse signal the time, address output pin fA18 always exports high level; When no level signal on this pin was exported or exported changeless level signal, the level signal of address output pin fA18 always equated with the level signal of address input pin cA18.In system powered on the normal start-up course of vectoring phase, CPU regularly exported high level pulse by the GPIO pin, and Notify Address mapping and the operation of commutation circuit current C PU boot are normal in this way, did not need to switch to back up the boot section and load program; In fault initiating stage and master routine operation phase, do not export any signal on this pin, the level signal of fA18 pin always equates with the level signal of cA18 pin;
The cA18 pin, i.e. address input pin, it links to each other with a address wire in the cpu address bus.By adjusting the address pin numbering that links to each other with CPU, can adjust the size of boot section code.For example: if cA18 links to each other with the A18 of CPU, then the size of master boot sector and backup boot section all is 256KByte, if link to each other with the A19 pin of CPU, then the size of master boot sector and backup boot section all is 512Kbyte;
The fA18 pin, i.e. address output pin, it with the flash address bus in a corresponding address wire link to each other.In normal boot process, fixing output high level on this pin; In the fault bootup process or the master routine stage, the level signal of this pin is identical with the cA18 leg signal.
More particularly, as shown in Figure 2, timer clear circuit 101 comprises first resistance R 1 and first capacitor C 1 that the series connection back is connected with ground, and wherein the other end of first capacitor C 1 receives the zero clearing control signal that comes from CPU, promptly link to each other the other end ground connection of first resistance R 1 with the clear pin; First resistance R 1 is connected the control end of the first triple gate U1_A with the link of first capacitor C 1, the input end of the first triple gate U1_A is by the 4th resistance R 4 ground connection, and the output terminal of the first triple gate U1_A is connected with timer circuit 103.
As shown in Figure 2, switch executive circuit 102 and comprise the second triple gate U1_B and the 3rd resistance R 3 that is connected with this triple gate output terminal, the other end of the 3rd resistance R 3 is connected with power supply VCC, the input end of the second triple gate U1_B receives the address input signal (promptly linking to each other with the cA18 pin) that comes from CPU, its control end connects timer circuit 103, its output terminal OPADD output signal (promptly linking to each other with the fA18 pin).
As shown in Figure 2, timer circuit 103 is made of second resistance R 2, second capacitor C 2 of series connection, and control end and the status pin of the second triple gate U1_B of the output terminal of both links and the first triple gate U1_A of timer clear circuit 101, switching executive circuit 102 are connected.
It generally is 0 characteristics that present embodiment has utilized CPU enabling address interposition, and can realize function corresponding with U1_A on the same triple gate chip and U1_B two-way triple gate.
In the present embodiment, the enabling address interposition that map addresses shown in Figure 2 and commutation circuit 100 utilize central processor CPU to export is these characteristics of 0, become the 1 enabling address replay that central processor CPU is exported by a certain position, the centre of control address line and be mapped to the another one address, control address position A18 on the PowerPC of freescale for example, then the 0x00000100 replay is mapped to 0x00040100, and the address of the address after remapping as master boot sector, this always remapping can be performed in the normal start-up course.When master boot sector breaks down, this bit address is reverted to 0, become from the startup of backup boot section.
Embodiment 2:
It is different with embodiment 1 to remove the concrete structure that switches executive circuit 102, and other circuit structure is identical with embodiment 1.
If the interposition of enabling address is not 0, one tunnel vacant XOR gate XOR is perhaps just arranged in the system, then can utilize an XOR gate XOR to realize the switching executive circuit that above-mentioned second triple gate U1_B and the 3rd resistance R 3 constitute, as shown in Figure 4.Wherein XOR gate XOR input end links to each other with the cA18 pin, receives the address input signal that comes from central processor CPU; The link of second resistance R 2 and second capacitor C 2 in another input end connection timer circuit; Its output terminal connects the 3rd resistance R 3 and fA18 pin, OPADD output signal.
In the present embodiment, when realizing switching executive circuit with XOR gate XOR, the master boot sector address is identical with the central processor CPU enabling address.
Embodiment 3:
A kind of system of switching and booting codes in double memory area comprises as shown in Figure 1
Central processor CPU, output zero clearing control signal clear and address input signal cA18 receive timer status signal status;
Bootstrap memory flash respectively stores a mutually the same guidance code, receiver address output signal fA18 in two zone;
Map addresses and commutation circuit 100 receive zero clearing control signal clear and address input signal cA18, output timer status signal status and address output signal fA18;
Watchdog circuit, when guidance code is directed failing in one of them zone on bootstrap memory, this watchdog circuit central processing unit that resets, the guidance code of packing in another zone then.
Also have the control signal of transmitting by control bus CTRLs, the data-signal that passes through data bus DATAs transmission between central processor CPU and the bootstrap memory flash, transmit address signal by address bus A0-A17, A19-A25, the address wire A18 in the centre of address bus then transmits signal by map addresses and commutation circuit 100 with bootstrap memory.
As shown in Figure 1, the watchdog circuit that is connected with central processor CPU in the present embodiment, can adopt the commercialization watchdog chip of selling on the market, realize " supply voltage monitoring " and " software crashes and monitors " two kinds of functions, when guiding is failed on the boot section, this watchdog circuit CPU that resets is then from backup boot section boot.
Wherein map addresses and commutation circuit 100 can be the structures of embodiment 1 as shown in Figure 2, also can be the structures of embodiment 2 as shown in Figure 4, decide according to the actual conditions of concrete central processor CPU and system.
Be applied to the system of present embodiment with map addresses shown in Figure 2 and commutation circuit 100, one end of first capacitor C 1 of timer clear circuit 102 receives the zero clearing control signal clear of central processor CPU output by clear pin (being the zero clearing pin), the input end of the second triple gate U1_B of switching executive circuit 102 is by cA18 pin (being the address input pin) receiver address input signal cA18, the output terminal of the second triple gate U1_B is by fA18 pin (being the address output pin) OPADD output signal fA18, second resistance R 2 of timer circuit 103, the link of second capacitor C 2 is by status pin (being status pin) output timer status signal status.
Present embodiment is by inserting a map addresses and commutation circuit 100 between central processor CPU chip and bootstrap memory flash chip, two region memories at a slice bootstrap memory flash chip contain two parts of identical guidance codes, a copy of it is as main guidance code, use main guidance code to start and the down-stream of packing under the normal condition, when its guidance code is ruined, use the backup guidance code to start and boot, to reach the enhanced system fault freedom, improve the purpose of system reliability.
The principle of work of map addresses of the foregoing description and commutation circuit 100 and the system that is employed thereof is as follows:
The present invention begin from system's electrifying startup to the whole procedure operational process of shutdown be divided into " unloading phase " and " master routine stage " two stages.The unloading phase be divided into " normal start " and " fault initiating " two types again.Map addresses shown in Figure 1 and commutation circuit only to the unloading phase work.In the master routine operation phase, cA18 always equates that with the signal of fA18 map addresses and commutation circuit effect conductively-closed have been fallen, just as not having map addresses and commutation circuit in the system.
As shown in Figure 2, the timer clear circuit 101 of map addresses and commutation circuit 100 receive clear pin input come from the high level pulse of central processor CPU the time, at the output terminal Point_C of first triple gate U1_A point output low level reset signal.When the clear pin kept low level, high level or high-impedance state for a long time, then the Point_D point became low level state, and the output of the first triple gate U1_A becomes high-impedance state, does not export reset signal.
As shown in Figure 2, when the control end of the second triple gate U1_B of switching executive circuit 102 is low level, its output terminal keeps high-impedance state, owing to draw effect on the 3rd resistance R 3, this moment, address output pin fA18 went up the fixing high level signal of output, when the address of central processing unit CPU by address input pin cA18 output be the 0x00000000-0x0003ffff scope (as shown in Figure 3, be the backup boot section of bootstrap memory) time, be mapped to the 0x00040000-0x0007ffff scope (master boot sector) of flash address by replay.When the control end of the second triple gate U1_B was high level, this moment, the output signal of address output pin fA18 was identical with the incoming signal level of address input pin cA18, and the flash address that is directed is identical with the CPU OPADD.When constituting the executive circuit of map addresses and switching with triple gate and resistance, the address of master boot sector is different with the enabling address of central processor CPU, and the Be Controlled position that is the central processor CPU enabling address is through the address after reverse.The address of backup boot section is identical with the enabling address of central processor CPU.
As shown in Figure 2, second resistance R 2 in the timer circuit 103 and the link of second capacitor C 2 are input end (Point_C point), also are output terminal (Point_B points).When it does not have overtime overflowing, at low level signal of Point_B point output; High level signal of the output of ordering at Point_B in the time of overtime overflowing.The Point_C point is the input end of the reset signal of this timer, in the time of Point_C point input low level, and 2 discharges of second capacitor C, timer zero clearing.When the first triple gate U1_A is ordered when being output as high-impedance state at Point_C, second capacitor C 2 is slowly charged by second resistance R 2.If be not cleared in the charging process, then the Point_B point voltage becomes high level after a period of time, and timer overflows.The level signal that point_B is ordered is represented the state whether timer overflows, this signal is connected on the GPIO pin that is configured to import of central processor CPU, can judge it is normal startup by the level value that software is read this pin, or fault initiating.
With Fig. 1, circuit structure shown in Figure 2 and process flow diagram shown in Figure 5 is example, further specifies the method for switching and booting codes in double memory area of the present invention.
Once normal CPU start-up course comprises the steps:
The central processor CPU electrification reset, and read again by bus and to get article one instruction, instruction address is 0x00000100.Central processor CPU becomes 0x00040100 after article one instruction address 0x00000100 of bus output is through map addresses and commutation circuit, central processor CPU is actually from the flash article one instruction of having packed into of this address of 0x00040100.
Central processor CPU continues the subsequent instructions of packing into, and the address of these instructions is remapped to the main district that guides to by map addresses and commutation circuit 100.
As shown in Figure 5, in the central processor CPU program operation process, reading status pin logical value is 0, judge that this is a subnormal start-up course, then at set intervals, high level pulse of output on the clear pin, the RC timer that zero clearing second resistance R 2 and second capacitor C 2 constitute.
Before the boot end of run, software waits for that status pin logical value becomes 1, and master routine again brings into operation.
And once out of order CPU start-up course comprises the steps:
The central processor CPU electrification reset, and read article one by bus and instruct, instruction address is 0x00000100, central processor CPU becomes 0x00040100 after article one instruction address 0x00000100 of bus output process map addresses and commutation circuit 100, central processor CPU is actually from bootstrap memory flash and goes up this address of 0x00040100 packed into article one instruction, i.e. master boot sector.
Central processor CPU continues the subsequent instructions of packing into, and the address of these instructions is remapped to the main district that guides to by address switchover and mapping circuit mapping.
As shown in Figure 5, in the central processor CPU boot operational process, reading status pin logical value is 0, judge that this is a subnormal start-up course, then at set intervals, high level pulse of input on the clear pin, the RC timer that zero clearing second resistance R 2 and second capacitor C 2 constitute.
Because the code of storing on the master boot sector is destroyed, at this moment central processor CPU becomes " deadlock " state, promptly is absorbed in a certain section illegal code area operation.This moment, central processor CPU can not regularly be exported the high level pulse signal on the clear pin, and the clear pin becomes fixing high level or low level, and central processor CPU can not normally be exported WDT simultaneously.
After a period of time, the Point_D point becomes low level among Fig. 2, and keeps low level state always, and the first triple gate U1_A keeps off state.After a period of time, the timer expiry that second resistance R 2 and second capacitor C 2 constitute overflows, and the Point_B point voltage is a high level, and the second triple gate U1_B becomes opening state, and then the address of central processor CPU output will no longer be remapped.
After a period of time, watchdog circuit is overtime, and central processor CPU is resetted again.
Central processor CPU reads article one instruction by bus, instruction address is 0x00000100, through the address after map addresses and the commutation circuit 100 still is 0x00000100, the backup boot section load of central processor CPU from the bootstrap memory flash.
In the central processing unit cpu boot operational process, judge that the logical value that status reads is 1, judge that this is the primary fault start-up course, Main Boot Record is damaged as can be known, no longer regularly export the high level pulse signal on the clear pin later in the operational process, to keep from backup boot section load.
Behind the boot end of run, master routine brings into operation.
From the various embodiments described above as can be seen, the publication number of the present invention and prior art is that US2004/0250058 A1, application number are that U.S.'s application for a patent for invention of 10/861,737 is compared, and has following advantage:
1, the present invention uses the RC circuit to realize delay function, and circuit is simple, and cost is low;
2, in the prior art, the clear pin comes the zero clearing delay counter with high level signal, and the present invention comes to discharge for time-delay RC circuit with periodically exporting the high level pulse signal on the clear pin.When the program of CPU operation breaks down, if the clear pin of CPU is in high level state, then the counter of prior art is zero always, upset never, CPU can not reset yet, can't reload guidance code from backup area, not reach the effect of backup, then there is not this problem in the present invention;
3, map addresses of the present invention and switching device shifter only use an address wire, and unlike the high bit address wire, whether the address of being indifferent to the CPU visit is the guidance code memory block.The method that need remap the address that judges whether of the present invention is: operational process is divided into " startup " and " normal operation " two stages, only to the unloading phase remap, do not remap at normal operating phase, directly cA18 and fA18 are communicated with (see figure 1), thereby method of the present invention has been simplified the wiring of circuit version, it is long-pending to have reduced the circuit space of a whole page, and cost is lower.
4, do not comprise watchdog function in address switchover of the present invention and the mapping circuit, on the boot section in the guiding failure, utilize the outer watchdog circuit CPU that resets, then from backup boot section guidance code.The commercialization watchdog chip cost of Xiao Shouing is very low in the market, and have " supply voltage monitoring " and " software crash monitoring " two kinds of functions, and the inner watchdog function of realizing of prior art does not have the supply voltage monitoring function, so system also need dispose special voltage monitoring chip.With respect to prior art, the present invention has saved cost.
Disclosed all features in this instructions, or the step in disclosed all methods or the process except mutually exclusive feature and/or step, all can make up by any way.
Disclosed arbitrary feature in this instructions (comprising any accessory claim, summary and accompanying drawing) is unless special narration all can be replaced by other equivalences or the alternative features with similar purpose.That is, unless special narration, each feature is an example in a series of equivalences or the similar characteristics.
The present invention is not limited to aforesaid embodiment.The present invention expands to any new feature or any new combination that discloses in this manual, and the arbitrary new method that discloses or step or any new combination of process.
Claims (10)
1. the device of a switching and booting codes in double memory area is characterized in that, comprises
Timer circuit, the output mapping control signal is cleared when receiving reset signal;
The timer clear circuit receives the zero clearing control signal that comes from the external world, exports above-mentioned reset signal;
Switch executive circuit, receive the address input signal that comes from the external world, under the control of above-mentioned mapping control signal, the OPADD output signal.
2. a kind of device of switching and booting codes in double memory area according to claim 1 is characterized in that described timer circuit inputs to the switching executive circuit with reset signal as mapping control signal when being cleared.
3. a kind of device of switching and booting codes in double memory area according to claim 1 is characterized in that, described timer circuit is made of second resistance, second electric capacity of series connection, and both links are connected with the timer clear circuit.
4. a kind of device of switching and booting codes in double memory area according to claim 1, it is characterized in that, described timer clear circuit comprises first resistance and first electric capacity that the series connection back is connected with ground, and wherein the other end of first electric capacity receives and comes from extraneous zero clearing control signal; First resistance is connected the control end of first triple gate with the link of first electric capacity, the input end of first triple gate is by the 4th resistance eutral grounding, and the output terminal of first triple gate is connected with timer;
Described zero clearing control signal is the high level pulse signal.
5. a kind of device of switching and booting codes in double memory area according to claim 1, it is characterized in that, described switching executive circuit comprises second triple gate and the 3rd resistance that is connected with its output terminal, the input end of second triple gate receives and comes from extraneous address input signal, its control end connects timer circuit, its output terminal OPADD output signal.
6. a kind of device of switching and booting codes in double memory area according to claim 1, it is characterized in that, described switching executive circuit comprises NOR gate circuit and the 3rd resistance that is connected with its output terminal, an input end of this NOR gate circuit receives and comes from extraneous address input signal, another input end connects timer circuit, its output terminal OPADD output signal.
7. as the device of a kind of switching and booting codes in double memory area as described in as described in the claim 3, it is characterized in that, described timer clear circuit comprises first resistance and first electric capacity that the series connection back is connected with ground, and wherein the other end of first electric capacity receives and comes from extraneous zero clearing control signal; First resistance is connected the control end of first triple gate with the link of first electric capacity, the input end of first triple gate is by the 4th resistance eutral grounding, and the output terminal of first triple gate is connected with timer;
Described switching executive circuit comprises second triple gate and the 3rd resistance that is connected with its output terminal, and the input end of second triple gate receives and comes from extraneous address input signal, and its control end connects timer circuit, its output terminal OPADD output signal.
8. the system of a switching and booting codes in double memory area is characterized in that, comprises
Central processing unit, output zero clearing control signal and address input signal receive the timer status signal;
Bootstrap memory respectively stores a mutually the same guidance code, the receiver address output signal in two zone;
Map addresses and commutation circuit receive zero clearing control signal and address input signal, output timer status signal and address output signal;
Watchdog circuit, when guidance code is directed failing in one of them zone on bootstrap memory, this watchdog circuit central processing unit that resets, the guidance code of packing in another zone then.
Described map addresses and commutation circuit comprise timer circuit, timer clear circuit, switch executive circuit;
Described timer circuit is made of second resistance, second electric capacity of series connection, and both links are connected with timer clear circuit, switching executive circuit;
Described timer clear circuit comprises first resistance and first electric capacity that the series connection back is connected with ground, and wherein the other end of first electric capacity receives and comes from extraneous zero clearing control signal; First resistance is connected the control end of first triple gate with the link of first electric capacity, the input end of first triple gate is by the 4th resistance eutral grounding, and the output terminal of first triple gate is connected with timer;
Described switching executive circuit comprises second triple gate and the 3rd resistance that is connected with its output terminal, and the input end of second triple gate receives and comes from extraneous address input signal, and its control end connects timer circuit, its output terminal OPADD output signal.
9. the method for a switching and booting codes in double memory area is characterized in that, comprises
Guide the memory block high-order address signal by map addresses and commutation circuit mapping between central processing unit and the bootstrap memory;
The normal periodically high level pulse of the expression mapping whether map addresses and commutation circuit basis receive central processing unit output guides the memory block high-order address signal;
If normal condition, then the enabling address signal of central processing unit is mapped to the master boot sector of bootstrap memory by map addresses and commutation circuit, and the code in the master boot sector is read in guiding, and central processing unit starts successfully that the back continues to export the periodicity high level pulse;
If malfunction, then the enabling address signal of central processing unit is mapped to the backup boot section of bootstrap memory by map addresses and commutation circuit, the code in the backup boot section is read in guiding, does not export periodically high level pulse after central processing unit starts successfully.
10. as the method for a kind of switching and booting codes in double memory area as described in the claim 9, it is characterized in that central processing unit starts from master boot sector, the status signal of map addresses and commutation circuit output expression normal condition; Central processing unit starts from the backup boot section, the status signal of map addresses and commutation circuit output expression malfunction, and the status signal of central processing unit check map addresses and commutation circuit, judgement is normal starting state or fault initiating state.
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