JP3733746B2 - Programmable controller - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a programmable controller including dedicated hardware capable of processing both basic bit operation instruction processing and multi-bit application instruction processing.
[0002]
[Prior art]
Programmable controllers are widely used for controlling industrial devices, machines, and FA devices. As shown in FIG. 7, the simplest configuration is composed of various I / Os 1 connected to the controlled object, a memory 2 storing control programs and data, and a general-purpose microprocessor (hereinafter referred to as MPU) 3. The MPU 3 sequentially interprets and executes the stored instructions to realize a control function. By the way, it is required to process a larger number of input / output signals at a high speed in response to a demand for higher complexity and a device to be controlled. Therefore, as shown in FIG. 8, dedicated hardware (processor <hereinafter referred to as BPU>) capable of executing a basic instruction mainly including bit operation processing and an application instruction for processing data composed of a plurality of bits. ) 4 realizes high speed, MPU3 that performs communication processing, peripheral processing, application command execution, etc., memory that stores user program and internal relay information, etc., and exchanges information with control targets and peripheral devices There is provided a programmable controller composed of various I / Os 1 for performing.
[0003]
As a means for further speeding up, a configuration is also provided in which a control program created by a user is converted into a format suitable for high-speed execution and then executed by the BPU. A configuration example of this programmable controller is shown in FIG. In the configuration of FIG. 9, in addition to the configuration of FIG. 8, a second memory 5 for storing the program of the BPU 4 is added. The control program created by the user stored in the first memory 2 is converted and transferred to the second memory 5, and the BPU 4 reads the program from the second memory 5 and sequentially interprets and executes the control function. . In the case of the configuration example of FIG. 9, a RISC type instruction system having a simplified structure compared to the original instruction stored in the first memory 2 is adopted for the instruction expanded in the second memory 5, By adopting a pipeline configuration, a higher speed can be realized compared to the configuration of FIG. However, because two sets of instruction memory are required and the bus configuration differs between the MPU 3 side and the BPU 4 side depending on the configuration of the instruction word, the circuit configuration is complicated, for example, a new bus interface unit (BIU) 6 is required. As a result, the cost increases accordingly.
[0004]
[Problems to be solved by the invention]
As described above, in response to the demand for higher speeds, dedicated hardware (processors) for configuring programmable controllers has been developed to improve the operating speed of the entire system. At that time, an optimum instruction word to be executed by dedicated hardware has been developed in consideration of the configuration of the programmable controller, unlike that of a general-purpose microprocessor.
[0005]
On the other hand, there is a request to process a larger number of input / output signals, but once a dedicated hardware instruction word is defined, there may be a problem that it becomes difficult to meet the request. In order to explain this problem, FIG. 10 shows an example of the structure of instruction words of dedicated hardware. The instruction word is 16 bits long, of which 6 bits are an obcode part (OP Code) indicating the type of instruction, and the remaining 10 bits are a part indicating a data number (DATA No.). In this case, the number of data that can be handled by one instruction is 1024 that can be expressed in 10 bits, and such an instruction word is defined based on the determination that the number of data points is sufficient when the instruction word is developed. However, this command may not be able to handle a request to process a larger number of input / output signals, that is, a request to handle a larger number of data points.
[0006]
Therefore, it is necessary to consider modifying the instruction word so that it can handle a larger number of data points. However, in order not to waste development resources up to that point, the modified instruction word has upward compatibility with conventional instruction words. It is desirable. FIG. 11 shows a configuration example of an instruction word modified to satisfy the condition. An unused code in the instruction word is used as an extension instruction, and an instruction word preceded by the extension instruction is interpreted by adding a predetermined value to the data number. In the example of FIG. 11, 1024 is added to the data number for the instruction word prefixed with the extended instruction (Expand1), and 2048 is added to the data number for the instruction word prefixed with the extended instruction (Expand2). . 11 (a) is interpreted as an ST command (start command) for the X relay No. 100, FIG. 11 (b) is interpreted as an ST command for the X relay 1124, and FIG. 11 (c) is interpreted as an ST command for the X relay 2 148. The
[0007]
In this way, by using the unused code of the instruction word as an extension instruction used for extending the data area, it is possible to meet the demand for processing a large number of input / output signals. Similarly, by using the unused code for indirect designation of the data address called index modification, it can be used to increase the degree of freedom of program development. By the way, when the instruction word before adding such an extension instruction is developed at the same time as the programmable controller having the configuration of FIG. 8, the BPU 4 executing the instruction word cannot interpret and execute the added extension instruction. Such an instruction word cannot be used. In addition, the programmable controller having the configuration shown in FIG. 9 that executes the control program created by the user after converting it into a completely different type of instruction word can cope with the addition of such an extension instruction. In exchange for the increase and the improvement of the processing speed, there is a disadvantage that the cost increases.
[0008]
On the other hand, as shown in FIG. 7, it is possible to interpret and execute instructions only by software processing of the MPU 3 without using dedicated hardware (BPU). However, in this case, it becomes difficult to meet the demand for high-speed processing.
[0009]
The present invention has been made in view of the above points, and its object is to execute an instruction word having an extension instruction for expanding a data area or indirectly specifying an address at high speed. An object of the present invention is to provide a programmable controller that can be manufactured at low cost.
[0010]
[Means for Solving the Invention]
The invention of claim 1 includes an I / O connected to a control target, a memory for storing a control program and data, and a general-purpose microprocessor that at least executes communication processing, peripheral processing, and application instructions. Instructions such as dedicated extension instructions that enable data area expansion and indirect address specification, basic bit operation instructions, multi-bit application instructions, etc. If a bit operation instruction or multi-bit application instruction is executed, processing of those instructions is executed. When an extended instruction is read, the subsequent normal instruction is also read, and the contents of the instruction are combined with these extended instruction and normal instruction. After interpreting the above, it is provided with dedicated hardware for executing instruction processing.
[0011]
According to a second aspect of the present invention, in the first aspect of the invention, the dedicated hardware is controlled by a state machine, and the process for determining whether the instruction is read from a normal instruction or an extended instruction is separated into independent states. It is characterized by.
[0012]
According to a third aspect of the present invention, in the first aspect of the present invention, the dedicated hardware is controlled by a state machine, the state in which the instruction is read out, the state in which the first word is read out, and the instruction word in the second and subsequent words. It is characterized by comprising a state to be read.
[0013]
According to a fourth aspect of the present invention, in the process of reading an extension instruction according to any one of the first to third aspects, the contents of the read extension instruction are converted into a minimum data amount that can be determined later, and It is stored in a dedicated storage means, and instruction execution processing is performed using the stored data.
[0014]
According to the invention of claim 5, in the invention of any one of claims 1 to 4, among the instructions executed by the dedicated hardware, the instructions for performing similar processing are classified into a plurality of groups, and the dedicated hardware is controlled. The state in which the state machine executes instructions is made independent for each group.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
The present invention implements the configuration shown in FIG. 8 in consideration of a trade-off between operation speed and cost when realizing a programmable controller that executes an instruction word to which an extension instruction for extending the number of data points or indirectly specifying an address is added. I will adopt it. Here, the BPU4, which is dedicated hardware for executing the extended instruction, interprets the contents of the instruction by reading the normal instruction when the normal instruction is read, and further reading the subsequent normal instruction when the extended instruction is read. Can be executed. Hereinafter, the present invention will be described with reference to embodiments.
[0016]
(Embodiment 1)
In this embodiment, as shown in FIGS. 11B and 11C, not only a normal instruction but also a separately defined extension instruction (Expand) is arranged before a normal instruction, thereby expanding the data area and addressing. Defines instruction words that can be indirectly specified, implements dedicated hardware that sequentially reads, interprets and executes the instruction words, and implements a programmable controller having the same configuration as that shown in FIG. Was realized by the state machine shown in FIG. The meaning of the states used in Fig. 1 is IF: Instruction Read (Instruction Fetch)
ID: Instruction Decode
EX: Execute
In FIG. 1, after reading an instruction in the IF state (stage) and interpreting it in the ID state (stage), if it is an extended instruction, it returns to the IF state (stage) again and further subsequent instructions. A read process is performed, the contents of the instruction are interpreted together with the extension instruction and the subsequent instruction, and the process proceeds to instruction execution (EX1,...). If the read instruction is not an extended instruction (Expand) but a normal instruction, the process proceeds to instruction execution processing such as data reading / writing and arithmetic processing according to the instruction interpretation (decoding) result. In the figure, only a part of the state machine is illustrated. Since the hardware configuration is the same as that in FIG. 8, reference is made to FIG. 8, which is not shown here.
(Embodiment 2)
In the case of an instruction prefixed with an extended instruction as in the present invention, instruction decoding and instruction reading are repeated as described above. In this embodiment, this instruction decoding process is performed in the state transition of the state machine of FIG. As shown in FIG. 1, ID1: Processing for determining a normal instruction or an extended instruction ID2: Dividing into other instruction decoding processes, reading an instruction in the IF1 state (stage), and normal instruction or in an instruction decoding state (stage) ID1 By executing the extension instruction determination process, it is possible to speed up the instruction execution.
[0017]
As shown in the timing charts at the time of instruction execution in FIGS. 3A and 3B, the configuration using the state machine of FIG. 1 that does not divide the instruction decoding state (stage) in the case of only normal instructions (FIG. 3A In the case of ()), the instruction execution time does not change even in the case where the instruction decoding state (stage) is divided as in the present embodiment (in the case of FIG. 3B). However, when an instruction in which an extended instruction is arranged before a normal instruction is executed, in this embodiment, as shown in FIG. 3E, the first instruction word is read and it is determined that it is an extended instruction. Further, since the operation of reading the instruction word becomes faster, the instruction execution time can be shortened compared to the case of FIG. 3D using the state machine of FIG. 1 in which the instruction decoding state (stage) is not divided. Since the hardware configuration is the same as that in FIG. 8, reference is made to FIG. 8, which is not shown here.
[0018]
(Embodiment 3)
By the way, since the BPU 4 that executes an instruction has only one instruction register for reading an instruction, if the read instruction word is an extension instruction, the information is stored in the BPU 4 and further subsequent instructions are read. This is because if the information that the extended instruction is read is not stored, the contents of the instruction register are overwritten by subsequent instructions. However, the information that this extended instruction has been read must be cleared each time the first instruction word is read. Even if the instruction currently being executed is an instruction that does not prepend an extension instruction, if the previously executed instruction is an instruction with an extension instruction, the information on the extension instruction has an adverse effect on the current instruction execution. Will be affected.
[0019]
Further, if the information of the extension instruction is unconditionally cleared when the instruction word is read, the extension instruction is cleared when the instruction is read after the extension instruction is read, so that the instruction cannot be executed correctly. As described above, the extension instruction information must be cleared when the first instruction word is read. To achieve this, a complicated control circuit is configured for reading the instruction word and setting and clearing the extension instruction information. Need arises. Therefore, by implementing the instruction read processing of the state machine in two states, a state in which the first word is read and a state in which the second and subsequent instruction words are read out, a dedicated hardware control circuit that executes the instructions can be simplified. To do.
[0020]
For the state transition of the state machine that controls the BPU 4 of this embodiment, the state transition of the state machine shown in FIG. 2 is used as in the above embodiment. FIG. 4 shows a timing chart at the time of instruction execution in the present embodiment.
[0021]
In this embodiment, the extended instruction information is stored in the extended instruction information register (in the BPU 4 as shown in FIG. 4B or FIG. 4D) in the IF1 state (stage) in which the instruction is read as shown in FIG. 4 (a) and (b) with only a normal instruction, and even in the case of FIGS. 4 (c) and 4 (d) in which an extended instruction is preceded, the previous instruction is started. Can cancel the effect of the order. When the first instruction word read as a result of decoding is an extension instruction and further instruction words need to be read, the instruction reading is performed by changing to the IF2 state (stage) instead of the IF1 state (stage). Since the extended instruction information (Expand 1) set as a result is not cleared, the extended instruction information (Expand 1) can be used to execute an instruction without error.
[0022]
When an extension instruction for data area expansion or address indirect designation is read in this way, the information is stored in the extension instruction information register, which is a dedicated storage means inside the BPU 4, and at this time, the extension instruction is stored in the instruction word. If the data is converted into a minimum amount of information that can be used to distinguish an extension instruction and stored instead of being stored as it is, the scale of the hardware can be reduced. As shown in FIG. 10, if the data width of the instruction word is 16 bits and there are a total of 7 types of extension instructions, a 16-bit storage location is required if the instruction words are stored as they are. Since 7 types of extension instructions can be expressed with a total of 4 bits, 1 bit of presence / absence of extension instructions and 3 bits indicating the number of extension instructions, if the extension instruction information is converted in this way, a storage area of 4 bits is required.
[0023]
The “extended instruction information register” shown in FIG. 4 is configured with a minimum bit width necessary for determining the presence / absence and type of an extended instruction.
[0024]
(Embodiment 4)
By the way, after the instruction is decoded, instruction execution processing such as data reading / writing and arithmetic processing is performed according to the decoded contents. This is the EX1 and EX2 states (stages) shown in the state machine of FIG. 2, but there are various data addresses to be accessed depending on the type of instruction of the programmable controller, and access to the memory is not required depending on the type of instruction in the first place. Or one that needs to be read from memory, one that reads data and performs arithmetic processing based on it, writes the result back to one memory, or reads multiple memory values to perform arithmetic processing There are various things, such as those that write the results into a plurality of memories, all of which are divided into cases and executed in EX1, EX2,... State (stage), the processing per state becomes complicated, and instruction execution It takes a lot of time. Therefore, by classifying the instructions of the programmable controller into groups of instructions that perform similar processing by paying attention to the state of access to the memory, etc., and having the state that executes the instructions of the state machine independently for each group of instructions In this embodiment, the instruction execution speed is improved.
[0025]
FIG. 5 shows the state transition of the state machine of the present embodiment, and FIG. 6 shows a timing chart for comparing the instruction execution time in the second embodiment with the instruction execution time in the present embodiment.
[0026]
The state machine of this embodiment has a plurality of states (EXA1,..., EXB1,..., EXA1,..., EXB1,. EXC1,...). For this reason, the scale of the state machine becomes large and the scale of the BPU 4 which is dedicated hardware also becomes large, but on the other hand, since the contents of processing executed by one of the EX states (stages) are reduced, the state (stage) becomes one. Such time can be reduced. As shown in FIG. 6B, by dividing into a plurality of instructions according to the instruction grouping, the processing related to the EX state (stage) becomes faster than the case shown in FIG. 6A. As a result, the instruction execution speed is increased. Can be improved.
[0027]
【The invention's effect】
The invention of claim 1 includes an I / O connected to a control target, a memory for storing a control program and data, and a general-purpose microprocessor that at least executes communication processing, peripheral processing, and application instructions. Instructions such as dedicated extension instructions that enable data area expansion and indirect address specification, basic bit operation instructions, multi-bit application instructions, etc. If a bit operation instruction or multi-bit application instruction is executed, processing of those instructions is executed. When an extended instruction is read, the subsequent normal instruction is also read, and the contents of the instruction are combined with these extended instruction and normal instruction. Since it has dedicated hardware that executes instruction processing after interpreting, instruction words with extended instructions to expand the data area and indirectly specify addresses There is an effect that can be performed, also configured with easy cost is inexpensive.
[0028]
According to a second aspect of the present invention, in the first aspect of the invention, the dedicated hardware is controlled by a state machine, and the process of determining whether the instruction is read from a normal instruction or an extended instruction is separated into independent states. There is an effect that it is possible to realize a high speed when executing an instruction preceded by the extended instruction.
[0029]
According to a third aspect of the present invention, in the first aspect of the invention, the dedicated hardware is controlled by a state machine, the state in which the instruction is read out, the state in which the first word is read out, and the instruction word in the second and subsequent words. Since it is configured with a read state, it is possible to simplify the process of reading instructions and storing information of extended instructions, and the design of the control circuit can be facilitated.
[0030]
According to a fourth aspect of the present invention, in the process of reading an extension instruction according to any one of the first to third aspects of the invention, the contents of the read extension instruction are converted into a minimum data amount that can be discriminated later. Since it is stored in the dedicated storage means and the instruction execution process is performed using the stored data, the scale of the storage means for storing the read extended instruction information can be reduced, and the instruction for executing the instructions in the programmable controller can be reduced. There is an effect that the scale of the hardware portion can be reduced.
[0031]
According to a fifth aspect of the present invention, in the invention according to any one of the first to fourth aspects, among the instructions executed by the dedicated hardware, the instructions for performing similar processing are classified into a plurality of groups, and the dedicated hardware is controlled. Since the state in which the state machine executes instructions is made independent for each group, the instruction execution speed can be improved.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a state machine that controls dedicated hardware used in the first embodiment.
FIG. 2 is a configuration diagram of a state machine that controls dedicated hardware used in the second embodiment.
FIG. 3 is a timing chart for explaining the operation.
FIG. 4 is a timing chart for explaining operations of the third embodiment.
FIG. 5 is a configuration diagram of a state machine that controls dedicated hardware used in the fourth embodiment.
FIG. 6 is a timing chart for explaining the operation of the above.
FIG. 7 is a configuration diagram illustrating an example of a programmable controller.
FIG. 8 is a configuration diagram illustrating another example of a programmable controller.
FIG. 9 is a configuration diagram illustrating another example of a programmable controller.
FIG. 10 is an explanatory diagram of the structure of an instruction word of a programmable controller.
FIG. 11A is an explanatory diagram of a normal instruction.
(B) is an explanatory diagram of a normal instruction and an extended instruction.
(C) is an explanatory diagram of a normal instruction and another extension instruction.
[Explanation of symbols]
IF instruction read state (stage)
ID Instruction decoding state (stage)
EX1, ... Execution state (stage)

Claims (5)

It has an I / O connected to the control target, a memory for storing control programs and data, and a general-purpose microprocessor that at least executes communication processing, peripheral processing, and application instructions, and is arranged before normal instructions. In this way, instruction words such as dedicated extension instructions that enable data area expansion and indirect address specification, basic bit operation instructions, and multi-bit application instructions are read sequentially, basic bit operation instructions, and multiple bits. If it is an application instruction, the processing of those instructions is executed. When an extended instruction is read, the subsequent normal instructions are also read. After interpreting the contents of the instruction by combining these extended instructions and normal instructions, A programmable controller comprising dedicated hardware for executing processing. 2. The programmable controller according to claim 1, wherein the dedicated hardware is controlled by a state machine, and the process of determining whether the instruction is a normal instruction or an extended instruction is separated into an independent state from a state in which the instruction is read. 2. The state in which the dedicated hardware is controlled by a state machine and the instruction is read out is configured by a state in which the first word is read and a state in which the second and subsequent instruction words are read. The programmable controller described. In the process of reading an extended instruction, the contents of the read extended instruction are converted into a minimum amount of data that can be discriminated later, stored in an internal dedicated storage means, and executed using the stored data The programmable controller according to any one of claims 1 to 3. Among the instructions executed by the dedicated hardware, the instructions for performing similar processing are classified into a plurality of groups, and the states for executing instructions of the state machine for controlling the dedicated hardware are made independent for each group. The programmable controller in any one of Claims 1 thru | or 4.

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