JPH11353174A - Programmable controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the programmable controller which can execute at a high speed instruction words having extension instructions for expanding a data area and indirectly specifying addresses and is advantageous in cost. SOLUTION: In an IF state (stage), an instruction is read out and interpreted in an ID state (stage) and when it is an extension instruction, a return to the IF state (stage) is made to read a following instruction; and the contents of both the extension instruction and following instruction are interpreted together and the instructions begin to be processed (EX1...). When the read instruction is not the extension instruction (Expand), but a normal instruction, an instruction executing process such as data reading and writing, and an arithmetic process is performed according to the instruction interpretation(decoding) result.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller having dedicated hardware capable of processing both basic bit operation instruction processing and multi-bit application instruction processing.

[0002]

2. Description of the Related Art Programmable controllers are widely used for controlling industrial equipment, machines, and FA equipment. The simplest configuration is, as shown in FIG. 7, various I / Os 1 connected to a control target, a memory 2 storing control programs and data, and a general-purpose microprocessor (hereinafter referred to as MPU) 3.
The control function is realized by the MPU 3 sequentially interpreting and executing the instructions stored in the memory 2. By the way, according to the complexity of the device to be controlled and the demand for higher speed, it is required to process a larger number of input / output signals at high speed. For this reason, as shown in FIG. 8, dedicated hardware (processor <hereinafter referred to as BPU>) capable of executing a basic instruction mainly for bit operation processing and a negative part of an application instruction for processing data composed of a plurality of bits. 4) Realizes high-speed processing, MPU 3 for performing communication processing, peripheral processing, execution of applied instructions, etc., memory for storing information of user programs and internal relays, and exchange of information with controlled objects and peripheral devices. Various I / O1 to perform
There is provided a programmable controller composed of the above.

As means for further increasing the speed, there is also provided a configuration in which a control program created by a user is converted into a format suitable for high-speed execution and then executed by a BPU. FIG. 9 shows a configuration example of this programmable controller.
Shown in In the configuration of FIG. 9, in addition to the configuration of FIG.
The second memory 5 for storing the program is added. The control program created by the user stored in the first memory 2 is converted and transferred to the second memory 5,
The BPU 4 implements a control function by reading programs from the second memory 5 and sequentially interpreting and executing the programs. In the case of the configuration example of FIG. 9, the RISC-type instruction system whose structure is simplified as compared with the original instruction stored in the first memory 2 is adopted for the instruction to be expanded in the second memory 5, or the BPU 4 is used. By adopting the pipeline configuration, it is possible to further increase the speed as compared with the configuration in FIG. However, depending on the necessity of two sets of instruction memory and the configuration of instruction words, MPU
Since the bus configuration is different between the 3 side and the BPU 4 side, the circuit configuration becomes complicated, for example, a new bus interface unit (BIU) 6 is required, and the cost increases accordingly.

[0004]

As described above, in response to the demand for high speed, dedicated hardware (processor) for configuring a programmable controller has been developed to improve the operation speed of the entire system. At that time, an instruction word to be executed by dedicated hardware has been developed in consideration of the configuration of a programmable controller, which is different from that of a general-purpose microprocessor.

On the other hand, there is a demand to process a larger number of input / output signals. However, once a dedicated hardware command is determined, it may be difficult to meet the demand. To explain this problem, FIG. 10 shows an example of the structure of an instruction word of dedicated hardware. It is assumed that the instruction word is 16 bits long, of which 6 bits are an Obe code portion (OP Code) indicating the type of instruction, and the remaining 10 bits are a portion indicating a data number (DATA No.). In this case, the number of data that can be handled by one instruction is 1024, which can be expressed by 10 bits. At the time of developing the instruction word, such an instruction word was defined based on the judgment that this number of data points was sufficient. However, a request to process a larger number of input / output signals, that is, a request to handle a larger number of data points, may not be able to be handled by this command.

Therefore, it is necessary to consider modifying the instruction word so as to handle a larger number of data points. However, the modified instruction word is upwardly compatible with the conventional instruction word so as not to waste development resources up to that time. It is desirable to have FIG. 1 shows a configuration example of a command word modified to satisfy the condition.
It is shown in FIG. An unused code in the instruction word is used as an extension instruction, and the instruction word preceding the extension instruction is interpreted by adding a predetermined value to the data number. In the example of FIG. 11, it is assumed that 1024 is added to the data number for the instruction word prefixed with the extension instruction (Expand1), and 2048 is added to the data number for the instruction word prefixed with the extension instruction (Expand2). . That is, FIG.
1 (a) is interpreted as an ST instruction (start instruction) for X relay 100, FIG. 11 (b) is interpreted as an ST instruction for X relay 1124, and FIG. 11 (c) is interpreted as an ST instruction for X relay 2 148.

By using an unused code of an instruction word as an extension instruction used to extend a data area, it is possible to meet a demand for processing a large number of input / output signals. Similarly, by using an unused code for indirect specification of a data address called an index modification, it is possible to increase the degree of freedom in program development. By the way, if the instruction word before adding such an extended instruction is developed simultaneously with the programmable controller having the configuration of FIG. 8, the BPU 4 executing the instruction word cannot interpret and execute the added extended instruction. Such a command cannot be used. Further, the programmable controller having the configuration shown in FIG. 9, which converts the control program created by the user into a completely different type of instruction word and then executes it, can cope with the addition of such an extended instruction. In exchange for the increase in the processing speed and the increase in the processing speed, there is also a disadvantage that the cost increases.

On the other hand, as shown in FIG. 7, dedicated hardware (B
The instruction can be interpreted and executed only by the software processing of the MPU 3 without using the PU, but in this case, it becomes difficult to meet the demand for high-speed processing.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has as its object to quickly execute an instruction word having an extended instruction for expanding a data area or indirectly specifying an address. It is another object of the present invention to provide a programmable controller which can be implemented at a low cost.

[0010]

According to the first aspect of the present invention, at least an I / O connected to a control target, a memory for storing a control program and data, and communication processing, peripheral processing, and execution of application instructions are performed. It has a general-purpose microprocessor and a dedicated extended instruction that can be expanded before the normal instruction to expand the data area and indirectly specify the address, basic bit operation instructions, multi-bit applied instructions, etc. Are sequentially read, the basic bit operation instruction, and if it is a multi-bit application instruction, the processing of those instructions is executed. If an extended instruction is read, the subsequent normal instruction is also read. The present invention is characterized in that special hardware is provided for executing the processing of the instruction after interpreting the contents of the instruction together with the normal instruction.

According to a second aspect of the present invention, in the first aspect of the present invention, the dedicated hardware is controlled by a state machine, and a process of determining whether an instruction is a normal instruction or an extended instruction from an instruction reading state is changed to an independent state. It is characterized by being separated.

According to a third aspect of the present invention, in the first aspect of the present invention, the dedicated hardware is controlled by a state machine, and the instruction readout state is changed to a state in which the first word is read and a state in which the first word is read. And a state for reading a command word.

According to a fourth aspect of the present invention, in the processing for reading an extension instruction according to any one of the first to third aspects, the content of the read extension instruction is converted into a minimum data amount that can be determined later. Stored in dedicated internal storage means for executing the instruction execution process using the stored data.

According to a fifth aspect of the present invention, in the invention of any one of the first to fourth aspects, among the instructions executed by the dedicated hardware, instructions for performing similar processing are classified into a plurality of groups, and The state of executing the instruction of the state machine for controlling the state is controlled independently for each group.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention considers a trade-off between operating speed and cost in implementing a programmable controller that executes an instruction word to which an extended instruction for extending the number of data points and indirectly specifying an address is added. Then, the configuration of FIG. 8 is adopted. Here, the BPU 4 serving as dedicated hardware for executing the extension instruction interprets the processing of the instruction when the ordinary instruction is read and interprets the contents of the instruction together with the subsequent ordinary instruction when the extension instruction is read. Can be executed. Hereinafter, the present invention will be described with reference to embodiments.

(Embodiment 1) This embodiment is shown in FIG.
As shown in (b) and (c), by arranging not only a normal instruction but also a separately defined expansion instruction (Expand) before the normal instruction, it is possible to expand a data area and indirectly specify an address. A dedicated hardware which defines an instruction word, sequentially reads and interprets the instruction word, and realizes a programmable controller having the same configuration as that shown in FIG. 8 using the hardware, controls the BPU 4 in the state shown in FIG. Realized by machine. The meaning of the state used in FIG. 1 is IF: Instruction Fetch (Instruction Fetch) ID: Instruction Decode (Instruction Decode) EX: Execute (Execute), and in FIG. 1 an instruction is read in the IF state (stage) and is read. , After interpreting in the ID state (stage),
If the instruction is an extension instruction, the process returns to the IF state (stage) again to perform a subsequent instruction reading process, interprets the contents of the instruction together with the extension instruction and the subsequent instruction, and executes the processing of the instruction (EX1). , ...). If the read instruction is not an extended instruction (Expand) but a normal instruction, the process proceeds to instruction execution processing such as data reading / writing or arithmetic processing according to the instruction interpretation (decoding) result. In the figure, only a part of the state machine is shown. Since the hardware configuration is the same as that of FIG. 8, reference is made to FIG. 8 and not shown here. (Embodiment 2) In the case of an instruction preceded by an extension instruction as in the present invention, instruction decoding and instruction reading are repeated as described above. In this embodiment, this instruction decoding processing is performed in FIG. As shown by the state transition of the state machine, ID1: processing for judging a normal instruction or an extended instruction ID2: divided into other instruction decoding processing, an instruction is read in the IF1 state (stage), and the instruction decoding state (stage) is read. The execution of the instruction can be speeded up by performing the judgment processing of the normal instruction or the extended instruction with ID1.

As shown in the timing charts at the time of instruction execution in FIGS. 3A and 3B, the configuration using the state machine of FIG. 1 in which the instruction decoding state (stage) is not divided in the case of only ordinary instructions (FIG. 3) 3 (a)) or the configuration in which the instruction decoding state (stage) is divided as in the present embodiment (in the case of FIG. 3 (b)), the instruction execution time does not change. However, when executing an instruction in which an extension instruction is arranged before a normal instruction, in the present embodiment, as shown in FIG. 3E, the first instruction word is read and determined to be an extension instruction. Further, since the operation of reading the instruction word becomes faster, the instruction execution time can be reduced as compared with the case of FIG. 3D using the state machine of FIG. 1 in which the instruction decoding state (stage) is not divided. The hardware configuration is shown in FIG.
Therefore, FIG. 8 is referred to and not shown here.

(Embodiment 3) By the way, B for executing an instruction
Since the PU 4 has only one instruction register for reading an instruction, if the read instruction word is an extension instruction, the information is stored in the BPU 4 and further instructions are read. If you do not store the information that the extension instruction has been read, the contents of the instruction register will be overwritten by the subsequent instruction.However, the information that reads this extension instruction must be cleared every time the first instruction word is read. Even if the currently executed instruction does not precede the extended instruction, if the previously executed instruction is an instruction with an extended instruction, the information of the extended instruction will adversely affect the current instruction execution Will be exerted.

If the information of the extension instruction is unconditionally cleared when the instruction word is read, the extension instruction is cleared by reading the instruction after the extension instruction is read, so that the instruction cannot be executed correctly. . As described above, “extended instruction information must be cleared when the first instruction word is read”. To realize this, a complicated control circuit is configured for instruction word reading and setting and clearing of the extended instruction information. Need arises. Therefore, by executing the instruction reading process of the state machine in two states, one for reading the first word and the other for reading the second and subsequent words, the control circuit of dedicated hardware for executing instructions can be simplified. I do.

The state transition of the state machine that controls the BPU 4 of this embodiment uses the state transition of the state machine shown in FIG. 2 as in the above embodiment. FIG. 4 is a timing chart at the time of executing an instruction according to the present embodiment.

In this embodiment, in the IF1 state (stage) for reading the instruction shown in FIG. 4A or 4C, the extended instruction information is stored in the BPU as shown in FIG. 4B or 4D.
Since the extension instruction information register (not shown) in FIG. 4 is cleared, even in the case of FIGS. 4 (a) and 4 (b) where only the normal instruction is used, the extension instruction of FIGS. Even in this case, the effect of the previous instruction can be canceled at the start of the instruction reading. If the first instruction read as a result of decoding is an extended instruction and it is necessary to read another instruction, IF1
The instruction is read by transiting to the IF2 state (stage) instead of the state (stage), and at this time, the extended instruction information (Expand1) set as a result of the instruction decoding
Is not cleared, the extended instruction information (Expand
The instruction can be executed without error using 1).

When the extension instruction for extending the data area or indirectly specifying the address is read in this way, the information is stored in the extension instruction information register which is a dedicated storage means in the BPU 4. Is stored in the form of the command word as it is, instead of being stored as it is, by converting it into the minimum necessary amount of information that can determine the extension command, the scale of the hardware can be reduced. Here, FIG.
As shown by 0, assuming that the data width of the instruction word is 16 bits and the types of the extended instructions are seven in total, a 16-bit storage location is required to store the instruction word format as it is. An extended instruction can be expressed by a total of 4 bits: 1 bit for the presence or absence of the extended instruction and 3 bits indicating the number of the extended instruction.
Memory location.

"Extended instruction information register" shown in FIG.
Is constituted by the minimum bit width necessary to determine the presence / absence and type of the extension instruction.

(Embodiment 4) By the way, after a command is decoded, an instruction execution process such as data read / write or arithmetic processing is performed according to the decoded content. This is the EX1, EX2 state (stage) shown in the state machine of FIG.
However, the address of the data to be accessed varies depending on the type of the instruction of the programmable controller. Depending on the type of the instruction, the one that does not need to access the memory or the one that only needs to be read from the memory,
There are various types such as one that reads one data and performs arithmetic processing based on it and writes the result to one memory again, and one that reads values of multiple memories and performs arithmetic processing and writes the result to multiple memories. If all of these are executed in the EX1, EX2,... States (stages), the processing per state becomes complicated, and the time required for executing the instructions also increases. Therefore, the instructions of the programmable controller are classified into groups of instructions that perform similar processing by focusing on the state of access to the memory, etc., and the state that executes the instructions of the state machine is independently provided for each group of instructions. In this embodiment, the execution speed of the instruction is improved.

FIG. 5 shows the state transition of the state machine of the present embodiment, and FIG. 6 shows a timing chart for comparing the instruction execution time in the second embodiment with the instruction execution time in the present embodiment.

The state machine of this embodiment is different from the state machine of FIG. 2 in that EX1 and EX after the state D2.
, EXB3,..., EXB1,..., EXB1,.
.., EXC1,...). For this reason, the scale of the state machine is increased, and the scale of the BPU 4 which is dedicated hardware is also increased. On the other hand, since the content of processing executed by one of the EX states (stages) is reduced, only one state (stage) is required. Such time can be reduced. As shown in FIG. 6B, by dividing the instruction into a plurality of groups in accordance with the instruction grouping, the processing related to the EX state (stage) is faster than that in the case shown in FIG. 6A, and as a result, the instruction execution speed is reduced. Can be improved.

[0027]

According to the first aspect of the present invention, there is provided an I / O connected to a control target, a memory for storing a control program and data, and a general-purpose microprocessor for performing at least communication processing, peripheral processing, and execution of application instructions. In addition to special instructions, such as special extended instructions that enable data area expansion and indirect addressing by placing them before normal instructions, basic bit operation instructions, and multi-bit applied instructions, If it is a sequential read, basic bit operation instruction, or multi-bit application instruction, execute the processing of those instructions. If an extended instruction is read, the subsequent normal instruction is also read. In addition, the dedicated hardware that executes the instruction processing after interpreting the instruction content is provided, so it has extended instructions for expanding the data area and indirectly specifying addresses. Instruction word to be able to run faster, and there is an effect that the configuration is also a simple cost is also inexpensive.

According to a second aspect of the present invention, in the first aspect of the present invention, the dedicated hardware is controlled by a state machine, and the process of determining whether the instruction is a normal instruction or an extended instruction from the state in which the instruction is read is changed to an independent state. Because of the separation, there is an effect that it is possible to realize high-speed execution of the instruction preceding the extended instruction.

According to a third aspect of the present invention, in the first aspect of the present invention, the dedicated hardware is controlled by a state machine, and a state in which an instruction is read is a state in which the first word is read and a state in which the first word is read. Since the configuration is made up of a state in which the instruction word is read, it is possible to simplify the instruction reading and the storage processing of the information of the extension instruction, and it is possible to easily design the control circuit.

According to a fourth aspect of the present invention, in the processing for reading an extension instruction according to any one of the first to third aspects,
The content of the read extended instruction is converted into a minimum data amount that can be determined later and stored in an internal dedicated storage unit, and the instruction is executed using the stored data. And the size of a dedicated hardware portion for executing instructions in the programmable controller can be reduced.

According to a fifth aspect of the present invention, in any one of the first to fourth aspects of the present invention, among the instructions executed by the dedicated hardware, instructions for performing similar processing are classified into a plurality of groups, and Since the state of executing the instruction of the state machine for controlling the state is made independent for each group, there is an effect that the instruction execution speed can be improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a state machine that controls dedicated hardware used in a first embodiment.

FIG. 2 is a configuration diagram of a state machine that controls dedicated hardware used in a second embodiment.

FIG. 3 is a timing chart for explaining the above operation.

FIG. 4 is a timing chart for explaining the operation of the third embodiment.

FIG. 5 is a configuration diagram of a state machine that controls dedicated hardware used in a fourth embodiment.

FIG. 6 is a timing chart for explaining the above operation.

FIG. 7 is a configuration diagram illustrating an example of a programmable controller.

FIG. 8 is a configuration diagram showing another example of the programmable controller.

FIG. 9 is a configuration diagram showing another example of a programmable controller.

FIG. 10 is an explanatory diagram of a structure of a command word of the programmable controller.

FIG. 11A is an explanatory diagram of a normal instruction. (B) is an explanatory diagram of a normal instruction and an extended instruction. (C) is an explanatory diagram of a normal instruction and another extended instruction.

[Explanation of symbols]

 IF Instruction reading state (stage) ID Instruction decoding state (stage) EX1,... Execution state (stage)

Claims (5)

[Claims] An I / O connected to an object to be controlled, a memory for storing a control program and data, a general-purpose microprocessor for performing at least communication processing, peripheral processing, and execution of applied instructions, and a general instruction A special extension instruction that enables the data area to be expanded and the address can be indirectly specified by placing it in front of, a basic bit operation instruction, a multi-bit application instruction, etc. If the instruction is an arithmetic instruction or a multi-bit application instruction, execute the processing of those instructions. If an extended instruction is read, the subsequent ordinary instruction is also read, and the contents of the instruction are interpreted together with these extended instructions and ordinary instructions. And a dedicated controller for executing instruction processing. 2. The method according to claim 1, wherein the control of the dedicated hardware is performed by a state machine, and a process of judging whether the instruction is a normal instruction or an extended instruction is separated into an independent state from a state in which the instruction is read. Programmable controller. 3. A state in which the dedicated hardware is controlled by a state machine and an instruction is read out by a first one.
2. The programmable controller according to claim 1, wherein the programmable controller comprises a state for reading a word and a state for reading an instruction word after the second word. 4. A process for reading an extended instruction, converting the content of the read extended instruction into a minimum data amount that can be determined later, storing the converted data in an internal dedicated storage means, and executing the instruction using the stored data. The programmable controller according to any one of claims 1 to 3, wherein the processing is performed. 5. The instructions executed by the dedicated hardware are classified into a plurality of groups for executing similar processing, and the states for executing instructions of a state machine for controlling the dedicated hardware are made independent for each group. The programmable controller according to any one of claims 1 to 4, wherein: